Category Archives: Materials and Equipment

Toshiba Corporation today announced the launch of new embedded NAND flash memory modules integrating NAND chips fabricated with 19nm second generation process technology. The module is fully compliant with the latest e･MMCTM standard, and is designed for application in a wide range of digital consumer products, including smartphones, tablet PCs and digital video cameras. Mass production will start from the end of November.

Demand continues to grow for large density NAND flash memory chips that can support high resolution video and deliver enhanced storage. This is particularly true in the area of embedded memories with a controller function, which minimize development requirements and ease integration into system designs. In its official release, Toshiba said it is meeting this demand by reinforcing its line-up of high density memory products.

The company’s new 32-gigabyte (GB) embedded device integrates four 64Gbit (equal to 8GB) NAND chips fabricated with Toshiba’s 19nm second generation process technology and a dedicated controller into a small package measuring only 11.5 x 13 x 1.0mm. It is compliant with JEDEC e･MMCTM Version 5.0, published by JEDEC in September, and achieves a high read/write performance by applying the new HS400 high speed interface standard.

Toshiba said it plans to bring the NAND chips to a line-up of single-package embedded NAND flash memories in densities from 4GB to 128GB. All will integrate a controller to manage basic control functions for NAND applications.

Following 16GB and 32GB products, Toshiba will release 4GB, 8GB, 64GB and 128GB products in turn.

TOSHIBA_EmbeddedNANDModule_131031

At the recent ECTC conference, various presentations addressed silicon interposers for 2.5D (Shinko), CoWoS reliability (TSMC) and microbumping (imec).

Dr. Phil Garrou, Contributing Editor

Shinko and CEA Leti detailed their presentation entitled “Warpage Control of Silicon Interposer for 2.5D Package Applications.”

Large silicon-interposers when attached to an organic substrate can cause significant warpage problems. Shinko/Leti examined several warpage control techniques including:

  • Using a “chip first process” where chips are mounted on the interposer first vs “chip last process” where the silicon-interposer is mounted on the organic substrate first and chips are mounted onto the interposer last.
  • Using various underfill resins.
  • Using Sn-57Bi solder and thus lowering peak temperature 45-90 degree C. This reduced warpage after reflow to 75% of that using SAC305.

Warpage of silicon-interposer using three types of underfills for 0 level assembly (micro bumps) were investigated. Maximum warpage using U.F. A1, A2 and A3 were 108, 123 and 132mm, respectively. The lowest warpage was obtained at using U.F. A1. With U.F.A3, solder bump open failures were observed. The authors conclude that “using underfill material with low Tg and high storage modulus for 0 level leads to high reliability.”

TSMC and customer Xilinx presented “Reliability Evaluation of a CoWoS-enabled 3D IC Package” which used FEA to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Focus was especially on the fatigue failures of the C4 and BGA joints. Experimental data collected on CoWoS test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme.

Results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid. While a thicker lid has the higher stiffness and better co-planarity, the higher constraint from the thicker lid induces higher stress inside the package which negatively impacts C4 bump fatigue and the micro-bump Ti/Al delamination.

C4 bump layer underfill with Tg of 70°C or 120°C, were studied. The underfill with lower Tg has higher driving force to C4 bump fatigue. When temperature is above Tg, the underfill has much lower Young’s Modulus which has much lower capability to protect C4 bump; and therefore the underfill with lower Tg has higher driving force to C4 bump fatigue. On the contrary, the underfill with lower Tg has lower driving force to Ti/Al delamination in the micro-bump structure. The C4 underfill with lower stiffness can play as a buffer layer and results in lower driving force to Ti/Al delamination in microbump.

imec reported on “Key Elements for Sub-50μm Pitch Micro Bump Processes.” Scaling the microbump pitch from hundreds to a few tens of microns is not straightforward. Several process parameters need to be taken into account to allow a reliable Cu(Ni)Sn ubumping process. One of the challenges for fine pitch Cu(Ni)Sn stacking is to obtain a high bump uniformity. The non-uniformity prevents Cu and Sn from having good contact and subsequent intermetallic formation and increases the risk of underfill entrapment.

A bump scheme that offers better margin for alignment error is better based on a scheme where the size of top die bumps is smaller than the size of the bottom pads. For example it is better to achieve 20μm pitch with 7.5μm bump on 12.5μm pad than with 10μm bump and pad because equal bump and pad diameter can tolerate only 2μm misalignment whereas the 7.5μm/12.5μm bump/pad can tolerate 5μm. This is a significant difference when working close to the stacking tool’s limit of alignment accuracy.

Details on the plasma treatments necessary when attempting to plate into these fine featured plating resists are also discussed.

On 16 October 2013, Carlos Lee, Director General of the European Photonics Industry Consortium (EPIC), moderated a discussion with executives from the UK photonics industry. In conjunction with the Photonex UK exhibition, he approached the discussion from an international perspective of how various regions in the world and countries in Europe support their photonics industry. Mr. Lee filed this report:

While governments need to ensure a supportive legal and regulatory framework for companies to blossom, Anke Lohmann, Director of Photonics at UK government agency ESP KTN (Electronics, Sensors, Photonics Knowledge Transfer Network) pledged for industry engagement and collaboration between companies to address specific needs for ESP KTN to focus on. Mark Sims, Professor at the Space Research Centre of the University of Leicester requested on the other hand for the UK Science budget to be increased as soon as possible “by keeping it flat it is being eroded by inflation putting at risk the UK’s capability for medium and long-term growth”. 

The UK, which has historically been strong in manufacturing but then shifted focus to banking decades ago, wants to go back and rebalance the economy to include manufacturing, which it recognizes is imperative to create jobs, create growth, and avoid stagnation. Photonics will certainly play a role as one of the features of our industry is that it comprises a high proportion of small companies, which anticipate a higher recruitment percentage growth than larger companies. The UK claims 1,500 companies in photonics with a direct employment of 70,000 and a production output of £10.5 billion. This is about 20% of Europe’s total and the UK expertise is well balanced, with a distribution based on employment of Optical Systems (20%), Medical (19%), Production (15%) and Defence (10%). The UK has particular expertise in various fields such as Space, Life Science, Defence, Sensing (food, security, gas), and 3D Advanced Manufacturing. A clear sign of the expertise in the UK in these sectors are the many historical acquisitions such as SPI Lasers by Trumpf, CIP Technologies by Huawei, Barr & Stroud by Thales, Microlase Optical by Coherent and many more such examples. John Lincoln, appointed CEO of the UK Photonics Leadership Group (PLG) said that it was a priority to make a connection between photonics and the higher level of the value chain already being supported by the UK. David Gahan, a photonics industry veteran and currently a consultant, asked the UK TSB (Technology Strategy Board) to “provide follow-on funding into the higher levels of TRL 6-7 (Technology Readiness Level) to support demonstrators.” Remaining competitive requires a company to have access to skilled staff. Malcolm Varnham, Vice President Intellectual Property and Co-Founder of SPI Lasers asked for emphasis on the importance of education and training.

The show itself has much improved, after a dip in 2009 following the banking crisis, the UK’s only “photonics” exhibition has grown to 105 exhibitors, a level not seen for many years. Maybe it was due to a general improvement of the photonics market or because the organisers have added a co-located vacuum technologies exhibition, or the application-related sessions to their programme such as nano and bio-imaging and space applications. The event has also developed a strong Vision UK branding which supports its claim to be the primary European event for vision technology in 2013.

By Sandra Winkler, Senior Industry Analyst, New Venture Research

Small form factor, high speed and performance, and high bandwidth capability with low battery consumption are desired traits for many packaging solutions for integrated circuits (ICs).  High demand for handheld and high performance electronic devices is the driving factor behind the IC packaging needs.

IC packages with an array layout, as opposed to a perimeter layout, allow for more I/O density in a smaller form factor, meeting the needs outlined above.  Thus demand for array packages is on the rise, as additional I/O connections are fit beneath the package than traditional leadframe packages, providing them with form factor benefits.  BGA and FBGA package solutions also reach into I/O levels which are unreachable by traditional leadframe packages, as the substrate can be enlarged to fit a large number of solder balls, land pads, or columns beneath it to attach to the PCB.

Array packages include the PGA, BGA, FBGA, Fan-in QFN, and Fan-out WLPs.  The pin grid array, or PGA, is a through-hole package with pins which attach it to the PCB.  The other packages have more options.

BGA / FBGA

Ball grid arrays (BGAs) and their smaller cousins, fine-pitched ball grid arrays (FBGAs) generally have solder balls on the underside of the substrate for attachment to the printed circuit board (PCB).  The balls provide a self-centering effect during reflow, as well as a standoff for flexibility during electrical surges.

Removing these solder balls makes these packages land grid arrays, or LGAs, which allow for a shorter package in the “z” dimension.  This is important in thinner products, although the package placement to the PCB must be of greater accuracy and thus have a slower throughput.

Columns can take the place of solder balls, which allow for finer pitch and greater density of I/O connections.  These are known as column grid arrays, or CGAs.  These are more expensive to produce than the BGA or LGA package solutions.

The forecasts of each of these segments are provided in New Venture Research’s newly published report, The Array IC Packaging Market, 2013 Edition.

Fan-In QFN Package Solutions

The quad flatpack no-lead, or QFN, is a newer package introduced onto the market in 2008.  A new twist has been added to the QFN to add additional rows to this leadframe package, turning it into a leadframe version of an array package, and one that can reach even further into the market which would otherwise be covered by the larger QFP.  Additional rows are “fanned in” from the traditional perimeter-style leadframe, making this package unique.

Demand for both the traditional QFN and Fan-in QFNs are on the rise, shown in Table 1.

Table 1 Fan-In QFN

 

2012

2013

2014

2015

2016

2017
QFN Percentage of Total IC Packages

12.4%

12.7%

13.2%

13.8%

14.4%

14.8%
Growth Rate of Fan-In QFN and QFP

184.5%

15.4%

25.9%

11.9%

10.5%

9.9%
As a Percentage of Total QFN Market

3.4%

3.6%

4.1%

4.2%

4.3%

4.3%

Fan-Out WLPs

Wafer Level Packages, or WLPs, are the smallest package solution on the market, being die sized.  This unique package is formed while the die are still part of an uncut wafer, the only package to be created or assembled in this manner.  WLPs are array packages by nature, but since all the solder balls or bumps then must fit beneath the die itself, this limits the number of I/O which is on these packages.

The solution to this is the Reconfigured or Fan-out wafer-level packages (Fan-out WLP), for which the available surface available for I/O interface to the PCB is expanded beyond the perimeter of the die by virtue of a backside overmold.  All these processes are done on an uncut wafer, so that manufacturing efficiencies are maximized.

Like the Fan-in QFN, demand for both the WLP and the Fan-out WLP are on the rise.  This is displayed in Table 2.

Table 2 Fan-Out WLP

 

2012

2013

2014

2015

2016

2017
WLP Percent of WW IC Packaging Market

5.3%

5.5%

5.7%

5.9%

6.0%

6.1%
Growth Rate for Fan-out WLPs

60.1%

19.0%

17.0%

16.6%

6.8%

6.1%
Fan-out WLP Percent of total WLPs

9.5%

10.1%

10.8%

11.5%

11.7%

11.6%

InGaAs is a promising channel material for high-performance, ultra low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration.

Transistors with high mobility channels will likely be required for the 10nm and 7nm device generations, scheduled to go into production in 2016/2016 and 2017/2018, respectively. InGaAs is a good candidate for NFETS, while germanium is the candidate of choice for PFET devices.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 8-11 in Washington, D.C., a research team led by Japan’s AIST will describe how they built triangular InGaAs-on-insulator n-MOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 µA/µm at a 300nm gate length, showing they have great potential.

 

Triangular transistors produced with MOVPE demonstrate a high on-current of 930 µA/µm at a 30nm gate length.

Triangular transistors produced with MOVPE demonstrate a high on-current of 930 µA/µm at a 30nm gate length.

The National Institute of Advanced Industrial Science and Technology (AIST) is a public research institution largely funded by the Japanese government. About 2300 researchers (about 2050 with tenure: about 80 from abroad) and a few thousands of visiting scientists, post-doctoral fellows, and students from home and abroad are working at AIST.  About 650 permanent administrative personnel and many temporary staff support research works of AIST.

Blog Review October 14 2013


October 14, 2013

At the recent imec International Technology Forum Press Gathering in Leuven, Belgium, imec CEO Luc Van den hove provided an update on blood cell sorting technology that combines semiconductor technology with microfluidics, imaging and high speed data processing to detect tumorous cancer cells. Pete Singer reports.

Pete Singer attended imec’s recent International Technology Forum in Leuven, Belgium. There, An Steegan, senior vice president process technology at imec, said FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019). In DRAM, the MIM capacitor will give way to the SST-MRAM. In NAND flash, 3D SONOS is expected to dominate for several generations; the outlook for RRAM remains cloudy.

At Semicon Europa last week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

Phil Garrou reports on developments in 3D integration from Semicon Taiwan. He notes that at the Embedded Technology Forum, Hu of Unimicron looked at panel level embedded technology.

Kathryn Ta of Applied Materials connects how demand for mobile devices is driving materials innovation. She says that about 90 percent of the performance benefits in the smaller (sub 28nm) process nodes come from materials innovation and device architecture. This number is up significantly from the approximate 15 percent contribution in 2000.

Tony Massimini of Semico says the MEMS market is poised for significant growth thanks to major expansion of applications in smart phone and automotive. In 2013, Semico expects a total MEMS market of $16.8 B but by 2017 it will have expanded to $28.5 B, a 70 percent increase in a mere four years time.

Steffen Schulze and Tim Lin of Mentor Graphics look at different options for reducing mask write time. They note that a number of techniques have been developed by EDA suppliers to control mask write time by reducing shot count— from simple techniques to align fragments in the OPC step, to more complex techniques of simplifying the data for individual writing passes in multi-pass writing.

If you want to see SOI in action, look no further than the Samsung Galaxy S4 LTE. Peregrine Semi’s main antenna switch on BSOS substrates from Soitec enables the smartphone to support 14 frequency bands simultaneously, for a three-fold improvement in download times.

Vivek Bakshi notes that a lot of effort goes into enabling EUV sources for EUVL scanners and mask defect metrology tools to ensure they meet the requirements for production level tools. Challenges include modeling of sources, improvement of conversion efficiency, finding ways to increase source brightness, spectral purity filter development and contamination control. These and other issues are among topics that were proposed by a technical working group for the 2013 Source Workshop in Dublin, Ireland.

By Lara Chamness, senior manager, market analysis, SEMI

Given the industry’s anemic performance during the first part of the year, a number of analysts have recently downgraded their 2013 semiconductor revenue forecasts to low-single digits, while forecasting stronger growth in 2014. SEMI believes that the semiconductor materials market will trend with the device market, resulting in an increase of one percent this year and a seven percent increase in 2014, resulting in a materials market approaching $50 billion in 2014.

Looking at materials trends by region, Japan has traditionally been the largest semiconductor materials consuming region owing to its significant fab base and packaging presence. Over the past four years, manufacturers in the region rapidly adopted a fab-lite strategy or have consolidated many of their fabs and packaging plants. During this same time, companies based in Taiwan invested heavily in advanced packaging and foundry operations.

In the 2009 downturn, the materials market contracted 22 percent in Japan, while falling only 12 percent in Taiwan. Immediately out of the downturn, all regional materials markets enjoyed strong gains and by 2011 the Taiwan market surged ahead Japan, resulting in Taiwan becoming the largest semiconductor materials consuming region in terms of revenue. Rest of World, primarily SE Asia, represents the third largest market for semiconductor materials given the dominance of packaging in the region. For this year and the next, Taiwan will strengthen its lead, with Rest of World’s materials market to exceed Japan’s next year (Figure 1) due to continued strength in its packaging materials market.

Figure 1. Semiconductor materials market forecast by region. Source: SEMI Materials Market Data Subscription, August 2013.

Figure 1. Semiconductor materials market forecast by region. Source: SEMI Materials Market Data Subscription, August 2013.

It is interesting to note that in spite of many Japanese device manufacturers opting for a fab-lite strategy and/or consolidating, Japan still represents one of the largest regional markets for fab materials. This should not be surprising considering that fabs located in Japan currently account for about 22 percent of global IC fab capacity, followed by South Korea with 21 percent, Taiwan with 19 percent and North America with 15 percent (Source: SEMI World Fab Forecast database, August 2013). As a result, the wafer fab materials market roughly mirrors IC fab capacity (Figure 2).

Figure 2. 2013F wafer fabrications materials market by region. Source: SEMI Materials Market Data Subscription, August 2013.

Figure 2. 2013F wafer fabrications materials market by region. Source: SEMI Materials Market Data Subscription, August 2013.

Given current growth expectations for the semiconductor market, SEMI is forecasting that semiconductor materials will increase 1 percent this year and 7 percent in 2014. Taiwan now dominates the semiconductor materials market as the result of its aggressive foundry and advanced packaging presence. Japan still represents a significant portion of the global materials market owing to its historical manufacturing strength but it is expected that Rest of World, primarily SE Asia, will surpass the Japan market next year as the Rest of World region grows at a stronger rate due to continued strength in its packaging materials market.

To learn more about semiconductor materials and key market trends, register to attend the SEMI Strategic Materials Conference, which will be held at the Santa Clara Marriott, in Santa Clara, California on October 16-17. For more information about SEMI, visit www.semi.org.

 Dow Electronic Materials, a business unit of The Dow Chemical Company, today announced availability of its SOLDERON BP TS 6000 Tin-Silver Plating Chemistry for use in lead-free solder bump plating applications. This next-generation formulation features enhanced plating performance, bath stability and ease-of-use, thereby enabling the industry’s widest process window with the most robust process flexibility and a competitive cost of ownership.

“As flip chip packages become mainstream and the industry continues to move toward 2.5D and 3D packaging technologies, there is a clear market requirement for high-performance lead-free alternatives for plating applications,” said Dr. Robert Kavanagh, global business director, Advanced Packaging Metallization, for Dow Electronic Materials. “Customers need materials optimized for today’s finer bump geometries. This new chemistry achieves significant performance improvements, delivering even faster plating speeds, better uniformity and smoother surface morphology in addition to a smooth, void-free interface when used together with Dow’s and other leading copper (Cu) pillar formulations.”

In Cu pillar capping applications, SOLDERON™ BP TS 6000 Tin-Silver forms a smooth,micro-void free interface post reflow.

In Cu pillar capping applications, SOLDERON™ BP TS 6000 Tin-Silver forms a smooth,micro-void free interface post reflow.

With a single formulation, SOLDERON BP TS 6000 Tin-Silver (SnAg) is capable of plating speeds ranging from 2 to 9 um/min., which creates a significantly wider operating window when compared with other solutions in the marketplace. The tunable nature of the Ag composition in this formulation makes it suitable for a number of applications and eliminates the need to change the chemistry to address different processing requirements. The new chemistry has proven to be robust enough for both bumping and capping of a wide range of patterned wafers and it is not restricted for use with specific photoresists. It exhibits with-in die (WID) uniformity after reflow of <5% over a wide range of wafer types, which demonstrates its suitability for high-volume manufacturing. Additionally, it is macro- and micro-void free after reflow for improved yields and reliability.

“One of the most compelling strengths of SOLDERON BP TS 6000 Tin-Silver is the product’s enormous flexibility, which allows it to perform exceptionally well in a variety of applications from in-via and mushroom bumping to Cu and micro-Cu pillar capping,” added Kavanagh.

SOLDERON BP TS 6000 Tin-Silver plating bath has proven to be both electrolytically and thermally stable, which contributes to the chemistry’s competitive COO. Offering an electrolytic bathlife of >100 Ah/L and a ≥6-month pot life, it is compatible with in-line metrology processes, for superior ease-of-use.

GE acquires Imbera


September 26, 2013

GE Healthcare Finland Oy, in partnership with GE Idea Works, announced today that it has completed the acquisition of Imbera Electronics Oy, a pioneering Finnish company that has spent over 10 years developing advanced embedded electronics packaging technology and manufacturing solutions.  Financial terms of the transaction were not disclosed.

Embedded electronic packaging technologies can reduce the size and cost of components used in digital electronics by over 50 percent, enabling much higher integration for increasingly feature-rich consumer products such as smartphones and tablets.  This embedded packaging is also used in advanced avionics, power distribution and a variety of other applications.

“We are extremely pleased to add the cutting edge technology and intellectual property of Imbera Electronics Oy as a component of GE’s existing electronics packaging portfolio,” said Larry Davis, vice president and microelectronics packaging program director at GE Idea Works.

Risto Tuominen, CEO and founder of Imbera Electronics Oy, commented that “Combining the high volume-focused and cost effective embedded technology from Imbera with the advanced thermal and power handling capability of GE creates the most compelling technology platform for advanced high density electronics packaging.”

This acquisition expands and extends GE’s position in advanced electronics and electronics packaging and creates one of the most extensive intellectual property and technology portfolios for embedded electronic packaging in the world, covering applications from low-power consumer products to high-power industrial electronics. GE plans to continue developing and licensing the Imbera Electronics Oy intellectual property and technology portfolio in combination with its established power overlay portfolio.

Next-generation integrated devices for matching, filtering and protection help shrink circuit size and boost end-product performance. STMicroelectronics is revealing new families of these dimension-shrinking devices.

The latest advanced devices joining ST’s micro-package families include the world’s smallest single-line Transient-Voltage Suppressor, the ESDAVLC6-1BV2, in a 01005 surface-mount package to protect sensitive circuitry against hazardous voltage surges. ST is also introducing the first five members of its new ECMF family of common-mode filters embedding ESD protection. These are built using advanced silicon technology and are offered in ultra-thin packages only 0.55mm high.

Another new member of ST’s IPD (Integrated Passive Device) family, the BAL-NRF01D3 ultra-miniature wireless balun, has already enabled ST’s customers to boost the performance of their low-power wireless solutions and save up to 90 percent of the pc-board space occupied by discrete antenna-matching and harmonic-filtering components.

ST said in its official release that its technologies leverage advanced component-fabrication technologies to combine into a single device multiple circuit elements including resistors, capacitors, inductors and ESD diodes that are otherwise typically implemented as individual components on the pc-board. In this way, ST’s integrated devices eliminate multiple components and the interconnections between them, resulting in a large net saving in pc-board area. Designers can use them to create smaller end-products, increase functionality by designing-in extra ICs, simplify PCB layout and shorten time-to-market for new products.

Additionally, ST’s integrated devices deliver better performance than equivalent discrete devices, as they are produced using semiconductor processes that display greater quality, reliability and process control. Component values have closer tolerances and reduced variation over time compared with conventional devices such as Metal-Oxide Varistors (MOVs), Low-Temperature Co-fired Ceramic (LTCC) devices and general-purpose passive components. These advantages allow customers to improve the quality of their products and the perception of their brand.

The BAL-NRF01D3 is in mass production in a 5-bump flip-chip package, priced from $0.18 for orders over 5,000 units. The ECMF common-mode filters are also in mass production, priced from $0.16 (ECMF02-2BF3) for orders over 1,000 units. The ESDAVLC6-1BV2 Transient-Voltage Suppressor is priced from $0.10 for orders over 1,000 units.