Category Archives: Materials and Equipment

A wide array of package level integration technologies now available to chip and system designers are reviewed.

As technical challenges to shrink transistors per Moore’s Law become increasingly harder and costlier to overcome, fewer semiconductor manufacturers are able to upgrade to the next lower process nodes (e.g., 20nm). Therefore various alternative schemes to cram more transistors within a given footprint without having to shrink individual devices are being pursued actively. Many of these involve 3D stacking to reduce both footprint and the length of interconnect between the devices.

A leading memory manufacturer has just announced 3D NAND products where circuitry are fabricated one over the other on the same wafer resulting in higher device density on an area basis without having to develop smaller transistors. However such integration may not be readily feasible when irregular non-memory structures, such as sensors and CPUs, are to be integrated in 3D. Similar limits would also apply for 3D integration of devices that require very different process flows, such as analog with digital processor and memory.

For applications where integration of chips with such heterogeneous designs and processes are required, integration at the package level becomes a viable alternative. For package level integration, 3D stacking of individual chips is the ultimate configuration in terms of reducing footprint and improving performance by shrinking interconnect length between individual chips in the stack. Such packages are already in mass production for camera modules that require tight coupling of the image sensor to a signal processor. Other applications, such as 3D stacks of DRAM chips and CPU/memory stacks, are under development. For these applications 3D modules have been chosen so as to reduce not just the form factor but also the length of interconnects between individual chips.

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Figure 1: Equivalent circuit for interconnect between DRAM and SoC chips in a PoP package.

Interconnects a necessary evil

To a chip or system designer the interconnect between transistors or the wiring between chips is a necessary evil. They introduce parasitic R, L and C into the signal path. For die level interconnects this problem became recognized at least two decades ago as RC delay in such interconnects for CPUs became a roadblock to operation over 2GHz. This prompted major changes in materials for wafer level interconnects. For the conductors, the shift was from aluminum to lower resistance copper which enabled a shrink in geometries. For the surrounding interlayer dielectric that affect the parasitic capacitance, silicon dioxide was replaced by various low and even ultra low k ( dielectric constant ) materials, in spite of their poorer mechanical properties. Similar changes were made even earlier in the chip packaging arena when ceramic substrates were replaced by lower– k organic substrates that also reduced costs. Interconnects in packages and PCBs too introduce parasitic capacitance that contributes to signal distortion and may limit the maximum bandwidth possible. Power lost to parasitic capacitance of interconnects while transmitting digital signals through them depend linearly on the capacitance as well as the bandwidth. With the rise in bandwidth even in battery driven consumer electronics, such as smart phones, power loss in the package or PCBs becomes ever more significant (30%) as losses in chips themselves are reduced through better design (e.g., ESD structures with lower capacitance ).

Improving the performance of package level interconnects

Over a decade ago the chip packaging world went through a round of reducing the interconnect length and increasing interconnect density when for high performance chips such as CPUs, traditional peripheral wirebond technology was replaced by solder-bumped area-array flip chip technology. The interconnect length was reduced by at least an order of magnitude with a corresponding reduction in the parasitics and rise in the bandwidth for data transfer to adjacent chips, such as the DRAM cache. However, this improvement in electrical performance came at the expense of mechanical complications as the tighter coupling of the silicon chip to a substrate with a much larger coefficient of thermal expansion (6-10X of Si ) exposed the solder bump interconnects between them to cyclic stress and transmitted some stress to the chip itself. The resulting Chip Package Interaction (CPI) gets worse with larger chips and weaker low-k dielectrics on the chip.

The latest innovation in chip packaging technology is 3D stacking with through silicon vias (TSVs) where numerous vias (5µm in diameter and getting smaller) are etched in the silicon wafer and filled with a conductive metal, such as Cu or W. The wafers or singulated chips are then stacked vertically and bonded to one another. 3D stacking with TSVs provides the shortest interconnect length between chips in the stack, with improvements in bandwidth, efficiency of power required to transmit data, and footprint. However, as we shall see later, the 3D TSV technology is delayed not only because of complex logistics issues that are often discussed, but actual technical issues rooted in choices made for the most common variant: TSVs filled by Cu, with parallel wafer thinning.

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Figure 2: Breakdown of capacitance contributions from various elements of intra-package interconnect in a PoP. The total may exceed 2 pF.

Equivalent circuit for packages

PoP (package-on-package) is a pseudo-3D package using current non-TSV technologies and are ubiquitous in SmartPhones. In a PoP, two packages (DRAM and SoC) are stacked over one another and connected vertically by peripheral solder balls or columns. The PoP package is often talked about as a target for replacement by TSV-based 3D stacks. The SoC to DRAM interconnect in the PoP has 4 separate elements (wirebond in DRAM package, vertical interconnect between the top and bottom packages, substrate trace and flip chip in bottom package for SoC) in series. The equivalent circuit for package level interconnect in a typical PoP is shown in FIGURE 1.

From FIGURE 2 it is seen that interconnect capacitance in a PoP package is dominated by not just wire bonds (DRAM) but the lateral traces in the substrate of the flip chip package (SoC) as well. Both of these large contributions are eliminated in a TSV based 3D stack.

In a 3D package using TSVs the elimination of substrate traces and wire bonds between the CPU and DRAM leads to a 75% reduction in interconnect capacitance (FIGURE 3) with consequent improvement in maximum bandwidth and power efficiency.

Effect of parasitics

Not only do interconnect parasitics cause power loss during data transmission but they also affect the waveform of the digital signal. For chips with a given input/output buffer characteristics, higher capacitance slows down the rise and falling edges [1,2]. Inductance causes more noise and constricts the eye diagram. So higher interconnect parasitics limit the maximum bandwidth for error free data transmission through a package or PCB.

TSV-based 3D stacking

As has been previously stated, a major reason for developing TSV technology is to use it to improve data transmission – measured by bandwidth and power efficiency — between chips and go beyond bandwidth limits imposed by conventional interconnect. Recently a national Lab in western Europe has reported results [3] of stacking a single DRAM chip to a purpose-designed SoC with TSVs in a 4 x 128 bit wide I/O format and at a clock rate of just 200MHz. They were able to demonstrate a bandwidth of 12.8 MB/sec (2X that in a PoP with LP DDR3 running at 800MHz). Not surprisingly the power efficiency for data transfer reported (0.9 pJ/bit) was only a quarter of that for the PoP case.

Despite a string of encouraging results over the last three years from several such test vehicles, TSV-based 3D stacking technology is not yet mature for volume production. This is true for the TSV and manufacturing technology chosen by a majority of developers, namely filling the TSVs with copper and thinning the wafers in parallel but separately which requires bonding/debonding to carrier wafers. The problems with filling the TSVs with copper have been apparent for several years and affect electrical design [4]. The problem arises from the large thermal expansion mismatch between copper and silicon and the stress caused by it in the area surrounding copper-filled TSVs, which alters electron mobility and circuit performance. The immediate solution is to maintain keep-out zones around the TSVs, however this affects routing and the length of on-die interconnect. Since the stress field around copper-filled TSVs depend on the square of the via diameter, smaller diameter TSVs are now being developed to shrink the keep out zone.

Only now the problems of debonding thinned wafers with TSVs, such as fracturing, and subsequent handling are being addressed by development of new adhesive materials that can be depolymerized by laser and thinned wafers removed from the back-up without stress.

The above problems were studied and avoided by the pioneering manufacturer of 3D memory stacks. They changed via fill material from copper to tungsten, which has a small CTE mismatch with copper, and opted for a sequential bond/thin process for stacked wafers thereby totally avoiding any issues from bond/debond or thin wafer handling.

It is baffling why such alternative materials and process flows for TSVs are not being pursued even by U.S. based foundries that seem to take their technical cues instead from a national laboratory in a small European nation with no commercial production of semiconductors!

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Figure 3: When TSVs (labeled VI) replace the conventional interconnect in a PoP package, the parasitic capacitance of interconnect between chips, such as SoC and DRAM, is reduced by 75%.

Options for CPU to memory integration

Given the delay in getting 3D TSV technology ready at foundries, it is normal that alternatives like 2.5D, such as planar MCMs on high density silicon substrates with TSVs, have garnered a lot of attention. However the additional cost of the silicon substrate in 2.5D must be justified from a performance and/or foot-print standpoint. Interconnect parasitics due to wiring between two adjacent chips in a 2.5D module are significantly smaller than that in a system built on PCBs with packaged chips. But they are orders of magnitude larger than what is possible in a true 3D stack with TSVs. Therefore building a 2.5D module of CPU and an adjacent stack of memory chips with TSVs would reduce the size and cost of the silicon substrate but won’t deliver performance anywhere near an all TSV 3D stack of CPU and memory.

integration_table

Alternatives to TSVs for package level integration

Integrating a non-custom CPU to memory chips in a 3D stack would require the addition of redistribution layers with consequent increase in interconnection length and degradation of performance. In such cases it may be preferable to avoid adding TSVs to the CPU chips altogether and integrate the CPU to a 3D memory stack via a substrate in a double-sided package configuration. The substrate used is silicon with TSVs and high-density interconnects. Test vehicles for such an integration scheme have been built and electrical parameters evaluated [5,6]. For cost driven applications e,g. Smart Phones the cost of large silicon substrates used above may be prohibitive and the conventional PoP package may need to be upgraded. One approach to do so is to shrink the pitch of the vertical interconnects between the top and bottom packages and quadruple the number of these interconnects and the width of the memory bus [7,8]. While this mechanical approach would allow an increase in the bandwidth, unlike TSV based solutions they would not reduce the I/O power consumption as nothing is done to reduce the parasitic capacitance of the interconnect previously discussed (FIGURE 3).

A novel concept of “Active Interconnects” has been proposed and developed at APSTL. This concept employs a more electrical approach to equal the performance of TSVs [1] and replace these mechanically complex intrusions into live silicon chips. Compensation circuits on additional ICs are inserted into the interconnect path of a conventional PoP package for a Smart Phone (FIGURE 4) to create the SuperPoP package with Bandwidth and Power efficiency to approach that of TSV-based 3D stacks without having to insert any troublesome TSVs into the active chips themselves.

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Figure 4: Cross-section of a APSTL Super POP package under development to equal performance of TSV based 3D stacks. Integrated circuit with compensation circuits for ea. interconnect is inserted between the two layers of a PoP for SmartPhones. This chip contains through vias and avoids insertion of TSVs in high value dice for SoC or DRAM.

Conclusion
A wide array of package level integration technologies now available to chip and system designers have been discussed. The performance of package level interconnect has become ever more important for system performance in terms of bandwidth and power efficiency. The traditional approach of improving package electrical performance by shrinking interconnect length and increasing their density continues with the latest iteration, namely TSVs. Like previous innovations, TSVs too suffer from mechanical complications, only now more magnified due to stress effects of TSVs on device performance. Further development of TSV technology must not only solve all remaining problems of the current mainstream technology – including Cu-filled vias and parallel thinning of wafers — but also simplify the process where possible. This includes adopting more successful material (Cu-capped W vias) and process choices (sequential wafer bond and thin) already in production. In the meantime innovative concepts like Active Interconnect that altogether avoids using TSVs and APSTL SuperPoP using this concept show promise for cost-driven power-sensitive applications like smart phones. •

References
Gupta, D., “A novel non-TSV approach to enhancing the bandwidth in 3D packages for processor- memory modules “, IEEE ECTC 2013, pp 124 – 128.

Karim, M. et al , “Power Comparison of 2D, 3D and 2.5D Interconnect Solutions and Power Optimization of Interposer Interconnects,” IEEE ECTC 2013, pp 860 – 866.

Dutoit, D. et al, “A 0.9 pJ/bit, 12.8 GByte/s WideIO Memory Interface in a 3D-IC NoC-based MPSoC,” 2013 Symposium on VLSI Circuits Digest of Technical Papers.

Yang, J-S et al, “TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization,” Design Automation Conference (DAC), 2010 47th ACM/IEEE , June 2010.

Tzeng, P-J. et al, “Process Integration of 3D Si Interposer with Double-Sided Active Chip Attachments,” IEEE ECTC 2013, pp 86 – 93.

Beyene, W. et al, “Signal and Power Integrity Analysis of a 256-GB/s Double-Sided IC Package with a Memory Controller and 3D Stacked DRAM,” IEEE ECTC 2013, pp 13 – 21.

Mohammed, I. et al, “Package-on-Package with Very Fine Pitch Interconnects for High Bandwidth,” IEEE ECTC 2013, pp 923 – 928

Hu, D.C., “A PoP Structure to Support I/O over 1000,” ECTC IEEE 2013, pp 412 – 416

DEV GUPTA is the CTO of APSTL, Scottsdale, AZ ([email protected]).

Packaging at The ConFab


September 18, 2013

At The ConFab conference in Las Vegas in June, Mike Ma, VP of Corporate R&D at Siliconware (SPIL), announced a new business model for interposer based SiP’s, namely the “turnkey OSAT model.” In his presentation “The expanding Role of OSATS in the Era of System Integration,” Ma looked at the obstacles to 2.5/3D implementation and came up with the conclusion that cost is still a significant deterrent to all segments.

By Dr. Phil Garrou, Contributing Editor

Over the past few years, TSMC has been proposing a turnkey foundry model which has met with significant resistance from their IC customers. Under the foundry turnkey model, the foundry handles all operations including chip fabrication, interposer fabrication, assembly and test. Foundry rivals UMC and GlobalFoundries, have been supporting an OSAT/Foundry collaboration model where the foundries would fabricate the chips with TSV and the OSATs would do assembly of chips and interposers that could come from several different sources.

packaging
FIGURE 1. Amkor’s “possum” stacking technology.

SPIL is the first OSAT to propose this OSAT centric model where the interposer is fabricated by the OSAT who then assembles and tests modules made with chips from multiple sources. The impediment to this route in the past has been the lack of OSAT capability to fabricate the fine pitch interposers which require dual damascene processing capability, which until now was only available in the foundries. This week SPIL announced the equipment for fine pitch interposer capability (>2 layers, 0.4-3µm metal line width and 0.5µm TSV) has been purchased and is in place.

Ma indicates that while the foundries are not happy with this SPIL proposal, their customers, especially their fabless customers have been very supportive. He feels the inherent lower cost structure of OSATS will have a positive impact on the 2.5/3D market which has been somewhat stagnant since the FPGA and memory product announcements in 2010.

Also presenting at The ConFab: Bob Lanzone, Senior VP of Engineering Solutions for Amkor. He, like the other OSATS, sees smartphones and tablets driving the market moving forward.

Amkor’s update on Copper Pillar technology indicates an expected doubling in demand this year and continued expansion into “all flip chip products”. Their “TSV status” takes credit for being the first into production with TSMC and Xilinx.

Looking at the 2.5D TSV and interposer supply chain they see different requirements for high end, mid-range and lower cost products. For high end, such as networking and servers, silicon interposers are needed with < 2µm L/S, 25k μbumps per die. Amkor is engaged with foundries to deliver silicon interposers today.

For mid-range products, such as gaming, graphics, HDTV, and tablets, silicon or Glass interposers are need with < 3µm L/S, < 25ns latency and ~10k μbumps/die. Amkor is not actively pursuing glass interposers yet as the infrastructure is still immature.

For lower cost products, such as lower end tablets and smart phones, silicon, glass or laminate interposers are needed, with < 8um L/S, low resistance and ~2k μbumps per die. Lazone said a cost reduction path must be provided to enable this sector, and they are working with the laminate supply chain to do that. They are targeting 2014 for their “possum” stacking as shown in FIGURE 1. •

Brewer Science, a supplier of specialty materials and integrated solutions for microelectronics device fabrication, announced today that the next generation of carbon nanotube materials, the CNTRENE 1020 material series, is officially qualified for NRAM nanotube random access memory device manufacturing by Nantero Inc.

NRAM memory is a high-density, non-volatile memory technology invented by Nantero to serve as a universal memory device, which can replace flash, DRAM, and others in embedded and stand-alone memory applications.  Brewer Science is a licensed supplier of CMOS-grade carbon nanotube solutions utilizing processes developed by Nantero for use in the manufacture of NRAM devices.

The next generation of CNTRENE materials manufactured by Brewer Science provides an increased concentration of CNTs in solution, with lower ion content (<10 ppb) and extended stability for use in standard coater track systems. This new generation of Brewer Science CNT materials allows for reduced process costs and improved on-wafer coating performance, consistent with the company’s focus on integrated solutions.

“We are pleased to announce that our next generation of CNTRENE materials has been qualified with regard to the strict standards of NRAM production,” said Jim Lamb, Business Development Director, Carbon Electronics Center. “We are determined to support the commercial opportunities for CNTRENE materials and are looking forward to successful adoption of CNTs in non-volatile memory applications through our partnership with Nantero,” he added.

Brewer Science will present these advancements in CNTRENEmaterials for NRAM manufacturing at the FUJIFILM Advanced Lithography Workshop in Dresden, Germany on September 13, 2013.

Pitching for IC packages


September 13, 2013

By Sandra L. Winkler, New Venture Research

Itty bitty computers, smart phones, ipods, and more – these “must have” small electronic devices that Apple Computer and other companies have popularized, are forcing the hand of IC package designers to shrink the package to fit within these little hand-held gadgets.

Shrinking the package can be a challenge, as is routing these devices to a PCB.  Creative package designs, such as stacked packages, SiPs, and interconnection methods of through silicon vias (TSVs) are all being put into play to achieve a small footprint, enhanced electrical performance, while consuming less battery power.  Information on those technologies can be found in New Venture Research’s Advanced IC Packaging, Technologies, Materials, and Markets, 2012 Edition.

Package Pitch

Another method of reducing the form factor and reduced signal length is to reduce the package pitch, or the distance between the center of one second-level interconnect to the other as the interconnect to the printed circuit board (PCB).  The package pitch of a device, combined with the I/O count, will determine the size of a package substrate or leadframe, the test socket size, and the footprint of the device on a PCB.

Reducing the pitch on an IC package often results in smaller solder balls on an array package, and will require that the electrical traces to the package on the PCB be closer together.

When a package pitch is altered, this will in turn have an effect on the PCB layout, the solder ball size where applicable and volume of solder paste, the test socket and DUT board, and all the parts used to make the package itself.

When combining the total packages together, the pitch of 0.4 mm has the largest growth of all the pitch sizes, while the 0.5-mm pitch comprises the largest single package pitch. Figure 1 displays the percentages of these pitches for the years 2012 versus 2017.

Figure 1 Total IC Package Pitch Forecast, 2012 vs. 2017 (Click to view full screen.)

Figure 1 Total IC Package Pitch Forecast, 2012 vs. 2017
(Click to view full screen.)

Advanced packaging of semiconductor chips has emerged as a key enabler in many of today’s electronic system products.  Put another way, package selection is increasingly important to the success of the end product.  While much attention with regard to IC packaging is on 3D stacking and integration technologies, there is another area of packaging that has quietly been flourishing during the past decade-and-a-half.

Introduced in 1998, the quad flat no-lead (QFN) package design (including the related dual-sided DFN) has enjoyed phenomenal growth from the very beginning.  With its low cost, small size, and excellent thermal and electrical performance characteristics, the QFN quickly became the mainstream package of choice for many low-to-medium I/O count ICs.  In the past decade, new dual-row and even triple-row technologies have enabled QFNs to support many more I/Os and, thus, enter a wider range of IC product segments.  Today, the QFN is one of, if not the, most widely used IC package types.

IC Insights forecasts that the continuous high growth in demand for QFN-type packages will help push the flatpack/chip carrier (FP/CC) category of packages past the “old” small outline (SO) group of packages for the first time ever in 2013 (see Figure 1).  The QFN is a type of chip carrier.  The SO packages emerged in the early 1980s and then grew to become the industry’s most widely used package type by 1995.  The FP/CC packages emerged around the same time and they offered higher I/O capabilities than the SO packages because they had leads on all four sides.

The QFN package category in the JEDEC standards includes a variety of manufacturer-specific designs such as the MicroLeadFrame (MLF) package from Amkor, Fujitsu’s Bumped Chip Carrier (BCC) and small outline no-lead (SON) packages, Carsem’s Micro Leadframe Package (MLP), and ASE’s microchip carrier (MCC).  There are similar JEDEC standards for DFN packages that have external bond pads or “lands” on two sides instead of four like the QFN.  Besides being categorized in the FP/CC group of packages, QFNs and DFNs are also considered part of a larger group of packages called leadframe CSPs, or chip-scale packages.

chip carrier

Figure 1

QFN and DFN packages are inexpensive to manufacture—they typically don’t have solder balls, are targeted at low-I/O applications (typically <85), and make use of pre-plated leadframes.  Either wirebonds or flip-chip bumps are used to attach the IC to the leadframe.  Versions like the MLF and BCC have an exposed die-attach paddle on the bottom of the package, which serves as an excellent thermal path away from the chip as well as a good ground-plane if the pad is grounded on the circuit board.  That, in conjunction with the high electrical performance offered by short I/O connections, has made these leadframe CSPs attractive for use in packaging RF circuits for cellphones and other wireless and portable product applications.

Many companies have migrated from SO-type packages to QFNs and DFNs and their popularity continues to spread as new advancements make QFNs/DFNs capable of handling a greater amount of circuitry and functionality.  The QFNs with dual rows of lands can support as many as 180 I/Os.  There are also a growing variety of QFNs/DFNs such as versions with multiple chips stacked inside, or types that have an air-cavity designed into the package for high-frequency microwave applications.

RFMD today announced it has shipped more than one million RF7196D high-power, high-efficiency CMOS power amplifiers (PAs). The ultra-low cost RF7196D is RFMD’s newest and most innovative CMOS PA, delivering a revolutionary combination of cost, size and performance. It is in mass production in support of multiple high-volume 2G and 3G handset platforms, and shipments are expected to increase rapidly, reaching approximately 10 million units by the end of the September quarter.

RFMD is seeing strong adoption of its CMOS power amplifier technologies in next-generation handset platforms targeting emerging markets. The company is migrating its diverse set of customers of 2G power amplifiers (both GaAs and CMOS) to its ultra-low cost RF7196D and expects shipments will more than double in the December quarter and exceed 100 million units worldwide in calendar 2014.

Eric Creviston, president of RFMD’s Cellular Products Group (CPG), said, "RFMD’s ultra-low cost CMOS PA technology delivers excellent overall performance at highly competitive costs versus prior generations. We intend to launch a broad portfolio of innovative new CMOS products in the coming quarters, and we forecast strong growth in emerging markets across a highly diversified customer set."

Industry analysts forecast the total addressable market for RF applications in emerging markets will increase at a compound annual growth rate of approximately 20 percent through 2018 as next-generation 3G and 4G air standards are introduced, as existing subscribers upgrade their devices, and as new subscribers are added.

Cascade Microtech, Inc. and imec today announced breakthroughs in probing stacked integrated circuits (3D-SICs), fueling an important growth engine for the semiconductor market. Through a Joint Development Agreement, Cascade Microtech partnered with imec to successfully probe 25µm-diameter micro-bumps on a wide I/O test wafer with its fully-automated CM300 probe solution utilizing an advanced version of Pyramid Probe technology. This achievement comes as part of imec’s 3D integration research program which includes other industry partners from the entire semiconductor value chain.

The 3D semiconductor market (including 3D-SIC, 2.5D interposer, and 3D WLCSP) is expected to represent nine percent of the total semiconductor value by 2017, according to Yole Développement. Logic 3D SoC/SiP (including interposer chips, APE, CPU, FPGA, wide I/O memory, etc.) will be the biggest industry using 3D platforms in the next few years. 3D applications will emerge in high-performance computing, and electronic markets such as nanotechnology and medical applications, which will benefit from the high-density integration that 3D technology offers.

The semiconductor industry is exploring new methods to increase the functionality of ICs at a smaller footprint, extending Moore’s Law. 3D-SICs offer a solution to the speed, power and density requirements demanded by future mobile electronics platforms. Through-silicon vias (TSV) used in 3D-SICs shorten interconnects between logic elements, thus reducing power while increasing performance. Within imec’s 3D integration research program, industry leaders are jointly developing design, manufacturing, and test solutions to bring this new technology to high-volume manufacturing.

Cascade Microtech’s CM300 flexible on-wafer measurement system was designed to deliver superior positioning accuracy and repeatable contact, offering a level of precision that supports both shrinking pad sizes and pitch roadmaps. The CM300 captures the true electrical performance of devices with high-performance capabilities that include low leakage and low noise. As a comprehensive probing solution employing the latest advances in Pyramid Probe technology, the CM300 has proven to meet the fine-pitch (40 µm area array), low-force (< 1gf/tip) advanced probing requirements of 3D-SICs.

“We are excited that our work with Cascade Microtech has resulted in such a breakthrough. I believe together we’ve achieved a first in the industry,” said Erik Jan Marinissen, Principal Scientist at imec in Leuven, Belgium. “We are able to hit 25 µm-diameter micro-bumps with a high level of accuracy due to the probe-to-pad alignment features of Cascade Microtech’s CM300. And advances in their Pyramid Probe technology have enabled us to probe micro-bumped wafers with 40/50 µm pitch according to the JEDEC Wide-I/O Mobile DRAM standard.”

“Cascade Microtech’s CM300 probe solution is designed to provide greater alignment accuracy to probe directly on small, fragile micro-bumps. In conjunction with a fine-pitch, low-force Pyramid Probe card, we have achieved consistent, accurate measurements on a wide I/O test wafer using a single-channel, wide I/O probe core with an array of 6 x 50 tips at 40/50 µm pitch, with the ability to shrink down to 20 µm pitches in the future,” said Steve Harris, Executive Vice President, Engineering, Cascade Microtech. “Together, imec and Cascade Microtech are enabling the ongoing future of CMOS technologies through this ground-breaking work. 3D integration will undoubtedly result in increased performance and yield while reducing overall costs.”

 

Toshiba Corporation and Amkor Technology, Inc. today announced that the companies have completed Amkor’s acquisition of Toshiba Electronics Malaysia Sdn. Bhd., Toshiba’s semiconductor packaging operation in Malaysia. The transaction also includes Toshiba’s license to Amkor of related intellectual property rights and a manufacturing services agreement between Toshiba and Amkor.

Under the manufacturing services agreement, Toshiba has agreed to purchase and TEM has agreed to supply packaging and test services for certain discrete semiconductor products and analog LSI products.

Established in 1973, TEM has steadily expanded the scale of its packaging operations, primarily of discrete and analog semiconductors. In recent years, its main product has been power semiconductors.

Toshiba positions power semiconductors as a driver of growth for its semiconductor business and seeks to maximize cost competitiveness across its front- and back-end operations. Transferring ownership of TEM to the Amkor group will allow TEM to take full advantage of Amkor’s large scale production and materials procurement capabilities and boost the overall efficiency of its power semiconductor operations.

Toshiba will continue to subcontract power semiconductor packaging and test to Amkor as an important source of key products. As it does so, Toshiba will shift its focus and resources to front-end wafer fabrication for power semiconductors by reinforcing production capabilities at Kaga Toshiba Electronics Corporation, Toshiba Group’s discrete semiconductor production facility in Ishikawa Prefecture, Japan.

Amkor expects the transaction to further strengthen its relationship with Toshiba and to grow its semiconductor packaging and testing business. Amkor plans to leverage the technology and scale of this new factory to attract leading power discrete customers to Amkor.

Semiconductor revenue worldwide will see improved growth this year of 6.9 percent and reaching $320 billion according to the mid-year 2013 update of the Semiconductor Applications Forecaster (SAF) from International Data Corporation (IDC). The SAF also forecasts that semiconductor revenues will grow 2.9 percent year over year in 2014 to $329 billion and log a compound annual growth rate (CAGR) of 4.2 percent from 2012-2017, reaching $366 billion in 2017.

Continued global macroeconomic uncertainty from a slowdown in China, Eurozone debt crisis and recession, Japan recession, and the U.S. sequester’s impact on corporate IT spending are factors that could affect global semiconductor demand this year. Mobile phones and tablets will drive a significant portion of the growth in the semiconductor market this year. The industry continued to see weakness in PC demand, but strong memory growth and higher average selling prices (ASPs) in DRAM and NAND will have a positive impact on the semiconductor market. For the first half of 2013, IDC believes semiconductor inventories decreased and have come into balance with demand, with growth to resume in the second half of the year.

"Semiconductors for smartphones will see healthy revenue growth as demand for increased speeds and additional features continue to drive high-end smartphone demand in developed countries and low-cost smartphones in developing countries. Lower cost smartphones in developing countries will make up an increasing portion of the mix and moderate future mobile wireless communication semiconductor growth. PC semiconductor demand will remain weak for 2013 as the market continues to be affected by the worldwide macroeconomic environment and the encroachment of tablets," said Nina Turner, Research Manager for semiconductors at IDC.

According to Abhi Dugar, research manager for semiconductors, embedded system solutions, and associated software in the cloud, mobile, and security infrastructure markets, "Communications infrastructure across enterprise, data centers, and service provider networks will experience a significant upgrade over the next five years to support the enormous growth in the amount of data and information that must be managed more efficiently, intelligently, and securely. This growth is being driven by continued adoption of rich media capable mobile devices, movement of increasingly virtualized server workloads within and between datacenters, and the emergence of new networking paradigms such as software defined networking (SDN) to support the new requirements."

Regionally, Japan will be the weakest region for 2013, but IDC forecasts an improvement over the contraction in 2012. Growth rates in all regions will improve for 2013 over 2012, as demand for smartphones and tablets remain strong and automotive electronics and semiconductors for the industrial market segment improve in 2013.

Cree, Inc. announces that its 1200 V SiC MOSFETs are being incorporated into the latest advanced power supplies from Delta Elektronika BV. Delta Elektronika demonstrated a 21 percent decrease in overall power supply losses and a reduction in component count by up to 45 percent when compared to power supply products using traditional silicon technology.

Since 1959, Netherlands-based Delta Elektronika BV has produced power supplies for a range of industrial applications, such as specialized equipment used in factories, automation and industrial power conversion. Its power supplies typically provide high efficiency with low noise levels and are well known for their long operating lifespan.

“We are pleased to have Delta Elektronika BV as one of the volume adopters of our newest generation of SiC MOSFETs,” said Cengiz Balkas, general manager, Cree Power and RF. “Delta Elektronika BV has a half-century legacy of producing some of the most reliable, efficient and compact power supplies on the market. The industrial power supply market, which values efficiency, reliability and power density, is a key market for SiC MOSFET technology. Our new second-generation SiC MOSFET portfolio, which now includes a 160 m-Ohm MOSFET for the 5-10 kW market, is receiving strong market pull.”

Introduced in March 2013, Cree’s second-generation SiC MOSFETs have been well received throughout the power industry and are experiencing an increasing rate of adoption in several key applications, including a design-in at a major manufacturer’s next-generation, highly efficient PV inverters. With SiC, power supply manufacturers are able to reduce their component count to help improve reliability while maintaining or improving the power supply’s efficiency. Improving power density can also lead to reductions in the size, weight, volume and in some cases, even the cost of power supplies. SiC has been demonstrated to achieve more than twice the power density than typical silicon technology in standard power supply designs.