Category Archives: Materials and Equipment

Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers.

The HMC is the result of a consortium formed in late 2011 by Micron, Samsung, Altera, Xilinx and Open-Silicon to define an industry interface specification for developers, manufacturers and architects of high-performance memory technology. The consortium has grown to 110 members, including SK Hynix, IBM and ARM. Analysts are projecting the TSV-enabled 3D market to be a $40billion market by 2017, or roughly about 10% of the global chip business.

We caught up with Micron’s Scott Graham, General Manager, Hybrid Memory Cube, at Semicon West. “Today, we’re very close to delivering our engineering samples this summer to our lead customers that are taking the technology into their system designs,” Graham said.  The lead applications are in high performance computing, such as supercomputers, as well as the higher end networking space. “Those will be the early adopters. As we move forward in time, we’ll see that technology evolve as costs come down for TSVs and manufacturing technology, it will enter into future space where traditional DDR type of memory has resided. Beyond DDR4, we can certainly see this of memory technology being a mainstream memory,” Graham said.

Since the HMC is an open specification in terms of the architecture of the device, it will be up to each memory manufacturer to decide how it might be customized and manufactured. “The way it’s done today is we source the substrate, we source the logic layer and then we bring those in-house and we complete the finishing of those logic wafers as well as all the slicing, dicing, stacking, assembly and test,” Graham said. “What we end up providing for the customer is a known good cube, or known good piece of memory, just like we would if it was a DDR device or wide I/O device,” he said. He added that the HMC is designed so that it has not only the repair capability during manufacturing but also out in the field. “It’s very flexible and very robust, so reliability is very high with this device,” he said.

The consortium delivered its first specification earlier this year. “We’ve since extended the consortium to work on both future generations of the HMC technology in both the short-reach and ultra-short reach configurations,” Graham said.

The HMC was designed to get high density and high bandwidth in a relatively small package. The team adopted an off-the-shelf SERDES I/O and that’s based on IBM’s 32nm process. “With that, we can achieve 10 Gbps, 12.5 Gbps, or 15 Gbps for those SERDES links,” Graham said. “If you look at a 2 GByte or a 4GByte HMC device, those first devices will deliver a total aggregate bandwidth of 160GBytes/sec. I want to emphasize those are bytes not bits. It’s a very high bandwidth and low energy per bit device that is something that can be designed into a multitude of systems.”

The consortium has several generations of the HMC device planned (this summer’s engineering samples are Gen2). “As we move forward, you’ll see us moving into the 28 Gbps SERDES as far as the I/O goes,” Graham said. Bandwidths are going to be 320 Gigabytes/sec and higher, and the density will be in 4Gbyte and 8 Gbyte configurations.

Graham said one of the main challenges they had to overcome was the stacking. “We’re stacking a logic layer on top of a substrate and then four to eight DRAM on top of those logic layers,” he said. “We have over 2000 TSVs in this package and it was a challenge to stack these ultrathin die and make sure that what we end up with is a high performance and very reliable package.” Graham declined to comment on the exact TSV process flow used at Micron, saying only that it was leading edge. “We had to make sure our equipment partners were up to speed and could deliver us the technology that would allow us to manufacture this in high volume,” he said.  

Because customer can customize the HMC design, another challenge it to make sure that the design capabilities are available at the foundry for that logic layer, Graham said.  

Heat dissipation in the device is achieved through a metal lid, and through the TSVs which acts as chimneys (in addition to conducting electricity). The photo shows two Gen2 HMC devices. The larger one, in a 31mm x31 mm package, is a 4 link device that will achieve 160 Gig-bytes per second. The smaller one is a two link device capable of 120 Gigabytes/sec, measuring 16mm x 19.5 mm. “Both are being manufactured now in our plant and we’re doing the whole debug phase,” explained Aron Lunde, program manager, DRAM solutions group at Micron in Boise. He said the metal lid was in contact with not only the top layer, but different internal layers. “We call it an integrated heat spreader. It makes contact at more than one level and that’s what really helps,” he said.

Although manufacturers such as Micron, Samsung and SK Hynix must now handle the manufacturing, assembly and test process, Graham believes that it could eventually evolve to the point where select foundry partners would be able to provide volume manufacturing services for these HMC cubes.

Graham said DDR4 will likely be the last DDR device. “Beyond DDR4, you have to move to managed memory like HMC technology,” he said.  “We’re solving the memory wall problem with HMC-like architecture and what’s really going to be happening in the future is that you’ll be running into a CPU wall. That’s going to be the barrier to system progress as we move forward.”

Graham expects some challenges with scaling of conventional memory at sub-20nm process nodes. “We get into physical challenges of meeting the timing requirements and the 12 pages of JEDEC specifications to be able to yield properly and to be able to provide a cost-effective memory device moving forward,” he said.  

Although the HMC is now designed around DRAMs, Graham said it would be possible to use other types of memories, and even a mixed set of memories. He noted Micron is looking at alternatives to the conventional DRAM cell, such as spin torque and resistive memories. “Micron is investing heavily in research in those technologies and of course the HMC team here at Micron is looking at future technologies that we can take HMC architecture and be able to utilize different DRAM or even flash types of memory,” he said. “As the technology matures and it becomes lower cost, we can see this technology certainly evolving into more global applications and utilizing different memory types in that stack – and perhaps even multiple memory types in that stack.”

HMCs could eventually make their way into mobile devices, but Graham said that is likely to be three or four years away. Mobile applications presently employ low power DDR3 solutions, which will be used for several years. “We’ll see quite a few interesting designs start spinning when the mobile folks see they can differentiate with a managed memory solution. It’s not going to be HMC as we know it today, it will have to be optimized for mobile,” Graham said.

Alchimer, S.A. today announced a collaboration with the French research institute CEA-Leti to evaluate and implement Alchimer’s wet deposition processes for 300mm high-volume manufacturing. The project will evaluate Alchimer’s Electrografting (eG) and Chemicalgrafting (cG) processes for isolation, barrier and seed layers. When combined, Alchimer’s wet deposition processes have been demonstrated to achieve 20:1 aspect ratio through silicon vias (TSVs) due to their ability to coat conformally regardless of via topography, diameter or depth.

3D integration is moving towards a "via middle" approach where TSVs are formed after front-end processes, but prior to stacking.  Several applications are in the development phase, leading to constraints and different specifications for TSVs. Alchimer’s technology shows the potential to break through existing barriers to achieve high aspect ratio TSVs. This collaboration will evaluate the potential of its technology and its suitability for high-volume manufacturing.

"Current techniques, such as PECVD isolation and iPVD metallization, have performance limitations that are limiting achievable TSVs to 10:1 aspect ratios," said Bruno Morel, CEO of Alchimer. "Our 3D TSV products have unequivocally demonstrated their ability to deliver 20:1 aspect ratios at a significantly reduced cost as compared to current approaches. Now it is critical to validate the products’ full potential for 300mm high-volume manufacturing as well as to study their compatibility with the overall 3D integration process. Leti’s leading 3D expertise and world-class infrastructure will allow us to do that.

"Collaborating with Alchimer fits perfectly our strategy of delivering innovative solutions to industry," added Fabrice Geiger, head of Leti’s Silicon Technology Division. "Alchimer’s eG technology is a promising, cost-effective and breakthrough solution to address the challenges of future 3D TSV integration. Through this collaboration, Alchimer will have access to Leti’s expertise in the domain of 3D TSV integration and its world-class 300mm 3D platform capabilities."

eG is based on surface chemistry formulations and processes. It is applied to conductive and semiconductive surfaces and enables self-oriented growth of thin coatings of various materials, initiated by in-situ chemical reactions between specific precursor molecules and the surface. This process achieves a combination of conformality, step coverage and purity that cannot be matched by dry processes.

Developers have made major progress in the technology to manufacture printed or flexible circuits, sensors, batteries and displays. But frankly it’s been hard to build applications with much market pull without logic or memory as well, and those have been much harder to make. However, now printed memory and solutions for integrating conventional silicon die into flexible systems are edging into production, to potentially improve performance for a wider range of applications.  On the display side, easily integrated printed or flexible transparent conductive films for touch screens are starting to see some market traction.

Yole Développement projects the market for printed and flexible electronics will remain a modest ~$176 million this year, but will see 27 percent CAGR to ~$950 million by 2020, driven largely by printed layers integrated into large OLED displays.

Thinning patterned die makes flexible silicon on polymer

One interesting solution to add performance to flexible electronics could be an open platform for making flexible silicon die. American Semiconductor proposes drastically thinning conventional fabricated silicon wafers, and coating them with a combination of polymers. The resultant silicon-on-polymer approach protects and eases handling of the ultra-thin die, says CEO Doug Hackler, who will discuss the technology in a program on such hybrid solutions in the emerging market program series at SEMICON West in San Francisco in July. He reports user interest for large area distributed sensing systems that include ICs within structural composites in aircraft bodies to monitor stress, for bio sensors that conform to the body, for RF for wireless data transmission from printed sensors, and for drivers for flexible displays.

The company has qualified TowerJazz’s 130nm process to make SOI CMOS for its initial flexible standard microcontroller, and has worked with the foundry to establish design rules to make an open platform for other designers to create their own flexible chips. American Semiconductor thins these fabricated wafers by standard methods down to about ~40µm. “And then from <40µm it gets trickier and more proprietary,” says Hackler. But once these flexible silicon-on-polymer die are diced and released, they can be handled pretty much like standard chips. “The dicing and release are a little different, but once the die are on tape, then it appears feasible to do traditional pick and place,” he says, noting the company intends to use printed connections instead of bonding wire or solder bumps. After assembly on a flexible substrate, perhaps by a pick-and-place module integrated on a roll-to-roll printing tool, the devices would typically be laminated or overcoated for additional protection. The company plans to follow its flexible microcontroller with a standard analog/digital converter to take in sensor data, and an RF IC to send out the data. 

Innovative solutions for assembling silicon on flexible substrates move towards production

Packaging and assembling tiny thin die on flexible substrates remains a challenge, but multiple suppliers are making progress towards solutions that are starting to edge into commercial production. One approach particularly suitable for attaching sensors to the body is the spring-like stretchy wiring developed by MC10 for attaching thin silicon die to flexible substrates, for everything from wearable heart rate and fitness monitors to sensor membranes that can be implanted directly on organs inside the body. VP of R&D Kevin Dowling reports the company’s first commercial application is in a soft skullcap from Reebok that uses flexibly connected motion sensors to measure impacts to the head.

Tiny die size could also help with both cost and attachment of rigid die to conformable substrates, although handling and assembling them then becomes more of an issue. Terepac Corp. CTO Jayna Sheats notes that plenty of logic for simple controls could be very tiny and low cost — microprocessors with ~8000 transistors like the Z-80 generation currently used for many embedded control applications take up  <70µm2 of silicon with 90nm design rules, for millions on a wafer. But the die are too tiny to make the input/output connections or to handle with traditional pick and place for packaging and assembly. So Terepac proposes a photochemical assembly process instead, picking up an array of thinned and diced chips with a sticky printhead, positioning the chips over the substrate with a tool similar to a proximity aligner, and vaporizing the proprietary polymer/adhesive behind each selected chip with a combination of heat and UV so it falls into the desired position.  Chips can then be attached to the flexible substrate by conductive adhesive, electroplating, or printed connections. The company is working with equipment manufacturing partners including Rockwell International to construct manufacturing facilities for customers with products for the Internet of Things.

Jabil reports progress in low temperature attachment technologies for use with heat-sensitive flexible substrates. And Sandia National Lab reports it’s come up with a solution for the common researchers’ problem in this field of how to build prototypes of flexible systems when the necessary ultra thin chips only come in costly wafer-level volumes. Researchers there have figured out how to thin off-the-shelf single die for developing flexible systems.

Printed memory targets low-cost, high-volume applications          

Thin Film Electronics, meanwhile, is developing systems that use its simple, low cost printed memory. The company’s 20-bit memory can be produced in volume for under ~$0.05, targeted at applications like consumer packaging, with volumes of billions of units a year where roll-to-roll printing makes most sense, says Chandrasekhar Durisety, assistant director, North America, who will give an update on the company’s progress towards commercialization at the session. Thin Film is introducing a next generation of passive array memory, in 4×4 (16 bit), 5×5 (25 bit) or 6×6 (36-bit) options, a more conventional format with fewer pads at higher density for easier addressing than its initial 20-bit in-line architecture. 

The company is working with a global consumer product maker on using low-cost printed memory to make brand authentication cost effective for a wide range of lower-priced products. It’s also working with major flexible packaging supplier Bemis Company Inc. on sensor labels for food, healthcare and consumer products that can collect and wirelessly communicate sensor information at roughly the same low cost as current color-changing chemical indicators. The digital system under development — with Thin Film’s printed memory, an electrochromic display from Acreo, and printed logic technology from PARC — stores data when the temperature exceeds a certain range, to indicate more clearly than a color gradient can whether the product is usable or not. 

Thin Film aims to add electronics to applications that currently don’t use them, to add simple intelligence at prices far below those possible with silicon, such as low-cost brand authentication, temperature sensors on packaging, or simple electronics in toys.  “Silicon die could add significant capability to printed electronics. But with fabrication and assembly it would likely be more expensive than either silicon or printed electronics alone,” suggests Durisety.”  

Market starts to develop for printed/flexible ITO replacements

Another key potential market for printed/flexible electronics is next-generation transparent conductive film to replace brittle and expensive indium tin oxide in touch screens and displays, lighting, and photovoltaics.  Touch Display Research says the market for non-ITO transparent conductors will be about $206 million this year, and grow to some $4 billion by 2020.  “High demand for touchscreens for notebook and PC size displays has created a shortage of ITO touch sensors since the end of last year to drive more interest in these technologies, and the more flexible and potentially cheaper replacement technologies are getting more mature,” notes Jennifer Colegrove, president and analyst, who will speak at the FlexTech workshop on transparent conductors. She notes that Atmel, FUJIFILM, Unipixel and Cambrios are all in some phase of production.

There is, however, a confusing range of contending options for processes and materials for these films.  Applied Materials has interesting progress in its roll-to-roll deposition technology, while FUJIFILM Dimatix targets ink jet printing the materials, and NovaCentrix offers rapid thermal curing that doesn’t heat the substrate. Materials options range from nano metal wires at Cambrios Technology, Carestream and Sinovia, to embossed and metalized patterns from Unipixel, to carbon nanotubes at Brewer Science and graphene at Nanotech Biomachines. 

These and other speakers will talk about the challenges and solutions to move printed/flexible electronics into real markets at SEMICON West’s emerging technology programs, July 9-11 in San Francisco.

· Mon, July 8: Market Symposium, SF Marriott Marquis, Keynote: “New Directions in Flexible and Printed Electronics,” Dr. Ross Bringans, VP at PARC (1:00-5:30pm)

· Tue, July 9: Materials Growth Opportunities at Both Ends of the Spectrum (1:30-3:30pm)

· Wed, July 10: FlexTech Alliance Workshop: Emerging Materials and Processes for Transparent Conductors, SF Marriott Marquis (10:00am-5:00pm)

· Thur, July 11: Integrating Conventional Silicon in Flexible Electronics at the Extreme Electronics TechXPOT, South Hall (10:30am-1:10pm)

For more information, visit www.semiconwest.org/SessionsEvents/PlasticElectronics

Paula Doe is an analyst for advanced technologies for the global trade association SEMI.

Imec has developed a Manganese (Mn)-based self-formed barrier (SFB) process that significantly improves Resistance Capacitance (RC) performance, via resistance and reliability in advanced interconnects. It provides excellent adhesion, film conformality, intrinsic barrier property and reduced line resistance. This technology paves the way towards interconnect Cu metallization into the 7nm node and beyond.

With continuous interconnect scaling, the wire resistance per unit length increases, which has a detrimental impact on the device performance (RC). Moreover, when reducing the dimensions with conventional barrier layers, an increased loss of copper (Cu) cross sectional area is observed, resulting in high resistance and decreased interconnect lifetime (electro-migration and time dependent dielectric breakdown – EM and TDDB). To overcome these interconnect metallization issues when scaling beyond the 1X technology node, imec’s R&D program on advanced interconnect technology explores new barrier and seed materials as well as novel deposition and filling techniques. The Mn-based SFB was demonstrated to be an attractive candidate for future interconnect technology.  At module level, Mn-based SFB resulted in a 40 percent increase in RC benefits at 40nm half pitch compared to conventional barrier and good lifetime performance (comparable to TaN/Ta reference).

These results were achieved in cooperation with imec’s key partners in its core CMOS programs Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu and Sony.

Imec exhibits at SEMICON West, July 9-11, 2013.

Dr. Deepak Sekar is a senior principal engineer at Rambus Labs. He is the author or co-author of a book, two invited book chapters, 30 publications and 100 issued or pending patents (50 issued). He is a program committee chair at the International Interconnect Technology Conference, has received two best paper awards and serves on the committee of the International Technology Roadmap for Semiconductors. 

 In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult. The solution, he said, is to supplement VLSI with what he called a Wafer Level System Integration (WLSI) paradigm. Advances in wafer level packaging and through-silicon via technology could allow systems to scale and reduce the dependence on transistor/chip scaling, according to Yu.

Figure 1: Douglas Yu of TSMC talked about WLSI

Techniques for WLSI

Yu then described TSMC’s efforts towards WLSI.

Fan-in wafer level packages, where the package is the same size as the chip, were shown with sizes as high as 52 sq. mm (see Figure 2(a)). These could be used for low pin count applications such as WiFi.

Fan-out wafer level packages, where individual die are embedded in a molding compound, could be used for higher pin count applications, said Yu. These allow placing one or more die within the same package. TSMC has qualified large 225 sq. mm fan-out wafer level packages with tight 20um pitch redistribution layer wiring (see Figure 2(b)). These fan-out wafer level packages could be used for medium to high pin count applications and also for multi-chip packages.

Figure 2: (a) A 52 sq. mm fan-in wafer level package (b) A 225 sq. mm fan-out wafer level package where the die is surrounded by a molding compound

Yu then showed TSMC’s silicon interposer and 3D-TSV technology, called CoWoS (chip-on-wafer-on-substrate). Figure 3 depicts the process flow for CoWoS and finished systems built with the technology. It is just a matter of time before TSV technologies are prevalent, he said.

Figure 3: Chip-on-Wafer-on-Substrate technology used for interposer and 3D systems

How WLSI could allow system scaling despite the increasing challenges with Moore’s Law

Significant reductions in system size are possible with wafer level packaging, interposer and 3D stacking technologies, said Yu. This is particularly beneficial to mobile applications, which show the fastest growth in the industry today. This would allow packing more and more functionality within the same form factor, something Moore’s Law is finding increasingly difficult to do.

Smart system partitioning with WLSI can benefit electronic products quite a bit, said Yu. He gave an example of partitioning digital and analog components. With finFETs moving to production, designing analog components on the same chip as logic becomes difficult due to high parasitic capacitance. Analog blocks take up more and more percentage of the chip area since they don’t scale well. In this scenario, placing analog components on a separate chip and using fan-out wafer level packaging or TSV technology to build competitive systems is beneficial, he said. This allows systems to combine analog at a trailing edge node (eg. 65nm) and logic at a leading edge node (eg. 14nm). IP blocks can be reused, time-to-market can be accelerated with smart system partitioning and yields can be improved due to the lower die size, said Yu.

System performance per watt improvement, one of the benefits of Moore’s Law scaling, can also be obtained with WLSI, according to Yu. Memory (access) power is now a key component of total system power and this is increasing with every generation. By using fan-out wafer level packaging or TSV technology, memory power can be significantly reduced due to the shorter wire lengths (Figure 4).

Figure 4: WLSI could reduce logic to DRAM wire lengths from 20mm to 0.03mm.

During the question and answer session, Yu mentioned that all of the technologies he described used pure wafer-based processes, which allowed larger packages and lower cost. Audience members, when asked about the keynote, mentioned that cost will determine how prevalent the technologies presented in Yu’s talk will become. 3D chip technologies are still considered a few years away from mass adoption.

The International Interconnect Technology Conference, held in Kyoto this year, is IEEE’s flagship conference in the interconnect field.

CEA-Leti announced today that researchers Dominique Vicard and Jean Brun received the Avantex Innovation Prize for the use of the E-Thread technology in textiles.

The award was presented June 10 during the award ceremony at the opening of the Techtextil and Avantex Symposia in Frankfurt, Germany.

According to Avantex, the “innovation awards go to outstanding achievements in research, new materials, products, technologies and applications.”

E-Thread is a microelectronic packaging technology developed by Leti that allows for a direct connection of a chip to a set of two conductors, which can provide the functions of antenna, power and/or data bus. This allows a 10x improvement in size, assembly time and reliability compared to classic microelectronic packaging. The E-Thread assembly can then be incorporated inside a yarn and used by the textile and plastic industries using standard production tools. Electronics such as LEDs, RFIDs or sensors can then be truly integrated in materials and objects.

In choosing this technology for the innovation award, the Avantex jury said “electronics integrated in textiles during the textile processing and not simply by adding the components in a last step will be a significant step forward.” The jury also said the prize was awarded to “this development, as it shows that research and development is also for the textile industry of vital importance and that it can lead to the creation of new companies.”

E-Thread is one of the technologies used within the European FP7 PASTA project (Platform for Advanced Smart Textile Application), and is the key technology asset of the Primo1D startup company, that will be created by Leti during the second half of 2013.

Vicard previously won a 40,000-euro startup award from OSEO, the French organization committed to supporting entrepreneurship, for proposing embedding electronic functions in textile yarns using the E-Thread technology.

Samples of E-Thread will be on display during the symposia, Hall 3.1, stand B11.

Fab equipment spending will grow two percent year-over-year  (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast. Fab construction spending, which can be a strong indicator for future equipment spending, is expected to grow 6.5 percent ($6.6 billion) in 2013, followed by a decline of 18 percent ($5.4 billion) in 2014. The new World Fab Forecast report covers fab information on over 1,140 facilities, including such details as capacities, technology nodes, product types, and spending for construction and equipment for any cleanroom wafer facility by quarter.

Fab equipment spending for the second half of 2013 is expected to be much stronger with a 32 percent growth rate or $18.5 billion compared to the first half of 2013. The equipment spending increase in the second half is attributed to growing semiconductor demand and improving average selling price for chips. 2014 is expected to have about 23 to 27 percent growth year-over-year (YoY) to reach about $41 billion, which would be an all-time record.

Looking at product types, the largest amounts of spending on fab equipment in 2013 will come from the foundry sector, which increases by about 21 percent. This is driven mainly by capex increases by TSMC. The memory sector is expected to have an increase of only one percent — after a 35 percent decline in the previous year. The MPU sector is expected to grow by about five percent. A double-digit increase in the Analog sector in 2013 will still translate into low absolute dollar amounts, compared to the other sectors.  

 

Construction spending is a good indicator for more equipment spending.  Fab construction spending in 2013 is expected to be almost 15 percent growth YoY ($6.6 billion) with 38 known construction projects. Top spenders for fab construction in 2013 are TSMC and Samsung, who plan to spend between $1.5 and $2 billion each, followed by Intel, Globalfoundries and UMC. The SEMI World Fab Forecast report reveals more detail.

2014 shows a decline of about 18 percent ($5.4 billion) in construction spending with only 21 construction projects expected to be on-going. These construction projects include large fabs; some are 450mm-ready. 

Since the last fab database publication at the end February 2013 SEMI’s worldwide dedicated analysis team has made 389 updates to 324 facilities (including Opto/LED fabs) in the database. The latest edition of the World Fab Forecast lists 1,144 facilities (including 310 Opto/LED facilities), with 61 facilities with various probabilities starting production this year and in the near future. Seventeen new facilities were added and 8 facilities were closed.

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs; and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter.

GLOBALFOUNDRIES plans to unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes at next week’s 50th Design Automation Conference (DAC) in Austin, Texas. The sign-off ready flows, jointly developed with the leading EDA providers, offer robust support for implementing designs using sophisticated multi-die packaging techniques, leveraging through-silicon vias (TSVs) in 2.5D silicon interposers and new bonding approaches.

Multi-vendor support is available, with full implementation flows from Synopsys and Cadence Design Systems. Physical verification with Mentor Graphics’ suite of tools is included in the flow.

The GLOBALFOUNDRIES 2.5D technology addresses the challenges of multi-die integration with solutions for front-end steps such as via-middle TSV creation, and flexibility for the backend steps, like bonding/debonding, grinding, assembly, and metrology.

“Our 2.5D technology provides designers with a path to enable heterogeneous logic and logic/memory integration, offering increased performance and reduced power consumption, without the need for additional packages,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “These benefits can now be realized very efficiently with certified design flows that provide support for the additional steps and design rules involved in the design process. By working closely with our EDA partners, we can greatly reduce the development time and time-to-production using the most advanced multi-die approaches.”

The flows allow designer to quickly and reliably address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing. The flows support the need for additional verification steps brought on by 2.5D design rules.

The design flows work with GLOBALFOUNDRIES’ process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GLOBALFOUNDRIES design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

The flows come with a CPU core and memory IP and all the scripts and settings to execute a Synopsys Galaxy Implementation Platform-based flow or Cadence Encounter-based implementation flows with the GLOBALFOUNDRIES PDK. Similarly, the Mentor Calibre 3DSTACK tool is exercised in the flow to verify DRC, LVS and extraction within and between the various die stacks leveraging the same golden design kits as used inside of GLOBALFOUNDRIES .

The semiconductor industry’s march toward broader 3D IC integration marked an important milestone this week at the 2013 Electronic Components & Technology Conference (ECTC), with the report of an advanced new temporary bonding solution for 3D Through-Silicone-Via (TSV) semiconductor packaging. The breakthrough was unveiled during ECTC’s 3D Materials and Processing session, when Ranjith John, materials development and integration engineer at Dow Corning, presented a paper co-authored by Dow Corning, a developer of silicones, silicon-based technology and innovation, and SÜSS MicroTec, a supplier of semiconductor processing equipment.

The paper, titled Low Cost, Room Temperature Debondable Spin on Temporary Bonding Solution:  A Key Enabler for 2.5D/3D IC Packaging, details the development of a bi-layer spin-on temporary bonding solution that eliminates the need for specialized equipment for wafer pretreatment to enable bonding or wafer post-treatment for debonding. Thus, it greatly increases the throughput of the temporary bonding/debonding process to help lower the total cost of ownership. 

“This advance underscores why Dow Corning values collaborative innovation. Combining our advanced silicone expertise with SÜSS MicroTec’s knowledgeable leadership in processing equipment, we were able to develop a temporary bonding solution that met all critical performance criteria for TSV fabrication processes. Importantly, the spin coat-bond-debond process we detailed in our co-authored paper takes less than 15 minutes, with room for further improvement,” said John. “Based on these results, we are confident that this technology contributes an important step toward high-volume manufacturing of 2.5D and 3D IC stacking.”

Both 2.5D and 3D IC integration offer significant potential for reducing the form factor of microelectronic devices targeting next-generation communication devices, while improving their electrical and thermal performance. Cost-effective temporary bonding solutions are a key enabler for this advanced technology by bonding today’s ultra-thin active device wafers to thicker carrier wafers for subsequent thinning and TSV formation. However, in order to be competitive, candidate temporary bonding solutions must deliver a uniformly thick adhesive coat, and be able to withstand the mechanical, thermal and chemical processes of TSV fabrication. In addition, they must subsequently debond the active and carrier wafers without damaging the high-value fabricated devices.

Through their collaboration, Dow Corning and SÜSS MicroTec were able to develop a temporary bonding solution that met all of these application requirements. Comprising an adhesive and release layer, Dow Corning’s silicon-based material is optimized for simple processing with a bi-layer spin coating and bonding process. Combined with SÜSS MicroTec equipment, the total solution offers the benefits of simple bonding using standard manufacturing methods. In their co-published paper, the collaborators report a solution exhibiting a total thickness variation of less than 2 µm for spin-coated films on either 200- or 300-mm wafers. The bonding material exhibited strong chemical stability when exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. In addition, the bonding solution and paired wafers showed good thermal stability when exposed to the 300°C temperatures common to the TSV process.

Dow Corning builds on a long history of silicon-based innovation and collaboration in semiconductor packaging. From die encapsulants for stress relief, to adhesives for sealing and bonding, to thermal interface materials for performance and reliability, Dow Corning’s well-established global infrastructure ensures reliable supply, quality and support, no matter where you are in the world.

Signetics Corporation today announced that it has again approved capex plans that will further expand their capacity for flip chip package assembly at their factory in Paju, South Korea. The new Flip Chip expansion will be ready for volume production in July 2013 and will increase assembly capacity by more than twenty percent. This line is capable of handling boat type flip chip ball grid arrays (FCBGA) including Signetics’ new high density Super Wide Boat, as well as flip chip fine pitch BGAs (FCFBGA) with substrates as wide as 95mm.

"In the first half of this year, we have continued to see an increase in the forecasts for Flip Chip packaging from our established tier 1 and high growth customers," stated JI Kim, CEO and president of Signetics. "The growth in flip chip continues to be driven by applications such as Smart TVs, SSD and WiFi", continued Kim.

Signetics offers a range of flip chip packaging options that use industry standard bumping technologies as well as the finer pitch copper pillar bumping technology.  Substrates used for flip chip packaging at Signetics include both PBGA and FBGA as well as leadframe technologies such as QFN.  Flip chip assembly is offered in multi die or system-in-package configurations and hybrid configurations with both wirebond and flip chip connectivity for today’s new applications that require more and more system integration in a single package.