Category Archives: Materials and Equipment

Silicon nanocrystals have a size of a few nanometers and possess a high luminous potential. Scientists of Karlsruhe Institute of Technology (KIT) and the University of Toronto/Canada have now succeeded in manufacturing silicon-based light-emitting diodes (SiLEDs). They are free of heavy metals and can emit light in various colors.

Liquid-processed SiLEDs: By changing the size of the silicon nanocrystals, color of the light emitted can be varied. (Photo: F. Maier-Flaig, KIT/LTI)

Silicon dominates in microelectronics and photovoltaics industry, but has been considered unsuitable for light-emitting diodes for a long time. However, this is not true for nanoscopic dimensions: Minute silicon nanocrystals can produce light. These nanocrystals consist of a few hundred to thousand atoms and have a considerable potential as highly efficient light emitters, as was demonstrated by the team of Professor Uli Lemmer and Professor Annie K. Powell from KIT as well as Professor Geoffrey A. Ozin from the University of Toronto. In a joint project, the scientists have now succeeded in manufacturing highly efficient light-emitting diodes from the silicon nanocrystals.

So far, manufacture of silicon light-emitting diodes has been limited to the red visible spectral range and the near infrared.

“Controlled manufacture of diodes emitting multicolor light, however, is an absolutely novelty,” explains Florian Maier-Flaig, scientist of the Light Technology Institute (LTI) of KIT and doctoral student of the Karlsruhe School of Optics and Photonics (KSOP). KIT scientists specifically adjust the color of the light emitted by the diodes by separating nanoparticles depending on their size.

 “Moreover, our light-emitting diodes have a surprising long-term stability that has not been reached before,” Maier-Flaig reports.

The increased service life of the components in operation is due to the use of nanoparticles of one size only. This enhances the stability of the sensitive thin-film components. Short circuits due to oversized particles are excluded.

The development made by the researchers from Karlsruhe and Toronto is also characterized by an impressing homogeneity of the luminous areas. The KIT researchers are among the few teams in the world that know how to manufacture such devices.

“With the liquid-processed silicon LEDs that may potentially be produced on large areas as well as at low costs, the nanoparticle community enters new territory, the associated potentials of which can hardly be estimated today. But presumably, textbooks about semiconductor components have to be rewritten,” says Geoffrey A. Ozin, who is presently working as a KIT distinguished research fellow at KIT’s Center for Functional Nanostructures (CFN).

The SiLEDs also have the advantage that they do not contain any heavy metals. In contrast to cadmium selenide, cadmium sulfide or lead sulfide used by other groups of researchers, the silicon used by this group for the light-emitting nanoparticles is not toxic. Moreover, it is available at low costs and highly abundant on earth. Due to their many advantages, the SiLEDs will be developed further in cooperation with other partners.

Only light, aerial oxygen, and a catalyst are needed to remove pollutants from water. Ruhr-Universitat Bochum researchers led by Professor Radim Beránek are collaborating with colleagues from seven different countries in order to develop a photocatalyst that is efficient enough to be profitable. For that purpose, they combine sunlight-absorbing semiconductors and nanostructured materials which they optimize for electron transfer processes. The aim is to implement the newly developed photocatalysts into a liquid paint with which photoreactors can easily be coated. The EU supports the project within its 7th Framework Programme (FP7) with 3.7 million Euro funding for three years.

Current problems of photocatalysis

People from many countries of the world extensively use pesticides, which contaminate drinking and irrigation water with toxic organic compounds. In rural areas of Vietnam, herbicides and dioxins, resistant to degradation, made their way into the water cycle during the Vietnam War. The results can be devastating. People who drink this contaminated water are at a higher risk of developing cancer, and pregnant women may put their newborn at risk for birth defects, in worst case scenarios.

“Photocatalysis is potentially one of the cheapest and most efficient methods for purifying water from pollutants,” Radim Beránek says.

Sunlight and oxygen establish oxidizing conditions, under which toxins are easily degraded into non-harmful substances like water and carbon dioxide. Up until now, the process, however, faces two problems: degradation rates are too low and assembly of the needed photoreactors is too expensive.

The aim: cheeper and more efficient catalysts

Within the project “4G-PHOTOCAT,” the researchers aim to develop cost-efficient photocatalysts with a considerably improved degradation rate. They fabricate innovative composite materials consisting of semiconductors and nanostructured metal oxides. In order to achieve the optimal architecture for the product, they employ advanced chemical deposition techniques with a high degree of control over composition and morphology.

“Our ultimate goal is to implement the newly developed photocatalysts into a liquid paint,” Radim Beránek says. “Photoreactors painted with that liquid can be used, for example, for water decontamination in remote rural areas of Vietnam.”

Collaborators

“4G-PHOTOCAT “allies the expertise of seven academic and three industrial partners from five European countries and two Southeast Asian countries. At the RUB, Beránek collaborates with Professor Dr. Roland A. Fischer (Inorganic Chemistry II), Professor Dr. Martin Muhler, and Dr. Jennifer Strunk (Industrial Chemistry). The international collaborators include scientists from the University College London, J. Heyrovský Institute of Physical Chemistry in Prague, Jagiellonian University Krakow, University of Helsinki, Universiti Teknologi Malaysia, and Hanoi University of Agriculture. Furthermore, industrial partners from Finland (Picosun), Czech Republic (Advanced Materials), and Vietnam (Q&A) have joined the team.

The ability to improve silicon transistors is reaching its fundamental limit, so researchers are searching for new ways to keep making electronic devices faster and more powerful. University of Nebraska-Lincoln physicists and colleagues have taken a major step toward breaking that silicon barrier.

University of Nebraska-Lincoln physicists (from left) Evgeny Tsymbal, John D. Burton and Alexei Gruverman in the UNL Materials Research Science and Education Center’s Thin Film Growth and Characterization Facility. (Photo by Craig Chandler/University Communications)

UNL physicist Evgeny Tsymbal and colleagues demonstrated that a nanostructure with unique properties may hold the key to creating much smaller, more powerful electronics. They reported their findings in Nature Materials, published online this week. This work builds on predictions by Tsymbal, Bessey Professor of Physics and Astronomy and director of UNL’s Materials Research Science and Engineering Center, and colleague John D. Burton, reported in Physical Review Letters in 2011.

They had theorized that a layer of ferroelectric oxide just a few atoms thick could be exploited as a memory element to store more digital information using less energy than silicon-based memories. Using quantum theories and super computers at the university’s Holland Computing Center, they predicted how a ferroelectric memory element would behave.

Then they asked experimentalist Qi Li at Pennsylvania State University, UNL physicist Alexei Gruverman and colleagues at Oak Ridge National Laboratory, Tenn., and at universities in China and Korea to put their theories to the test. Those results proved the researchers’ predictions correct.

The theory is based, in part, on a phenomenon called quantum tunneling, in which particles can pass through a barrier only at the quantum, or atomic, level. To develop a new generation of electronics, scientists are experimenting with tunnel junctions, in which an ultra-thin barrier is placed between two electrodes. When voltage is applied, electrons are able to tunnel through the barrier, creating a current with resistance.

Tsymbal and colleagues created a tunnel junction using nano-thin ferroelectric oxide, a material with both positive and negative polarization directions, which can be reversed by switching the voltage charge. They have shown that reversing the polarization changes the resistance through the tunnel junction by 100 times, a difference large enough to easily measure.

These ferroelectric properties are important because its two polarization directions could be read across regions like a binary code to store information. Tsymbal’s team has shown that the measurable difference in resistance could be used to detect polarization directions.

Current silicon-based devices require large currents, so the size of the space between regions must be big enough to accommodate the heat that’s generated. Because a ferroelectric device would use less energy, it would allow for more regions in a much smaller space, which would enable more compact and powerful devices.

Such a device won’t hit stores anytime soon, however. The effect only works up to minus 100 degrees Fahrenheit.

"For applications, you obviously want to have this change in resistance at room temperature," Tsymbal said. "This can’t be used immediately, but it shows some new directions to pursue."

Next, UNL’s team will investigate other geometric and material configurations to find alternatives with greater applicability. Gruverman and Tsymbal also are exploring something called memristor. Rather than abruptly reversing polarization between two directions, memristor would allow changing polarization, and therefore resistance, continuously.

"Changing in a continuous way offers many stages of resistance and that will allow us to see more interesting physics and applications," Tsymbal said.

Co-authors are: UNL’s Tysmbal, Burton and Gruverman; Li of Penn State; Y.W. Yin, Penn State and the Hefei National Laboratory for Physical Sciences at Microscale at the University of Science and Technology of China; X.G. Li, Hefei National Laboratory for Physical Sciences at Microscale at the University of Science and Technology of China; Y-M. Kim, Oak Ridge National Laboratory and Seoul National University, Korea; A.Y. Borisevich and S.J. Pennycook, Oak Ridge National Laboratory; and S.M. Yang and T.W. Noh, Seoul National University.

Grants from UNL’s National Science Foundation-funded Materials Research Science and Engineering Center and the NSF’s Nebraska Experimental Program to Stimulate Competitive Research help support this research.

 

Tim Turner, the Reliability Center Business Development Manager at the College of Nanoscale Science and Engineering (CNSE), Albany, NY, blogs about the potential of resistive memory and the reliability challenges the must be overcome.

Resistive Memory, RRAM or Memristors is a hot topic right now.  RRAM has the potential for single digit nano parameters (speed as fast as 1 ns, area per bit as small as 5 square nm) and is non-volatile.

The technology is based on the formation of a small conductive filament inside an insulator.  The filament is formed the first time using a high voltage.  After that, set or reset transformation (conductive to non-conductive or visa versa) is accomplished by moving one or a few atoms an atomic scale distance.  This can be done with a low voltage (less than a volt).    This small movement gives a repeatable set or reset that can withstand many cycles.

Conduction in the filament appears to be due to oxygen vacancies existing in a percolation path through the insulator.  A small electric field in the reverse direction causes the migration of these oxygen vacancies in a mechanism similar to electromigration of Al or Cu atoms in a metal line.  Momentum exchange between electrons and the vacancies appears to be the driving force.  The vacancies do not have to move far to open the small filament.  An oxygen vacancy moves an atomic scale distance and the tiny filament opens, allowing an insulator to exist between points in the filament.  Forcing a forward voltage can move the oxygen vacancy back into the area where the filament is conductive.  This small movement can give a 100X change in the conduction through the dielectric.  This is the state change that can be interpreted as the digital signal stored on the memory cell.

The material set used for RRAM is CMOS compatible.  RRAM cells have been made out of Cu/HfOx [1], Al/AlOx/Pt, TiN/AlOx/Pt or even Al/AlOx/CNT (Carbon Nano Tubes)[2].  Most of the work reported to date has been on arrays where the cell is similar to a DRAM, using one transistor and one capacitor [3].  The RRAM cell starts with a capacitor, then forms the filament in the capacitor dielectric.  The advantage  this technology has is the smaller size of the capacitor.  There is no need for deep trenches in the silicon or for thick vertical stacks.   The technology is also non-volatile, so there is no need to refresh the charge every few milliseconds.

In polycrystalline materials, the filaments appear to form along grain boundaries between crystals [7].  For amorphous material there are no grain boundaries, but the material is reported to be able to withstand more cycles before failure [1].

RRAM might also be produced with a simple single resistor cross-point array (no transistor per cell required).  Figure 1 shows an array where the each cell is addressed by a row and a column.  The conduction in the row/column pair determines if the cell is set or reset (conductive or insulating).  This arrangement has the distinct advantage of allowing the memory array to be printed on top of a logic circuit.  Active circuits are required only for the address circuitry, allowing a large memory array to be added with little additional silicon area. 

Figure 1: Cross-point RRAM cell

That is the good news.  Now for the bad news.  What are the technology challenges that prevent you from enjoying this technology today?

The first issue is one of measurement noise.  With atomic spacing causing the difference between a set and a reset state, there is some uncertainty in the answer.  Sometimes, a bit will not program.  Nimal Ramaswamy of Micron [3] reported that random bits in a large array failed any given write operation.  There was an average number of failures for each write of a large array, but different bits failed each time.  Every bit apparently has the same probability of failure. 

Random Telegraph Noise (RTN) is another issue.  The state of the bit will most likely be read by forcing voltage and measuring current.  RTN is caused by trap states in the gate dielectric of a transistor that might address the bit.  These traps randomly fill or emit, changing the conduction of the channel.  The noise generated by this increases as the transistors are scaled.  Originally, this was thought to be just the larger impact of a single trap on a smaller area gate [4], but Realov and Shepard [5] showed that shorter L transistors show a greater noise than longer transistors with the same total area (below 40nm).  Thus, this is a problem that will increase as the technology is scaled.  There is also a chance that RTN will be generated by the movement of oxygen vacancies in the filament itself.

Degraeve et. Al. [6] reported a highly voltage sensitive disturb in the reset state.  Their RRAM cell could withstand 100 thousand disturb pulses (100ns) at -0.5 volts, but at -0.6 volts the cell could only withstand a little over 100 pulses.  They also showed that the sensitivity to disturb could be reduced significantly by balancing and optimizing the set and reset pulses.

Figure 2: Disturb in Reset State

Optimization of the Set and reset pulses also has a strong impact on the set/reset cycling endurance of the cell.  Degraeve was able to show up to 10 G set/reset pulses after optimization. 

Wu et. Al [2] showed the impact of scaling on a cross-point array.  According to their model, scaling the technology from 22nm to 5 nm resulted in an increase for the parasitic word and bit line resistance from under 10 ohms to almost 100,000 ohms as the lines width and thickness are reduced.  Adding to the significance of this is the variation in resistance between the closest cell in the array and the furthest call in the array.  This variation could be over 4 orders of magnitude while the difference between the set and reset resistance is only 2 orders of magnitude.  This issue could restrict the size of sub arrays, compromising the potential area savings using this technology.

As the metal lines are scaled to obtain higher memory densities, the filament that generates the conduction in the cell does not scale.  That means the set and reset pulse currents remain about the same as the array is scaled.  This results in an electromigration issue in the scaled metal lines.

Figure 3: Oxygen Vacancy Filament Determines Set or Reset State of RRAM Memory Cell

RRAM is certainly an appealing technology with its ability to scale the cell to tiny dimensions, good speed, CMOS compatible material set and the possibility of mounting the technology above a logic array.  Unfortunately, the devil is in the details and the list of advantages is balanced by a list of problems that must be overcome before this technology can carve out a space as a memory solution.

References:
1] Jihan Capulong, Benjamin Briggs, Seann Bishop, Michael Hovish, Richard Matyi, Nathaniel Cady, College of Nanoscale Science and Engineering, “Effect of Crystallinity on Endurance and Switching Behavior of HfOx based Resistive Memory Devices”, Proceedings of the International Integrated Reliability Workshop 2012
2] Yi Wu, Jiale Liang, Shimeng Yu, Ximeng Guan and H. S. Philip Wong, Stanford University, “Resistive Switching Random Access Memory – Materials, Device, Interconnects and Scaling Considerations”, Proceedings of the International Integrated Reliability Workshop, 2012
3] Nirmal Ramaswamy, Micron, “Challenges in Engineering RRAM Technology for High Density Applications”, Proceedings of the International Integrated Reliability Workshop, 2012
4] K.K. Hong, P.K Ko, Chemming Hu and Yiu Cheng,  Random Telegraph Noise of Deep Sub-Micrometer MOSFETs, 1990 IEEE 1741-3106/90/0200-0090 http://www.eecs.berkeley.edu/~hu/PUBLICATIONS/Hu_papers/Hu_JNL/HuC_JNL_167.pdf
5] Simeon Realov and Kenneth L. Shepard, “Random telegraph noise in 45nm CMOS: Analysis Using an on-Chip Test and Measurement System,  IEDM10-624, 978-1-4244-7419-6/10/$26.00 ©2010 IEEE, http://bioee.ee.columbia.edu/downloads/2010/S28P02.PDF
6] R. Degraeve, A. Fantini, S. Clima, B. Guvoreanu, L. Goux, Y. Y. Chen, D. J. Wouters, Ph. Rousset, G. S. Kar, G. Pourtois, S. Cosemans, J. A. kittl, G. Groeseneken, M. Jurczak, l. Altimime, IMEC, “Reliability of Low Current Filamentary HfO2 RRAM Discussed in the Framework of the Hourglass set/reset Model”, Proceedings of the Integrated Reliability Workshop, 2012.
7] Gennadi Bersuker, SEMATECH, “Origin of Conductive Filaments and Resistive Switching in HfO2 based RRAMS” Proceedings of the International Integrated Reliablity Workshop, 2012, 1.2-1

Leti to coordinate European supply chain in silicon photonicsCEA-Leti today announced that it will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding industrialization of the technology.

The PLAT4M (Photonic Libraries And Technology for Manufacturing) project will focus on bringing the existing silicon photonics research platform to a level that enables seamless transition to industry, suitable for different application fields and levels of production volume.

PLAT4M, which is funded by a European Commission grant of 10.2 million euros, includes 15 leading European research and development institutes and CMOS companies, key industrial and research organizations in design and packaging, as well as end users in different application fields to build the complete supply chain.

“Silicon with its mature integration platform has brought electronic circuits to mass-market applications – our vision is that silicon photonics will follow this evolution,” said Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, coordinator of PLAT4M. “Upgrading existing platforms to become compatible with industrialization is now essential and this requires streamlining and stabilizing the design and process flows by taking into account design robustness, process variability and integration constraints. The PLAT4M partners bring a combination of expertise to the challenge of building a complete supply chain for commercializing silicon photonics in Europe.”

A surge in output of silicon photonics research in recent years has significantly boosted the potential for commercial exploitation of the technology. However, most of this R&D has been devoted to developing elementary building blocks, rather than fabricating complete photonic integrated circuits, which are needed to support large potential markets.

 The PLAT4M consortium will make technologies and tools mature by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration and developing a packaging toolkit. The project will validate the complete supply chain through application-driven test vehicles representing various application fields, such as telecom and datacom, gas sensing and light detection and ranging (LiDAR) and vibrometry. It also will focus on preparing the next-generation platform by setting up a roadmap for performance evolution and assessing scalability to high-volume production.

The supply chain will be based on technology platforms of Leti, imec and STMicroelectronics, supported by a unified design environment.

 The multiple benefits of PLAT4M for the European photonic industry will include:

  • Preparing the supply chain for silicon photonics technology, from chip-level technology to packaged circuits
  • Making integration technologies accessible to a broad circle of users in a fabless model
  • Contributing to the development of a design environment that facilitates photonics/electronics convergence
  • Moving the emphasis from the component to the architecture, and thus concentrate efforts on new products or new functionalities rather than the technology level
  • Aggregating competencies in photonics/electronics design and fabrication, and
  • Retaining the key added value in components in Europe through optoelectronic integration, with little added value in offshore assembly

PLAT4M Consortium Members

The consortium consists of technology providers, research institutes, end users and SMEs with excellent track records in advanced photonics technologies. At the design and process level, CEA and imec have been the most prominent European players in silicon photonics for a decade. Together with University of Paris-Sud, III-V Lab and TNO, they have demonstrated numerous scientific and technological breakthroughs.

For building a complete design flow, Mentor Graphics, PhoeniX BV and Si2 are world leaders in EDA tools and will work together to develop a common reference platform.

STMicroelectronics (France and Italy) brings its experience in microelectronics, and it has been engaged for the past year in the development of silicon photonics at the industrial level. Tyndall-UCC and Aifotec are renowned experts in the field of optoelectronic packaging and will work together on the implementation of packaging technologies developed within PLAT4M in a manufacturing environment.

End-users like Polytec, Thales Research & Technology and NXP will drive the demonstrators development and assess the use of silicon photonics in their applications fields.

SEMATECH today announced that Poongsan, a producer of annealing furnaces, has joined its Front End Processes (FEP) program, and will work with SEMATECH to explore high-pressure anneal (HPA) techniques for silicon and non-silicon channel materials to improve device performance and reliability for next-generation technologies.

Today, the solid-state device community is investigating non-silicon, high-mobility materials to increase carrier mobility within the device channels and improve overall transistor performance. High-mobility channels such as germanium and III-V compounds have the potential to operate at high speeds with low operating power and may be used in mainstream semiconductor CMOS technologies in the future. However, numerous manufacturing challenges associated with high-mobility channels such as processes, tools, device test structures and environment, safety, and health issues need to be addressed before these materials-based solutions are brought to manufacturing.

Since 2006, Poongsan and SEMATECH have partnered in tool and process development projects that have successfully demonstrated the technical merits of a high pressure annealing furnace. 

“Working with SEMATECH, we have demonstrated that high-pressure anneals are both effective and manufacturing-worthy approaches to high-k/Si interface defect passivation. From this work, we have gone on to develop and ship production-worthy annealing furnace tools to world-wide customers,” said Dr. Bob Wu, director of sales and marketing of Poongsan. “We look forward to continuing our strategic partnership with SEMATECH as we work toward developing emerging technologies and improving products.”

As a member of SEMATECH’s FEP program, located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, Poongsan will collaborate with SEMATECH’s engineers and leverage SEMATECH’s activities in advanced test structures, advanced materials and device electrical characterization to improve processing technologies to increase mobility and reduce interfacial defects. Specifically, SEMATECH and Poongsan will collaborate on passivation of silicon and non-silicon gate stacks and other interfaces.

“To achieve better device performance and help shape the next generations of nanoelectronics, it’s necessary to partner to share know-how in materials, processing, equipment development and device technologies,” said Paul Kirsch, SEMATECH’s director of Front End Processes. “Poongsan’s proven expertise in high-pressure annealing processes will complement our own device and process expertise. We will work together on the technical and manufacturing gaps to address the continued scaling needs of today’s aggressive chip manufacturing market.”

The goal of SEMATECH’s FEP program is to provide novel leading-edge materials, processes, structural modules and electrical and physical characterization methods to support the continued scaling of logic and memory applications.

STMicroelectronics (NYSE: STM) announced today another milestone in its testing of its 28nm FD-SOI Technology Platform. Following the Company’s December announcement of the successful manufacturing of System on Chip (SoC) integrated circuits, ST today announced that application-processor engine devices manufactured at the Company’s Crolles, France fab, were capable of operating at 3GHz with even greater power efficiency at a given operating frequency than alternate technologies.

This announcement follows on the heels of recent announcements from other organizations to utilize FD-SOI technologies. Moore’s Law—the observation that the number of transistors on a chip doubled about every two years—has driven the semiconductor industry over the past 50 years to shrink the size of the transistors, which are essentially miniature on/off switches. The increased density from these size reductions have given consumers the explosion of new and more exciting features at lower-cost that we’ve come to expect. In parallel, these new features are able to operate at clock speeds that allow the phones to respond to your commands—by keypad, touchpad, and now voice—almost before you finish expressing the command.

Now, as those transistors shrink to nanoscale dimensions where about 450 transistors can fit within the diameter of a human hair, physics are challenging the traditional high-speed and low-power advantages of planar CMOS technology manufactured on bulk silicon wafers. FD-SOI technology is a major breakthrough in the pursuit of miniaturization of electronic circuits, and the achievement of 3GHz operating speed for an application-processor engine presages the adoption of FD-SOI in portable equipment, digital still cameras, gaming and ASICs for a range of applications. Of the next-generation process technologies, FD-SOI alone has proven its ability to meet the industry’s highest performance and lowest power demands that are vital to delivering graphics and multimedia that amaze without sacrificing battery life.

“As we had anticipated, FD-SOI is proving to be fast, simple and cool; we had fully expected to see 3GHz operating speeds, the design approach is very consistent with what we had been doing in bulk CMOS, and, with the benefits of fully depleted channels and back biasing, the low-power requirements are also meeting our expectations,” said Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, and Chief Technology and Manufacturing Officer of STMicroelectronics.

Reinforcing the point of simplicity, ST has found porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI to be straightforward, and the process of designing digital SoCs with conventional CAD tools and methods in FD-SOI to be identical to Bulk, due to the absence of MOS-history-effect. FD-SOI enables production of highly energy-efficient devices, with the dynamic body-bias allowing instant switch to high-performance mode when needed and return to a very-low-leakage state for the rest of the time – all in a totally transparent fashion for the application software, operating system, and the cache systems. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus Bulk CMOS.

It is a fact that semiconductor industry capital spending is becoming more concentrated with a greater percentage of spending coming from a shrinking number of companies.  As a result, IC industry capacity is also becoming more concentrated and this trend is especially prevalent in 300mm wafer technology.  The figure below lists the 300mm installed capacity leaders for 2012 and IC Insights’ forecast for 2013.  The list was compiled and included in IC Insights’ updated report titled, Global Wafer Capacity 2013—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity.    As shown, Samsung was by far the leader in 2012 having about 61% more 300mm capacity than second-place SK Hynix. Intel was the only other company that held a double-digit share of 300mm capacity at the end of 2012.  Assuming Micron is successful in acquiring Elpida in 1H13, the combined 300mm wafer capacity of the two companies will make the merged company the second-largest holder of 300mm capacity in the world behind Samsung.

 Of the top 10 companies on the list, half are primarily memory suppliers, two are pure-play foundries, and one company, Intel, is focused on MPUs.  Samsung is expected to maintain its lead in installed capacity through 2017, with aggressive capital spending plans seen over the past few years continuing over the next five years.  However, in terms of growth rate, IC Insights expects the largest increase in 300mm capacity to come from the pure-play foundries—TSMC, GlobalFoundries, UMC, and SMIC.  In total, IC Insights expects these four companies to more than double their collective 300mm wafer starts per month by 2017.

 IC Insights believes that the companies listed will represent essentially all the advanced 300mm IC production and capacity in the future.  IC Insights believes that the top seven or eight companies—Samsung, “Micron-Elpida,” TSMC, SK Hynix, Intel, Toshiba/SanDisk, and GlobalFoundries—can be considered an “elite” group that is just about guaranteed to be a driving force in 300mm capacity additions.  The remaining companies are likely to participate in future 300mm capacity expansion, but all have varying degrees of risk associated with fully realizing their long-term 300mm IC production capacity goals.

Meanwhile, there is still much uncertainty as to when the industry will make the next wafer-size transition—from 300mm to 450mm—and how much it will cost to do so, but momentum continues to build and the transition can now be considered certain to happen.  IC manufacturers have yet to fully optimize the high-volume manufacturing cost structure for the 300mm wafer size.  However, the potential per-die cost savings that the larger wafer can provide is enough of a motivating factor to make the transition happen.

Stretched-out clothing might not be a great practice for laundry day, but in the case of microprocessor manufacture, stretching out the atomic structure of the silicon in the critical components of a device can be a good way to increase a processor’s performance.

Creating "stretched" semiconductors with larger spaces between silicon atoms, commonly referred to as "strained silicon," allows electrons to move more easily through the material. Historically, the semiconductor industry has used strained silicon to squeeze a bit more efficiency and performance out of the conventional microprocessors that power the desktop and laptop computers we use each day.

However, manufacturers’ inability to introduce strained silicon into flexible electronics has limited their theoretical speed and power to, at most, approximately 15GHz. Thanks to a new production process being pioneered by University of Wisconsin-Madison engineers, that cap could be lifted.

Professor develops flexible electronics"This new design is still pretty conservative," says Zhenqiang (Jack) Ma, a professor of electrical and computer engineering. "If we were more aggressive, it could get up to 30 or 40GHz, easily."

Ma and his collaborators reported their new process in Nature Scientific Reports on Feb. 18, 2013.

Ma endeavored to address a paradox for straining and doping silicon electronics built on a flexible substrate. The straining process is similar to stretching out a t-shirt: the researchers pull a layer of silicon over a layer of atomically larger silicon germanium alloy, which stretches out the silicon and forces spaces between atoms to widen. This allows electrons to flow between atoms more freely, moving through the material with ease-just as a t-shirt stretched over a dummy will have more space between threads, allowing it to breathe.

The problem comes during the doping process. This necessary step in semiconductor manufacturing introduces impurities that provide electrons that ultimately flow through the circuit. Doping a stand-alone sheet of strained silicon is like ironing a decal onto a stretched t-shirt. Just as an ironed-on design cracks when the t-shirt is stretched and unstretched, the act of doping distorts the flexible free-standing silicon sheet, limiting its stability and usefulness as a material for integrated circuits.

Ma believes that using the material to design next-generation flexible circuits will yield flexible electronics that offer much higher clock speeds at a fraction of the energy cost.

"We needed to dope this material in a way that the lattice structure within would not be distorted, allowing for silicon that is both strained and doped," says Ma.

The solution is akin to dying a pattern into the fabric of a shirt, rather than ironing it on after the fact. Ma and his UW-Madison collaborators — Max Lagally, the Erwin W. Mueller Professor and Bascom Professor of Surface Science and Materials Science and Engineering; and Paul Voyles, an associate professor of materials science and engineering — have developed a process through which they dope a layer of silicon, then grow a layer of silicon germanium on top of the silicon, then grow a final layer of silicon over that. Now, the doping pattern stretches along with the silicon.

"The structure is maintained, and the doping is still there," says Ma.

The researchers call the new structure a "constrained sharing structure." Ma believes that using the material to design next-generation flexible circuits will yield flexible electronics that offer much higher clock speeds at a fraction of the energy cost.

The next step will be to realize processors, radio frequency amplifiers, and other components that would benefit from being built on flexible materials, but previously have required more advanced processors to be feasible. "We can continue to increase the speed and refine the use of the chips in a wide array of components," says Ma. "At this point, the only limit is the lithography equipment used to make the high-speed devices."

Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) has achieved a breakthrough in the manufacturing of power semiconductors on 300-millimeter thin wafers. In February, the company received the first customer go-aheads for products of the CoolMOS family produced by the 300-millimeter line at their site in Villach, Austria. The production process based on the new technology has completed qualification from start to finish and customers have given the go-ahead.

"Infineon put its faith in this manufacturing technology very early on and continued to invest even in economically difficult times. The qualification of our entire 300-millimeter line represents a veritable leap ahead of the competition," says Dr. Reinhard Ploss, CEO of Infineon Technologies AG. "300-millimeter thin-wafer manufacturing for power semiconductors will enable us, with the corresponding demand, to seize the opportunities that the market offers."

Infineon is the first and only company worldwide to produce power semiconductors on 300-millimeter thin wafers. Thanks to their larger diameter compared to standard 200-millimeter wafers, two-and-a-half times as many chips can be made from each one. Power semiconductors from Infineon feature low energy loss and compact design. Although not much thicker than a sheet of paper, the chips have electrically active structures on the front and back.

The next step is for the present manufacturing concept for CoolMOS products, qualified from start to finish, with the front-end site Villach and assembly of the thin chips at the back-end site Malacca, Malaysia, to be expanded to the front-end site Dresden. Here the focus is on high-volume production in a fully automated 300-millimeter line. The basis for the processes required and the manufacturing technology is currently being developed in research projects in Dresden. The technology transfer to Dresden is running on schedule and qualification of the first CoolMOS products will be completed in March. Shortly, in Villach more power semiconductor technologies will be transferred to the 300-millimeter line and produced. The development of the next power technology generation will focus on 300 instead of 200-millimeter technology.

"Our ability to innovate is the basis of our success – good ideas are turned into reality,” says Ploss. “In both Austria and in Saxony, we have the necessary conditions for this: technological know-how, well-educated and highly motivated specialists and exemplary support from government policy."

Last year, the independent research institute IMS Research (an IHS company) named Infineon as a market leader in power semiconductors. Infineon develops semiconductor and system solutions addressing three central challenges to modern society: energy efficiency, mobility, and security. In the 2012 fiscal year, ending September 30, the Company reported sales of Euro 3.9 billion with close to 26,700 employees worldwide.