Category Archives: Materials and Equipment

Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion, according to the 2013 edition of IC Insights’ McClean Report.  The increase lifted R&D spending by chip companies to 16.7% of total semiconductor sales in 2012, the highest level since the peak of 17.5% was reached in both 2008 and 2009.

For more than three decades, R&D spending as a percentage of total semiconductor sales has trended higher due to increasing costs associated with developing complex IC designs and creating next-generation process technologies to manufacture these circuits.  In the late 1970s and early 1980s, R&D spending as a percent of semiconductor sales by chip companies was typically 7-8%.  R&D-to-sales ratios grew to 10-12% of revenues by the early 1990s and then jumped to over 15% during the last decade, reaching a record 17.5% in 2008.

However, as shown in Figure 1, not all companies have seen a growing portion of sales consumed by R&D.  For example, Samsung’s R&D-to-sales ratio fell from a peak of 25% in 2001 to 8% in 2010 and has remained there since.  

Samsung’s semiconductor business is more capital-intensive than it is R&D-intensive because of the commodity nature of the DRAM and flash memory businesses in which it mainly participates.  As a result, since 2001, Samsung’s semiconductor sales have grown an average of 16% per year, while its R&D spending has increased at about one-third the rate (5%) and it’s capital expenditures have grown by an average of 19% annually.  The main focus of Samsung’s investments is in adding new fab capacity for large-diameter wafers (currently 300mm but heading toward 450mm later this decade).

Intel’s business is also capital-intensive.  Its spending on new fabs and equipment in each of the past two years was about $11 billion, which was only about $1 billion shy of what Samsung spent in each of those years.  Intel’s advanced microprocessors and other incredibly complex logic devices have very short life cycles.  Spending large amounts of money on research and development is part of its business model.  Intel’s $10.1 billion in semiconductor R&D spending in 2012 was more than 7x the amount spent by second-place Qualcomm!  In fact, Intel spent more than one-third of the combined $28.7B spent by the top-10 R&D spenders in 2012, according to the 2013 McClean Report.

Figure 1 also shows how much the industry’s largest pure-play foundry, TSMC, has been spending on R&D as a percent of sales over the past decade-and-a-half.  As the process technology needed for each new generation of ICs has become increasingly difficult to develop, fabless companies and the growing number of fab-lite companies have come to rely on TSMC not only for fabricating their wafers, but also for helping to bring their IC designs into existence.  As a result, TSMC’s R&D spending-to-sales ratio has been gradually climbing over the past 6-8 years.  TSMC’s spending ratio reached 8% in 2001, but that had a lot to do with the fact that its sales were hit hard by the industry recession that year.  Aside from a small dip in 2009, TSMC’s spending on R&D has grown every year since 1998 and at an average annual rate of 25%!  Over that same 1998-2012 timeperiod TSMC’s sales grew an average rate of 19% per year.

Design, assembly, inspection and repair personnel have a new tool to help improve reliability of ball grid arrays (BGAs) and fine-pitch ball grid arrays (FBGAs) in high density applications, thanks to the newly released C revision of IPC-7095, Design and Assembly Process Implementation for BGAs.

Published by IPC — Association Connecting Electronics Industries and developed with input from representatives from OEMs, fabricators, EMS companies and others in the electronics manufacturing industry, IPC-7095C addresses design and process considerations of particular importance to portable handheld products in which BGAs are a dominant interconnection technology.

 “Handheld products continue to shrink. At the same time, alloys, ball shape and attachment procedures are evolving,” says Ray Prasad of Prasad Consultancy Group, who helped spearhead development of the document. “That combination presents some unique challenges to product reliability that the new revision of IPC-7095 seeks to solve.”

A notable addition to the revised document is its inclusion of expanded information on mechanical failure issues such as PCB pad cratering or laminate defects that occur after assembly. In addition to providing guidelines for BGA inspection and repair, IPC-7095C addresses reliability issues and the use of lead-free joint criteria associated with BGAs. It also features numerous photographs of X-ray and endoscope illustrations to identify various defect conditions such as head on pillow, an incomplete and unreliable condition that can occur during BGA assembly processes.

Assumed failure mechanism for "head-on-pillow," also known as "head-in-pillow." Source: Renesas

IPC-7095C, Design and Assembly Process Implementation for BGAs, is 165 pages long. IPC members may purchase a hard copy of the document for $55; the industry price is $110. Single-user, site and global licenses are also available. For more information or to purchase a copy of IPC-7095C, visit www.ipc.org/7095.

STATS ChipPAC Ltd. (SGX-ST: STATSChP) and United Microelectronics Corp. (NYSE: UMC; TWSE: 2303) announced the world’s first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration. The 3D chip stack, consisting of a wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip, successfully reached a major milestone on package-level reliability assessment.

"The next level of chip integration is rapidly evolving, and 3D IC technology is poised to enable the next frontier of IC capabilities for customers under various deployment models," said Shim Il Kwon, VP of Technology Innovation of STATS ChipPAC.

S.C. Chien, vice president of Advanced Technology Development at UMC, said, "We see no imperative to restrict 3D IC to a captive business model, as UMC’s development work with nearly all the major OSAT partners for 3D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach. This model should work especially well for our mutual 3D IC customers, as foundry and OSAT can utilize their respective core strengths during development and delivery, while customers can benefit from keeping supply chain management flexible and realize better transparency over technology access compared to closed, captive 3D IC business models."

Under the 3D IC open development project with STATS ChipPAC, UMC provides the FEOL wafer manufacturing, with a foundry grade fine pitch, high density TSV process that can be seamlessly integrated with UMC’s 28nm poly SiON process flow. The know-how developed will be applied towards implementation on the foundry’s 28nm High-K/metal gate process. For MEOL and BEOL, STATS ChipPAC performs the wafer thinning, wafer backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking.

Renesas Electronics Corp. (TSE: 6723, Renesas) and J-Devices Corp. signed a memorandum of understanding regarding the transfer of the semiconductor back-end production business of three facilities operated by Renesas’ wholly owned manufacturing subsidiaries (the Hakodate Factory of Renesas Northern Japan Semiconductor, Inc. (Renesas Northern Japan), the Fukui Factory of Renesas Kansai Semiconductor Co., Ltd. (SKS), and the Kumamoto Factory of Renesas Kyushu Semiconductor Corp. (Renesas Kyushu)) and Renesas Northern Japan’s wholly owned subsidiary, Hokkai Electronics Co., Ltd. (Hokkai Electronics) to J-Devices.

This proposed transaction “aims at building a long-term, mutually beneficial relationship between the two companies as strategic partners in the semiconductor production business.” According to a press release.  The two companies plan to negotiate a final agreement and to complete the transfer in early June 2013.

The current employees of the transferred facilities will be “on loan” to J-Devices for a set period, under the premise that they will be reassigned to J-Devices on the basis of individual agreements in future. The Renesas products which will be manufactured at the facilities to be transferred will continue to be supplied by Renesas to customers with the quality, delivery schedules, service equal to or better than before even after the transfer.

In addition to the current seven facilities of J-Devices (Usuki, Oita Prefecture (Headquarters); Kitsuki, Oita Prefecture (Headquarters functions); Shibata-gun, Miyagi Prefecture; Aizuwakamatsu, Fukushima Prefecture; Miyawaka, Fukuoka Prefecture; Oita, Oita Prefecture; and Satsumasendai, Kagoshima Prefecture), the present transfer will add an additional three production facilities. This will make J-Devices one of the world’s top five OSAT (Outsourced Semiconductor Assembly and Test) service providers.

At the same time, the advantages gained as a long-term strategic partner of Renesas, including larger business scale, fusion of technical capabilities, and expanded product lineup, will enable J-Devices to improve cost competitiveness, technical capabilities, and product quality, allowing it to contribute to the continued development of the semiconductor industry as a world-top-level OSAT service provider and also providing substantial benefits for customers.

Renesas Electronics Corp. lays claim as world’s number one supplier of microcontrollers, and also offers SoC solutions and a range of analog and power devices. Business operations began as Renesas Electronics in April 2010 through the integration of NEC Electronics Corp. and Renesas Technology Corp., with operations spanning research, development, design and manufacturing for a wide range of applications. Headquartered in Japan, Renesas Electronics has subsidiaries in 20 countries worldwide. More information can be found at .

J-Devices is one of the largest independent semiconductor assembly and test company in Japan with seven factories in Japan. The original company (named Nakaya Microdevices) was established in 1970 and offers a broad lineup of packages including thermally enhanced BGA, CMOS sensor, leadframe and other original packages. J-Devices offers skilled package development as well as the full turnkey "one stop" service such as wafer sort, assembly, and final testing for consumer and automotive product.

January 24, 2012 – Imec and PVA Tepla say they have achieved void detection in through-silicon vias at wafer level, after TSV copper plating, thanks to a nondestructive high-frequency scanning acoustic microscopy (SAM) technique. The method also can be applied to detect voids in TSVs during processing, they claim.

The initial focus of their work was to develop metrology for detecting voids after temporary wafer bonding of 3D wafers, which remains challenging because development of interface particles and voids can impact subsequent wafer thinning processes, as well as overall wafer thinning and tool performance.

To address this, PVA Tepla and imec developed an automated foup-to-foup, wafer-level process based on 200MHz SAM using Tepla

frederic-raynalFrederic Raynal, CTO, Alchimer

Looking at 2014, we see challenges and innovations in both the front-end semiconductor and 3D TSV markets.

In the front end, we are seeing a focus on further scaling to smaller nodes. For logic, TSMC has just announced it is ready for 16nm node, and Intel is ramping to 14nm. Industry experts question whether shrinking to 10nm will be feasible from a technology perspective. For example, at 10nm, most of the layers in copper interconnection must be between 2 and 4nm thick, which poses challenges for the technologies used in volume manufacturing. Controlling the thickness of single as well as dual damascene layers requires new technologies, such as electrografting, which is much more controllable and able to meet emerging requirements. We strongly believe that new technologies will need to be introduced for logic at the 10nm node and memory at the 16nm node, with ramp occurring at the 10nm node for the industry to maintain the path of Moore’s law.

We also expect to see 3D TSVs ramping to production in 2014. This is another area where innovation is needed that can meet demanding performance requirements while controlling costs, since cost is currently holding back widespread adoption of 3D-ICs. High-aspect-ratio (HAR) vias are a good candidate for new technology like electrografting, which is cost competitive compared with electrochemical deposition, chemical vapor deposition or physical vapor deposition, and delivers higher performance. For example, 40:1 aspect-ratio capabilities were recently demonstrated for electrografted barrier and seed layers, and 20:1 aspect ratio for fill processes.

It is widely expected that both the front-end and packaging areas of the semiconductor industry are poised for growth in 2014. Continued technology innovations will be a key driver in both areas in order to meet emerging performance requirements while successfully controlling cost and overcoming current roadblocks.

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January 11, 2012 – GlobalFoundries says it plans to build a $2 billion R&D facility at its Fab 8 campus in Saratoga County, NY. The new Technology Development Center (TDC) will span more than 500,000 sq. ft of "flexible space" for various technology development and manufacturing activities, including cleanroom and lab space. Construction is planned to begin in early 2013 and completed in late 2014.

The TDC will focus on a variety of semiconductor development and manufacturing work "to support the transition to new technology nodes," and development of "innovative capabilities to deliver value to customers beyond the traditional approach of shrinking transistors," according to the company. Broadly speaking, the TEC is planned to be a collaborative space to develop "end-to-end solutions covering the full spectrum of silicon technology," from EUV lithography photomasks to new interconnect and packaging technologies enabling 3D chip stacking, "and everything in between."

"As the industry shifts from the PC era to a market focused on mobile devices, we have seen increasingly strong interest from customers in migrating to advanced nodes on an accelerated schedule," stated GlobalFoundries CEO Ajit Manocha. "To help facilitate this migration, we are making significant investments in strengthening our technology leadership, including growing our workforce and adding new capabilities to make Fab 8 the hub of our global technology operations." Toward that end, "the new TDC will help us bridge between the lab and the fab by taking research conducted with partners and further developing the technologies to make them ready for volume manufacturing," he added

Other regional New York State leaders chimed in with appreciation and optimism for the project’s synergy with the local and regional economy. "New York has become the world’s hub for advanced semiconductor research and now, the Technology Development Center will further help ensure the innovations developed in New York, in collaboration with our research institutions, are manufactured in New York," said Governor Andrew M. Cuomo. "New York State’s public investments to develop CNSE as a hub of innovation coupled with the private investments of GLOBALFOUNDRIES are prime examples of best practices for public-private partnerships linking research, innovation and production that have made New York a globally recognized center of innovation," added Charles W. Wessner, director of the National Academies’ Innovation Program.

GlobalFoundries began developing its Fab 8 project in the summer of mid-2009; today its campus includes approximately 2 million sq. ft of development. The company has continued to make investments in manufacturing production as well as technology development, including work underway on 20nm and 14nm technology nodes.

By Julian Gates, Managing Director, AG Semiconductor Services

The multibillion-dollar secondary or used semiconductor equipment market has gone through significant changes over the past five years and has become increasingly sophisticated in its approach, with industry leaders offering a full range of services well beyond the tool purchase itself. The days of a broker trying to sell a piece of chipmaking gear of uncertain condition and provenance out of a crate on a warehouse floor are numbered. IC manufacturers trying to balance cost considerations with the need to upgrade or expand their production capability can now partner with secondary equipment services firms that offer economical turnkey solutions combining tool configuration, refurbishment, installation, start-up and support with a risk-reducing warranty package that largely mirrors that of an original equipment manufacturer.

Since most OEMs have focused their efforts on the development and proliferation of their 300mm equipment suites and have either reduced or eliminated their 200mm offerings, many semiconductor companies need support in enhancing their existing 200mm production lines, or with converting from 150 to 200mm wafer size operations. Some firms lack the internal human resources or technical proficiency to handle the equipment aspects of the ramp by themselves. With dedicated expertise in 200mm systems, the full-service secondary equipment firm can provide a project management team to the customer site that will work with the device-maker to help get the facility’s toolset up and running.  

Another trend in the used equipment space we’re seeing is the synergistic combination of dedicated remarketing services with turnkey solution capabilities. Done well, these services increase the amount and diversity of a secondary equipment company’s inventory and provide customers more flexibility and velocity in their ability to buy and sell surplus equipment.

Analysts forecast that wafer fab utilization will increase in 2013 and gain momentum into 2014, which means that chipmakers will soon begin to invest in production equipment to meet the demand curve of the emerging upcycle in the market. For those seeking to gain the most out of their capital budgets, the availability of more high-quality pre-owned 200 and 300mm equipment backed by comprehensive service and support packages offers a financially attractive, low-risk path to fulfilling their capacity requirements.

Jim Mello, Vice President, Sales and Marketing, Entrepix, Inc.

The global economic difficulties are impacting the semiconductor industry more now than ever because the world has become increasingly interconnected and more consumer driven. The financial crisis in Europe, the "fiscal cliff" in the US and the slow down in China’s growth have made it more difficult for any one catalyst to push the markets in a positive direction. Ultimately, the semiconductor industry is caught up in this environment and its outlook continues to be mixed, which points towards a flat 2013. While smart phones and tablets will continue to drive the markets for communication chips, CMOS image sensors and many other types of sensors, the semiconductor industry will not be able to overcome the stagnation of the PC market. The momentum for more powerful, smaller and faster portable devices will dominate the PC market, continuing to drive smaller system packaging technologies and less power consumption while creating more functionality and memory capacity. Technology investments will continue for the advanced nodes and leading edge packaging development, but until the confidence of the economy comes back, the capacity investments will be selective based on individual markets. 

One of the biggest challenges for the industry is that 80 percent of the devices used for portable and mobile applications are currently manufactured on 200mm or smaller wafers. How this plays out going forward could change who the dominant players will be and therefore could drive consolidation. As the communications market advances, design wins play a large role in the uncertainty. The secondary equipment market provides ongoing opportunities throughout the entire market, especially during periods of economic difficulty, and is extremely well positioned to capitalize on the continued strength of the 200mm market. Remanufactured equipment continues to demonstrate its viability within the industry, often being sold with guaranteed reliability and shorter lead times that allow for capacity investments that can accommodate changes in short term demand. Additional value-add can be found in the secondary market from a subset of suppliers who are specialized in specific processes. These vendors provide process development and fully qualified processes to customers to accelerate the manufacturing ramp and further enhance the cost of ownership benefits of refurbished equipment.

By Ardy Johnson, Vice President of Marketing and Product Management, Rudolph Technologies, Inc.

Advanced packaging is in the early stages of a dynamic growth phase. Demand for equipment and related tools in the 3DIC and wafer-level packaging area is forecasted to grow from approximately $370 million in 2010 to over $2.5 billion by 2016. Advanced packaging requirements are driving the evolution of back end manufacturing to become more similar to the front end where the need to tie the entire process together with effective process control has long been established. Rudolph, with a long history in both the front end and back end, is participating fully in this evolution with a “total solution” approach, as exemplified by our recent entry into the back end photolithography market.

Ideally, a photolithography solution for advanced packaging begins with a reduction stepper that is uniquely capable of meeting current and future requirements of advanced packaging processes: greater depth of focus to handle the thicker resists required by exaggerated wafer topography; flexible automation and specialized handling for warped wafers, reconstituted wafers, and large panels; on-the-fly focusing at every exposure to ensure maximum image quality; and an on-board reticle library and fast-change reticle wheel for increased productivity. But the full power of the total solution derives from integrating the stepper with a suite of inspection and metrology tools and process control software: an inspection tool for CD overlay measurements; APC software for closed loop, run to run control; and a yield management system to provide fab-wide, automated, real-time process control feedback.

Fleet management provides another example of the use of automated data collection and analysis to increase equipment uptime, improve yield, and reduce production costs. It monitors the output and operational parameters of inspection and metrology tools performing similar tasks to detect statistical excursions that indicate tool health and stability. One important benefit of fleet management is the ability to improve tool matching-based actual performance.

As backend processes continue to evolve, incorporating the next generation packaging technologies needed to reduce size and increase functionality is a necessity, and manufacturers will derive increasing value from an integrated, total solution approach.