Category Archives: Materials and Equipment

By Arthur W. Zafiropoulo, Chairman and CEO, Ultratech, Inc.

After all the speculation, discussions and debates, the transition to 450-mm wafers will happen.  As an equipment manufacturer, it is not enough to simply survive, but it is imperative to thrive in the transition to 450mm. While driven by all the major semiconductor companies, the transition to 450-mm wafers will have a compounding effect on equipment manufacturers’ R&D investments. By combining the technology challenges and the wafer diameter change, companies in the equipment industry will require a strong balance sheet to be successful.

Smart companies know that success lies in the ability to be bold and aggressive in R&D and remain conservative on the balance sheet. Success is also determined by a company’s efforts to prepare for the future by investing and developing the right technologies and supporting capabilities. By developing innovative technologies that address the critical issues around the transition and adoption, companies can play an enabling role for 450mm. At Ultratech, we have prepared for the transition to 450mm in our design concepts for our laser spike anneal (LSA) and advanced packaging systems. Both of these products offer the lowest technical risks due their scanning and step and repeat processes. We have added a new inspection technology targeted at device, wafer stress and pattern overlay, which will quickly identify yield and device performance issues.

To provide our customers with competitive advantages, Ultratech introduced seven advanced technology products in 2012 and each one serves a different market. With our LSA technology already proven to reduce stress on the wafer, we introduced two dual-beam laser systems that are built on the Unity Platform™, and are easily scalable for 450-mm applications. We believe the 450-mm LSA systems will provide the industry with new process capabilities that did not previously exist, and the first system will be delivered to the G450 Consortium at the end of 2013.

Also, Ultratech has developed a new technology, Superfast 3G, based on patented coherent gradient sensing technology (CGS) for inspection using a fundamental stress measurement technique to analyze deformation on a microscale over the entire wafer. The system has the flexibility to be implemented anywhere in the production line―front-, middle- and back-end-of-line―to address stress issues confronting leading-edge device manufacturers. 

The development of innovative technologies that solve the critical issues for the transition and adoption of 450-mm manufacturing will be the defining factor for whether a company merely survives or thrives. Ultratech is a company that is thriving.

By Christian Gregor Dieseldorff, director, SEMI Industry Research & Statistics, San Jose, CA USA  

Despite difficult times, growing demand for mobile devices (such as tablets and phones) inspires an improved outlook for chip sales in 2013.  Various forecasts range from 4% to 16% revenue growth for 2013 (average of forecasts 7%). As observed in the past, chip sales and capex typically ride the same roller coaster; however, 2013 appears to be another year of uncertainty. While chip sales may rise in 2013, expectations for equipment range from timid 5% growth down to double-digit decreases — definitely not the same roller coaster.

The largest spenders on fab equipment are Samsung, TSMC and Intel.  As of mid-December 2012, some of these companies still have not made any official announcement about 2013 capex plans.

The SEMI Consensus Forecast and the SEMI World Fab Forecast, with data collected from two different methodologies, point to the same conclusion.  The year-end Consensus Forecast for wafer processing predicts 0% growth (flat) for 2013.  Meanwhile, the World Fab Forecast report for Front End Fabs (published November 2012) also shows 0% growth (flat) for 2013 and total fab equipment spending hovering at US$ 32.4 billion (including Discretes and LEDs, used equipment and in-house equipment).  The projected number of facilities equipping will drop, from 212 in 2012 to 182 in 2013. Fab equipment spending saw a drastic dip in 2H12 and, accounting for seasonal weakness and near-term uncertainty, will be even lower in 1Q13.  Examining equipment spending by product type, System LSI is expected to lag in 2013. Spending for Flash declined rapidly in 2H12 (by over 40%) but is expected to pick up by 2H13. The foundry sector is also expected to increase in 2013, led by major player TSMC, as well as Samsung, Globalfoundries and UMC.

While fab construction spending slowed in 2012, at -15%, SEMI data projects an increase of 3.7% in 2013 (from $5.6 billion in 2012 to $5.8 billion in 2013).  The World Fab Forecast tracks 34 fab construction projects for 2013 (down from 51 in 2012).  An additional 10 new construction projects (with various probabilities) may start in 2013. The largest increase for construction spending in 2013 is expected to be for dedicated foundries and Flash-related facilities.

In 2012, many device manufacturers stopped adding new capacity due to declining average selling prices and high inventories. This is most pronounced in the Flash sector, as seen with Sandisk since the beginning of 2012, and both Samsung and Toshiba starting 3Q12.

Breaking down the industry by product type, capacity growth for System LSI is expected to decrease in 2013. Flash capacity additions dragged in 2H12. But more activity is expected for Flash by mid-2013, with nearly 6% growth. The data also point to a rapid increase of installed capacity for new technology nodes, not only for 28nm but also from 24nm to 18nm and first ramps for 17nm to 13nm in 2013.

If the global economy and GDP begin to improve, and chip sales actually do increase in the higher single-digit range, equipment spending is expected to ride the same roller coaster, going even higher for 2013.

December 29, 2012 – Industry watchers have been lowering their outlooks for 2013 over the past few weeks, but there’s one set of opinions that still see optimism for an industry rebound in 2013 — chip industry executives themselves.

In its annual study, KPMG found three quarters of semiconductor executives polled believe they will see revenue growth in the next fiscal year — that’s up from 63% in last year’s survey. Two-thirds expect to hire more workers (vs. 48% in 2011), and 71% say annual industry profitability will increase in 2013. Overall their sentiment is for a recovery that builds up steam especially heading into the second half of the year.

KPMG’s Global Semiconductor Survey, conducted in September, surveyed 152 semiconductor industry business leaders (primarily senior-level execs) at device, foundry, and fabless manufacturers, half of whom have annual revenue of $1 billion or more. Overall, its "Semiconductor Business Confidence Index" climbs to 57, stepping across the 50/50 threshold into optimism vs. the index of 46 recorded a year ago. Among its other findings:

— More activity, inside and out. Seventy-three percent of respondents expect to increase capital spending over the next fiscal year, up from 51% a year ago — and 24% expect to increase spending by 10% or more, vs. 10% of respondents in late 2011. Just 6% of respondents expect capital spending cuts, s. 18% a year ago. Similarly, 77% of execs expect semiconductor-related R&D spending to increase in 2013, up from just 65% a year ago. And two thirds of execs expect more merger and acquisition deals in fiscal 2013, up from 62% a year ago looking into 2012’s crystal ball.

— The US is tops again. Execs placed the US ahead of China in the most important geographic markets for semiconductor revenue growth three years out — for a third consecutive year, fewer see China as their most important market. Next in priority are Europe, Korea, and then Taiwan — which two years ago was ranked 2nd and slightly ahead of the US, but might be losing favor due to exposure to softer Japanese and Chinese economies, according to Gary Matuszak, global chair of KPMG’s Technology, Media and Telecommunications practice. Also, "significantly" fewer chip execs viewed China as a top-three hiring market in 2013; it’s still in first place, but the US and Europe are gaining favor.

— Consumer is king, redux. Consumer applications are officially the most important revenue driver, as viewed by the chip execs over the next fiscal year; computing now ranks third, behind wireless. "Unlike past recoveries, this one won’t be driven by wireless handsets and wireless communications alone," said Matuszak. Other revenue-driving apps — industrial, medical, automotive (with many sub-applications in body electronics, communications convergence, and safety), and power management (a big feature in wireless devices) — were emphasized by more chip execs in this year’s survey than in the past three years. That’s a clear indication how semiconductors have proliferated beyond traditional wireless and computing applications, such as mobile commerce and various automotive functionalities, added Ron Steger, global chair of KPMG’s Semiconductor practice. Also getting a big push from semi execs: "renewal energy" such as battery technologies, listed by 53% of execs as an important revenue driver over the next three years, up from just 36% a year ago.

Percentage of survey respondents who expect their company’s semiconductor-
related capital spending to increase over the next fiscal year. (Source: KPMG)

At the recent Georgia Tech-hosted International Interposer Conference, Matt Nowak of Qualcomm and Nagesh Vordharalli of Altera both pointed to the necessity for interposer costs to reach 1$ per 100mm2 for them to see wide acceptance in the high-volume mobile arena. For Nowak, the standard interposer would be something like ~200mm2 and cost $2. The question that was posed but unanswered was: "Who will make such a $2 interposer?"

Less than a month later, this question began to be answered as several speakers at the year-ending RTI ASIP conference (Architectures for Semiconductor Integration and Packaging) began to lift the veil on silicon interposer pricing.

Sesh Ramaswami, managing director at Applied Materials, showed a cost analysis which resulted in 300mm interposer wafer costs of $500-$650 / wafer. His cost analysis showed the major cost contributors are damascene processing (22%), front pad and backside bumping (20%), and TSV creation (14%).

Ramaswami noted that the dual damascene costs have been optimized for front-end processing, so there is little chance of cost reduction there; whereas cost of backside bump could be lowered by replacing polymer dielectric with oxide, and the cost of TSV formation can be addressed by increasing etch rate, ECD (plating) rate, and increasing PVD step coverage.

Since one can produce ~286 200mm2 die on a 300mm wafer, at $575 (his midpoint cost) per wafer, this results in a $2 200mm2 silicon interposer.

Lionel Cadix, packaging analyst of Yole D

December 20, 2012 – Global spending on wafer fab equipment (WFE) is now on pace to finish 2012 with a -17% annual decline, and 2013 now looks like it’ll only be slightly better at a -10% dropoff, before the next cyclical spending upturn begins in 2014, according to an updated forecast from Gartner.

The firm now sees 2012 WFE investments coming in at about $29.9B, a -17.4% decline from 2011. That compares with an earlier projection of a -13% decline made in October, which was itself a downward revision (-9% in June, -11% in March). Those numbers are slightly steeper, but the trend is similar, to SEMI’s recent projections which also predict a rebound coming in 2014.

The environment has softened significantly in just the past few weeks, Gartner says, as the macroeconomic suffering takes a toll on consumer spending, which trickles down to overall capital spending (equipment plus facilities services, etc.) — which Gartner now sees declining -10.7% in 2012 vs. its -9.3% forecast in the third quarter. That will be followed by another -14.7% decline in 2013, as semiconductor manufacturers deal with excess capacity and a slow macroeconomy.

"Although a period of inventory correction that led to lowered production levels in the first half of 2012 appears to be over, inventories remain at critical levels," Johnson warned. "High inventories, combined with overall market weakness, will continue to depress utilization rates into the first half of 2013."

The year started off strong for wafer fab equipment spending as chipmakers ramped sub-30nm production and needed new tools to prop up yields, but as yields improve that equipment demand is softening, explains Bob Johnson, research VP at Gartner. Overall yields will touch bottom below 80% by the end of 2012 and slowly creep up to around 85% by the end of 2013, Gartner says; leading-edge utilization will be a bit higher as always, moving from mid-80% up to the low-90% range over the same period.

There’s hope on the horizon, though. Memory and logic spending should realign in 2014 with "substantial increases" in investments, followed by a flat to slightly positive 2015. look for a new WFE growth cycle starting in 2014, and lasting through 2016.

Here’s how Gartner sees things shaping out near-term, by technology investment:

— Memory: Continuing to be weak through 2013, with maintenance-level investments for DRAM and a slightly down NAND market until supply and demand are in balance.

— Foundry: Spending will increase 7.4% in 2013, as both IDMs and semiconductor assembly/test services (SATS) companies absorb spending declines.

— Logic: The only positive driver for capital investments in 2012 increasing just 3%, Gartner notes, thanks to the aforementioned sub-30nm ramp. Smartphones and media tablets won’t be enough to bring up utilization levels to where chipmakers need them, though, Johnson notes.

Projected global spending on semiconductor manufacturing equipment, in US $M. (Source: Gartner)

December 19, 2012 – Singapore’s Institute of Microelectronics (IME), a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR), has launched a new multiproject wafer service (MPW) for 2.5D through-silicon interposers, to provide a cost-effective platform for R&D prototyping and proof-of-concept in the technology.

The 2.5D interposer MPW service, supported by IME’s 3D through-silicon via (TSV) engineering line, includes the following modules:

  • Leveraging industry standard Electronic Design Automation (EDA) tools to perform 2.5D TSI design, extraction and verification;

  • TSV with critical dimension (CD), e.g. 10-50

December 17, 2012 – Samsung Austin Semiconductor sent out a PR last week about previously announced $4B investments in its Austin, TX facilities. The site is on schedule for production in 2H13 for mobile application processors (28nm process technologies on 300mm wafers). Samsung Austin Research Center also is adding about 200 engineers to fuel this effort, according to the company. The commitment — representing the largest single foreign investment ever made in the state of Texas — will bring Samsung’s total investment in its Austin Semiconductor unit to more than $15B since 1996.

The original Samsung Austin investment announcement — much less this update, thin on new details — wasn’t exactly a surprise; a 3Q12 retrofit had been seen as one of the key capex drivers for the latter half of this year. Samsung is expected to push its capex by 11% in 2012 to $13.1B, just ahead of Intel’s $12.5B (16% Y/Y growth) — together representing fully 40% of worldwide capital spending this year.

In a quick research note, Barclays’ CJ Muse notes that Samsung’s overall capex could be as much as halved this year (a -30% to -50% range), with most of it coming from the logic side due to an Apple defection. He currently models Samsung LSI’s capex in 2013 declining about 25% to KRW 6 trillion (~$5.4B), and possibly even more, and that it will focus on a 32nm-to-28nm transition, i.e. "spending will be shrink-oriented vs. capacity-oriented." Near-term, Muse sees Samsung’s orders, currently at "negligible levels," as possibly picking up in 1H13 to support this Austin push. He thinks this will contribute to an overall sector-wide orders environment of "flattish to slightly up (in-line with expectations)."

Another thing this announcement accomplishes, Muse notes, is a signal to the marketplace that Samsung is still investing to remain competitive with TSMC. Apple has openly partnered with Samsung in Austin to make the "engine" of the iPhone and iPad, despite the two companies’ fierce and broad competition in finished electronics devices. That business is in doubt, though, as many speculate about the electronics giant will seek other noncompetitive partners for future chip orders. With this $4B pledge, even if Samsung loses Apple’s business, it is sending a message to other fabless firms who may decide to grab some of that vacated capacity in 2013-2104.

December 17, 2012 – Tezzaron Semiconductor has licensed patents regarding Ziptronix’s direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), for use in 3D memory.

Bob Patti, CTO of Tezzaron, pointed to "a direct and robust synergy" between his company’s FaStack 3D technology and Ziptronix’s technologies, calling them "a formidable team." (The two companies have been partnering on 3D ICs since 2005.) This deal broadens Tezzaron’s capabilities in producing advanced 3D memories and extends the scope of 3D and 2.5D devices it can assemble for customers. "With this suite of powerful technologies, we offer a truly ‘one-stop’ solution for both 3D and 2.5D," he said.

Traditional die stacking requires die thinning and thinned-die handling and development of reliable interconnect processes. Ziptronix DBI combines proprietary wafer-level low-temperature oxide bonding and interconnection. It creates extremely strong low-stress bonds, allowing wafers to be processed and thinned after bonding, eliminating the need to handle thinned wafers and/or dies. Interconnect density and alignment accuracy are high, and the device profile is kept low, Ziptronix notes. The process is compatible with damascene interconnect processing, and various test and repair strategies.

DBI was originally used for backside imaging (BSI) sensors, where Ziptronix claims it delivers cost savings of up to 80% over copper thermo-compression bonding. Earlier this year the company helped a memory manufacturer use the new technology in place of standard die stacking, enabling wafer-level stacking to increase memory density and significantly reduce packaging costs. At the time the company had hinted more licensing deals outside the image sensor space were in the pipeline.

"With our DBI, which contains interconnect at the bond interface, Tezzaron can provide a technologically superior product in the memory market at a lower cost and better performance compared to competitors also attempting 3D integration of advanced memory devices," stated Ziptronix CEO Dan Donabedian. "Tezzaron stands alone today in its adoption of the most advanced interconnection technology and therefore will lead the industry in technology areas only imagined just a few short years ago."

Rudolph Technologies, Inc. (Nasdaq: RTEC) has entered the back-end advanced packaging lithography market, with the acquisition of Azores Corp., and the introduction of a new 2X reduction stepper called the JetStep. The move puts the company squarely in competition with San Jose-based Ultratech, Inc., which claims 80% of the existing market with a 1X proximity projection system.

The JetStep, based in part on Azores’ 6200 platform which was developed for LCDs, has several advantages over the 1X approach, according to Rudolph, which has added its own wafer handling and software to the system. . System advantages include the largest printable field-of-view, programmable aperture blades and large on-tool reticle library, large depth-of-focus along with autofocus to accommodate 3D structures in advanced packaging, very large working distance, and warped wafer handling (+/- 6mm). The system also feature programmable wafer edge protection, enabling a variable edge exclusion zone of 0.5-5 mm. The system also features a large (17mm) working distance between the lens and wafer, which helps avoid a common maintenance issue on 1X systems. “It’s critical to have an ample depth of focus,” said Elvino da Silveira, president and CEO of Azores (Wilmington, MA), who will stay on to head the Rudolph lithography group.

In addition, with its flat panel lithography heritage, the JetStep System incorporates Azores’ high precision grid motor stage. This provides a flexible platform that can be readily scaled to changing substrate sizes and types in the advanced packaging market. It can handle both standard and reconstituted 300mm and 330mm wafers, all panel sizes and is 450mm capable.

Commenting on the new product and the acquisition, Paul F. McLaughlin, chairman and CEO of Rudolph, said: “The JetStep System is a disruptive innovation in the back-end lithography market, addressing the technical and economic advantages demanded for advanced packaging. The Azores acquisition uniquely positions Rudolph in the back-end stepper advanced packaging photolithography market with a significantly expanded business model, and we believe that by offering the industry’s only total solution to advanced packaging lithography, we can more than double Rudolph’s total back-end addressable market.”

“Specifically, the advanced packaging market needs a stepper supplier willing to be flexible and capable of delivering unique solutions for their requirements, and a process control partner that can deliver improved production systems for advanced packaging applications,” McLaughlin noted. “By leveraging R&D investments from both the Rudolph and Azores organizations, we took a field-proven 2X display lithography technology and applied it to the needs of the high-growth back-end packaging market where Rudolph already has long-standing customer relationships and global brand recognition. In short, we have changed the game,” McLaughlin said.

Strategically, the deal doubles the combined companies’ backend market presence, giving Rudolph a foothold in backend litho for advanced packaging, points out Credit Suisse analyst Satya Kumar. This $150M-$200M market is currently "fragmented among proximity aligners" targeting lower-end bumping and steppers for wafer-level packaging applications, he notes, with the latter (~$100M market) currently dominated by UTEK (as mentioned above).

One JetStep tool has already been placed at a subcontract customer, according to Rudolph; Kumar speculates it’s STATS-ChipPAC.

Financially speaking, the deal should be accretive in 2013, contributing ~$20M in revenues (roughly 10% of the combined company’s total sales). Rudolph expects 100-200 basis points impact to gross margins in the near term, but operating margins should smooth out to corporate average in over the next year or so.

In an IC fab, cycle time is the time interval between when a lot is started and when it is completed. The benefits of shorter cycle time during volume production are well known: reduced capital costs associated with having less work in progress (WIP); reduced number of finished goods required as safety stock; reduced number of wafers affected by engineering change notices (ECNs); reduced inventory costs in case of a drop in demand; more flexibility to accept orders, including short turnaround orders; and shorter response time to customer demands. Additionally, during development and ramp, shorter cycle times accelerate end-of-line learning and can result in faster time to market for the first lots out the door.

Given all the benefits of reducing cycle time, it’s useful to consider how wafer defect inspection contributes to the situation. To begin with, the majority of lots do not accrue any cycle time associated with the inspection, since usually less than 25 percent of lots go through any given inspection point. For those that are inspected, cycle time is accrued by sending a lot over to the inspection tool, waiting until it’s available, inspecting the lot and then dispositioning the wafers. On the other hand, defect inspection can decrease variability in the lot arrival rate—thereby reducing cycle time.

Three of the most important factors used in calculating fab cycle time are variability, availability, and utilization. Of these, variability is by far the most important. If lots arrive at process tools at a constant rate, exactly equal to the processing time, then no lot will ever have to wait and the queue time will be identically zero. Other sources of variability affect cycle time, such as maintenance schedules and variability in processing time, but variability in the lot arrival rate tends to have the biggest impact on cycle time.

In the real world lots don’t arrive at a constant rate and one of the biggest sources of variability in the lot arrival rate is the dreaded WIP bubble—a huge bulge in inventory that moves slowly through the line like an over-fed snake. In the middle of a WIP bubble every lot just sits there, accruing cycle time, waiting for the next process tool to become available. Then it moves to the next process step where the same thing happens again until eventually the bubble dissipates. Sometimes WIP bubbles are a result of the natural ebb and flow of material as it moves through the line, but often they are the result of a temporary restriction in capacity at a particular process step (e.g., a long “tool down”).

When a defect excursion is discovered at a given inspection step, a fab may put down every process tool that the offending lot encountered, from the last inspection point where the defect count was known to be in control, to the current inspection step.  Each down process tool is then re-qualified until, through a process of elimination, the offending process tool is identified.

If the inspection points are close together, then there will be relatively few process tools put down and the WIP bubble will be small.  However, if the inspection points are far apart, not only will more tools be down, but each tool will be down for a longer period of time because it will take longer to find the problem.  The resulting WIP bubble can persist for weeks, as it often acts like a wave that reverberates back and forth through the line creating abnormally high cycle times for an extended period of time. 

Consider the two situations depicted in Figure 1 (below). The chart on the top represents a fab where the cycle time is relatively constant. In this case, increasing the number of wafer inspection steps in the process flow probably won’t help.  However, in the second situation (bottom), the cycle time is highly variable. Often this type of pattern is indicative of WIP bubbles.  Having more wafer inspection steps in the process flow both reduces the number of lots at risk, and may also help reduce the cycle time by smoothing out the lot arrival rate.

 

Because of its rich benefits, reducing cycle time is nearly always a value-added activity. However, reducing cycle time by eliminating inspection steps may be a short-sighted approach for three important reasons. First, only a small percentage of lots actually go through inspection points, so the cycle time improvement may be minimal. Second, the potential yield loss that results from having fewer inspection points typically has a much greater financial impact than that realized by shorter cycle time. Third, reducing the number of inspection points often increases the number and size of WIP bubbles. 

For further discussions on this topic, please explore the references listed at the end of the article, or contact the first author.

Doug Sutherland, Ph.D., is a principal scientist and Rebecca Howland, Ph.D., is a senior director in the corporate group at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

References

1.       David W. Price and Doug Sutherland, “The Impact of Wafer Inspection on Fab Cycle Time,” Future Technology and Challenges Forum, SEMICON West, 2007.

2.       Peter Gaboury, “Equipment Process Time Variability: Cycle Time Impacts,” Future Fab International. Volume 11 (6/29/2001).  

3.       Fab-Time, Inc.  “Cycle Time Management for Wafer Fabs:  Technical Library and Tutorial.”

4.       W.J. Hopp and M.L. Spearman, “Factory Physics,” McGraw-Hill, 2001, p 325.