Category Archives: Materials and Equipment

by Mark Danna, VP of business development, Owens Design

Continuing a series of columns for SST, Mark Danna from Owens Design highlights common mistakes that can cause an outsourced partnership to fail and detail a methodology for approaching an outsourcing agreement that can minimize the risk and costs involved and help ensure a successful partnership.

October 12, 2012 – One of the toughest things about getting started on a tool development design and build project is that in most cases the overall requirements for tool functionality and performance have not been focused yet. Nevertheless, the group tasked with tool development responsibility is told to get moving on the project because "we are already late." In fact, from the point of view of most of those involved, the picture of what is needed is still kind of fuzzy and none of the critical details are well-defined.

It is, however, possible to launch the project, get it off the ground, and make progress while still clarifying tool specifications and requirements. A disciplined phased approach to the program can resolve many of these open issues (technical, commercial and market-related) in the first phase of any project.

For example, at the start of most tool development projects there usually is a gap between desired tool functionality and target tool cost. The engineers want to design the tool to meet all potential market requirements and perform at the highest level. The marketing group wants a tool that meets a specific set of market requirements and can be produced at the lowest cost possible. Very early in the program a functional/cost trade-off analysis needs to be done — and well understood — by both parties before tool specifications and performance can be agreed upon and finalized. One of the most critical parts of finalizing the tool specification is to really understand how the functionality of the tool will be validated at the end of the program. Without an agreed-upon functionality test, tool performance cannot be validated and the specification is meaningless.

Unfortunately, not all tool functionality can be nailed down in the first phase of the tool development project. For some projects, it is standard procedure for final tool production launch to begin before the overall tool characterization has been completed. During this process, if overall tool functionality changes significantly, tool specification changes are the inevitable result and most likely will affect overall tool design. Going into this phase with a tool design that can accommodate a wide range of design parameters can minimize the risk of a total design restart. The trade-off, of course, is that this increase in functionality will most likely lead to an increase in overall tool cost. By thinking about these potential issues early on, it may be possible to minimize the impact of design-related change by having the ability to easily change the design to meet the tool requirements once overall tool functionality has been solidified.

A lack of clarity early on in design requirement can exist whether the project is handled as an in-house development project or is outsourced. If it’s an outsourced project, the selection of a design-and-build partner and its ability to help clarify and focus the development effort is critical to the overall success of the program. While there is always a desire in a tight economy to keep as many costs in-house as possible, the money spent engaging the right outsource design-and-build partner at the beginning is likely to end up benefiting the project budget long-term. Where a typical equipment OEM may produce a new tool every couple of years, a good outsource partner might go through this development process 10-20 times per year. As a result, this outsource design-and-build partner will have established and proven procedures that can take that fuzzy picture at the beginning of the project and put it into focus.

Time must be committed early in the development phase of a project to bring the fuzzy parameters into focus. Tool cost vs. functionality trade-offs must be well understood by all stake holders. By leveraging either in-house or outside expertise in project planning and management, as well as design input from the very beginning, one can end up saving a lot of time, money, and aggravation.

Mark Danna is VP for new business development at Owens Design.

Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.” The four groups, Silicon Saxony (Dresden/Germany), DSP Valley (Belgium), Minalogic (Grenoble/France) and Point One (Eindhoven/Netherlands), will be cooperating in research, development and business expertise.

Together they represent about 800 research institutes and companies, which account for more than 150,000 jobs; among the companies are global market leaders such as Philips, NXP, Globalfoundries, Infineon, STMicroelectronics, Schneider Electric und Thales.

This is a three year effort, as shown in the diagram. “We want to set up a joint action plan that is organized between the four clusters,” said Frank Bösenberg, in charge of administration of Silicon Europe, speaking at a press conference in Dresden. “Not only this, in the third year, we also want to start implementing this action plan. It’s not only about creating paper, but doing some action. In addition to this, we want to involve if possible additional European players.”


 “Global competition is tough and investments into European microelectronics are declining”, says Jean Chabbal, Chief Representative and CEO at the French Cluster Minalogic (Grenoble/France). In 2007 only 10% of all worldwide investments into microelectronics, around 28 billion Euro, went to Europe, while about 48% went to Asia. Since 2000 Europe’s market share in the semiconductor industry has dropped from 21 to 16 percent, yet the European microelectronics sector still employs 135,000 people directly along with another 105,000 in its supplier industries. “Europe is home to a number of the world’s best known, and most active regions in the micro- and nanoelectronics industry and the semiconductor industry, more specifically. These clusters, established over many years, with strong consolidated structures from industry, research and local governments, serve all application fields of micro- and nanoelectronics and have access to the most advanced research and key competencies – the European micro- and nanoelectronics sector must take advantage of this leading position and further expand upon it. This is the only way for Europe to maintain its role as a world-renowned leader in technology research and development”, continues Jean Chabbal.

Silicon Saxony (Dresden) is a unique conglomeration of companies with know-how in micro- and nanoelectronics, photovoltaic, organic and printed electronics, energy efficient systems, communications technology and sensor networks. More than 300 cluster partners employ 48,000 people. 

At the cluster Minalogic (Grenoble) 204 cluster partners with more than 39,000 employees develop modern micro- and nanoelectronics and integrated system-on-chip technologies. Their work applies to the sectors energy efficiency, connectivity and mobility, health systems and traditional industries. 

Point-One (Eindhoven) connects 170 cluster partners, who jointly develop solutions for mechatronics, integrated systems, photonics and micro-and nanoelectronics. Their solutions apply to lighting systems, to semiconductor and photovoltaic production and also the mobility, logistics and security branches. 

The 75 partners of the technology cluster DSP Valley (Leuven) are focusing on the development of hardware and integrated software technology for digital signal processing and system-on-chip solutions. 

Silicon Europe calls for a European ICT-Summit

 “Our activities and plans will not end at national borders as they did before – Silicon Europe stands for the common interest of the European microelectronics industry”, explains Peter Simkens, Managing Director at the Belgian Cluster DSP Valley. “However, to be successful in the long run, Silicon Europe and European microelectronics need active political support. We are appealing to all national governments to increase the synchronization of their economic and innovation policy with the European Commission and its guidelines. In order to realize this we are calling for a European micro- and nanoelectronics summit, which – similar to the German IT summit – shall bring together leading actors and decision makers from the European Commission, the national governments and all relevant branch organizations and associations. The European economy needs to expand on its strengths now, if it wants to remain competitive in the global market for the long run.”

Transnational Cluster Alliance as a new impetus

“Silicon Europe stands for a new quality of an European industry policy”, says Thomas Reppe, General Manager of the German Cluster Silicon Saxony. “In close cooperation with regional development agencies and institutes we transfer the cluster concept of Saxony’s Research Cluster for Energy Efficiency ‘Cool Silicon’ – the strong cooperation across organizational and institutional borders – onto a transnational level. Through this new and strong cluster alliance we are securing not only Europe’s current know-how in production of KET relevant technologies, but we are also working together on a strategic technology roadmap, which can serve the European Commission as a template and development guide for future programs.”

Silicon Europe offers a platform for active exchange among the clusters and their nearly 800 members, including internationally leading corporations; more than 75 percent of all partners are small and medium sized businesses. By performing a detailed analysis of each of the four cluster’s main research topics and by synchronizing their activities, previously unused synergies are being utilized.

Europe 2020

By intensifying transnational cooperation of regional research-oriented competence clusters, Silicon Europe will make a substantial contribution to “Europe 2020”, the EU growth strategy for the coming decade. The program’s focus is the advancement of research and development as a basis for a modern and strengthened European society. “With their activities, the European Commission aims at a digital and resource-efficient development – for both of these core goals micro- and nanoelectronics are a decisive factor”, says Eelco van der Eijk, contact person for the high-tech industry at the Dutch Ministry of Economic Affairs.  One of the key words for these activities is ‘smart specialization’ – the EU’s control mechanism to tailor and efficiently distribute development funds in the European technology regions.

Michael Kretschmer, Vice-Chairman of the CDU Parliamentary Group at the German Bundestag, member of the German Bundestag and member of the Committee on Education, Research and Technology Assessment explains his support for the initiative: “The Europe-Cluster of the micro- and nanoelectronics sites is a very important signal for both German and European politics. Together and across national borders we have to ensure that this key technology still has a home in Europe in the future. In the past, European clusters seldomly worked together – luckily, this is going to change now. I appreciate the Silicon Europe initiative and wish for it to find numerous supporters and advocates also in the German Bundestag and the German government. The high-tech nation Germany can simply not forego these technologies that by enabling innovations in various industries create jobs and prosperity”.

 

 

October 5, 2012 – Tessera Technologies (Nasdaq:TSRA) is giving CEO Robert A. Young a big financial incentive to spin off one of its two businesses within the next several years, one of the company’s key long-term strategic goals. The directive, issued by the board of directors and compensation committee, authorizes immediate vesting of 550,000 stock options at their Oct. 2 pricing, worth roughly $7.54M. It’s contingent on successful spin-out of one of the company’s business units by March 31, 2015; if no spinoff happens by that date, the promised stock options will expire.

"The 2012 compensation arrangement provides an additional financial incentive for Bob to pursue a key strategic alternative, and reflects the board’s continuing efforts to closely align executive compensation with the best interests of stockholders," stated company chairman Robert J. Boehlke.

Tessera Technologies is a holding company with operating subsidiaries in two segments. Its Intellectual Property unit handles license agreements with semiconductor companies and outsourced semiconductor assembly and test companies, while a Digital Optics division covers imaging and optics products and capabilities.

Reuters quotes Tessera’s newly appointed CFO, Richard Neely, suggesting the strategy centers on the digital optics side of the business: "We’ve been talking about building up the digital optics business and spinning it off." He was hired in August 2012 to build up the Digital Optics business "into a global, vertically integrated supplier of original design camera modules for handsets and other applications," while also helping grow the IP licensing business.

In a related SEC filing, Tessera reveals more of the incentive plan, as well as more details of Young’s overall compensation scheme — including his base annual salary ($684,000), potential annual bonuses equaling that salary, and $150,000 per year to offset expenses from traveling between his Connecticut home and the company’s offices in California.

Tessera currently projects 3Q12 sales of $66.5M-$69.0M, up 8%-12% from 2Q12. Most of that is in the IP licensing side ($53.0M-$54M, flat with 2Q), helped by a recent settlement with Amkor Technology. The digital optics business is expected to generate $13.5M-$15.0M in sales in 3Q, up from $8.4M in 2Q12.

October 4, 2012 – Fab equipment spending continues to soften in 2012, but don’t hope for a reprieve until later in 2013, warns one analyst.

Worldwide wafer fab equipment (WFE) spending is projected at $31.4 billion in 2012, a -13.3% decline from 2011, according to Gartner. But counter to some other industry watchers, the firm now thinks there won’t be a big rebound in 2013 — it’s now forecasting a -0.8% slip next year to $31.2B, before finding its footing again and bouncing back in 2014 with 15.3% growth to $35.9B.

Earlier this summer Gartner foresaw a -8.9% decline in 2012, followed by 7.4% growth in 2013. Less than a month ago SEMI predicted 2013 could be a "golden year" with nearly 17% growth in fab spending.

"The outlook for semiconductor equipment markets has deteriorated as the macro economy has weakened," stated Bob Johnson, research VP at Gartner. After starting the year strong thanks to sub-30nm production ramps at foundries and other logic manufacturers, demand for new equipment logic production will soften as yields improve, leading to declining shipment volumes for the rest of the year."

Fab utilization rates will erode to the low 80% range by the end of this year, slowly increase to about 87% by the end of 2013. (That’s less optimistic than its June outlook which saw mid-80% in mid-2012 and 87% by the end of the year.) Leading-edge capacity will recover slightly better, hitting the high-80% range by year’s end and gradually getting into the low-90% range as 2013 progresses.

Increased demand combined with less-than-mature yields at the leading edge had been hoped to consume extra capacity and raise utilization rates. In leading-edge logic that has in fact helped create inventory shortages, Johnson noted, but "not enough to bring total utilization levels up to desired levels. In the memory segment, some suppliers are even cutting production in an attempt to shore up weak market fundamentals."

Memory is expected to be weak through 2012, with strong declines in DRAM investments and a virtually flat NAND market, the firm notes. Foundry spending has been revised downward for both 2012 and 2013; some foundries have improved their 28nm yields, but mainly for SiON technology, as 28nm high-k/metal gate (HKMG) processes are still yielding below normal. Longer-term, Gartner thinks foundries will ratchet up their spending more in future years due to aggressive development of EUV lithography and 450mm wafer processing.

October 4, 2012 – Applied Materials says it will reduce its work force by between 6% and 9% (900-1300 positions) amid a global realignment deemed necessary to achieve certain strategic objectives, freeing up to $190M annually "to fund key growth initiatives."

The plan is twofold, according to the company: a voluntary retirement program for certain US employees meeting minimum age and service term requirements (and other non specified business-related criteria), and a subsequent further global workforce reduction, the scope of which will depend upon participation in that voluntary retirement program "and other considerations." The restructuring plan is expected to be substantially completed by the end of fiscal 3Q13 (end of July 2013), and free up $140M-$190M annually "to fund key growth initiatives."

"Achieving our strategic objectives requires us to deploy our talent in the best way possible," stated chairman/CEO Mike Splinter. "We are taking action to realign our worldwide organization and workforce while investing in key product development capabilities that will enhance our ability to grow."

The plan will result in pretax restructuring charges (severance and other termination benefits) of $180M-$230M, substantially all of which will be in cash. These charges will be recorded starting in fiscal 4Q12 (the current quarter, ending in October) and continuing through fiscal 2013.

UPDATE 10/4: First analysis out of the gate comes from Barclays’ CJ Muse, who thinks the cuts will primarily be overhead/corporate functions across all divisions, while the reinvestments will target the Silicon Services Group (technical marketing support, field service, and R&D) to reinforce leadership and recapture lost share in wafer-fab equipment (specifically process control and etch, deposition, CMP, and implant). Moreover, the move likely means a de-emphasis on the company’s Displays division and EES, the latter of which could see reduced breakeven or even an exit. "Let the turnaround begin," he proclaims, with these reinvestments representing a first step in a "transformation" to increasing its focus to core competencies, lowering its breakeven profit points, and boosting EPS.

Deutsche Bank’s Vishal Shah agrees the moves are a longer-term strategic play, and not a response to near-term sluggishness: "Today’s restructuring announcement is a step in the right direction as the company repositions to gain share over the next 3-5 years." He also points out that the company is choosing to cut back spending in corporate overhead and reallocate costs, instead of increasing opex.

by Dan Tracy, senior director, SEMI Industry Research and Statistics

October 3, 2012 – Semiconductor manufacturers in Japan are either consolidating or closing fabs, and, in several cases, transitioning to a "fab-lite" strategy, all in a restructuring effort to meet the market challenges ahead. While device manufacturers are consolidating manufacturing operations and plan to outsource more wafer fabrication and package assembly to foundries and packaging subcontractors, a large installed fab capacity remains in Japan. Recent data for the year shows overall wafer area shipments into Japan’s fabs being the same as shipments into Taiwan.

By 2014, the total installed fab capacity Japan should increase slightly from about 4.5 million to 4.6 million 200mm equivalent wafers per month. Installed 300mm fab capacity is expected to increase from about 760,000 to 840,000 300mm wafers per month — representing, by region, the third largest 300mm fab manufacturing capacity base globally. Over the next several years, fab spending in the Japan market will be directed towards the production of NAND flash memory, power semiconductors, high-brightness LEDs, and CMOS image sensors.


Regional share forecasted for 2013 fab materials market. Total market size: $25.7 billion.

Overall equipment spending in Japan will likely range on the order of $4 billion per year. Expected NAND flash investments in 2013 could approach up to $2.5 billion. LED fab equipment spending is estimated to be $340 million next year. Finally, Sony is expected to invest about US$ 1 billion or more in its CMOS image sensor production.

Japanese equipment and material suppliers are leading players on the global semiconductor industry stage. It is estimated that Japan-headquartered equipment companies collectively capture about 35% share of the global semiconductor industry spending per annum. Like their North American and European counterparts, customers in the rest of the Asia Pacific region are the largest base for new equipment sales.

Chemical and other material suppliers in Japan are market leaders in the manufacturing of silicon wafers, III-V wafers, advanced chemicals, packaging resins, and packaging substrates. It is estimated that the Japanese material suppliers sales represent about 70% of the global semiconductor materials market, both fab and packaging.

Japanese suppliers showcase the latest products at SEMICON Japan 2012

Leading Japanese equipment and materials suppliers will exhibit at SEMICON Japan 2012 on December 5- 7, along with global key players, at the Makuhari Messe, Japan. Find the latest products and innovations this companies offer to customers globally that enable key technologies for the future including 450mm, EUV, TSV, power devices, and HB-LEDs to name a few. Also, the show will co-locate with a major photovoltaic show, PVJapan 2012 so you can connect to two major microelectronics industries in a single visit.

For more information, including registration and exhibition, visit www.semiconjapan.org/en.

September 26, 2012 – EV Group says it has received an order for its EVG850 temporary bonding/debonding systems from a leading maker of compound semiconductor-based components, what it says is the first use of its ZoneBOND technology in this area.

"The compound semiconductor market has always been a front runner in driving the introduction of new temporary bonding/debonding technologies, starting from solvent-assisted debonding, tape debonding, slide off debonding and now ZoneBOND," noted Dr. Thorsten Matthias, business development director for EVG. The company has provided other equipment into compound semiconductor manufacturers for over 10 years, he noted, and introducing ZoneBOND "is a natural evolutionary step" in standardizing processes and equipment and widening options for bonding during thin-wafer processing.

EV Group and Brewer Science codeveloped the ZoneBOND technology, which works with silicon, glass, and other carriers and existing adhesive platforms. Debonding can take place at room temperature with virtually no vertical force on the device wafer. ZoneBOND defines two carrier wafer zones, with strong perimeter adhesion and minimal center adhesion. This allows wafer grinding and backside processing at high temperatures, while enabling low-force separation. The polymeric edge adhesive can be removed by solvent dissolution or other means.

Earlier this year Brewer released its own Cee 1300CSX thin wafer debond system that also incorporates the ZoneBOND technology, specifically targeting III-V and CS materials.

September 21, 2012 – Demand for chip tools fell again in August and is off by -30% from its peak in early summer, fulfilling fears that the second half of 2012 will be sluggish for chipmaking investments, according to the latest data from SEMI.

North America-based manufacturers of semiconductor manufacturing equipment reported $1.12B in orders worldwide in August (a three-month moving average), down -9.2% from July’s slightly downwardly revised level of $1.23B and down -3.6% from a year ago. Worldwide billings slipped to $1.34B, off by -7.4% from a similarly lowered mark in July and off by -8.4% from the same month in 2011.

For the year through August, chip tool bookings are running about -8% off the same pace in 2011 ($10.97B), with billings off by about -15% at $11.16B, according to SEMI’s historical data. Demand clearly peaked in the spring, flattened in the summer, and has now waned significantly. Global demand for semiconductor manufacturing equipment actually started slipping in 2Q12 with softness in just about every region except Taiwan. (As bad as the current pullback is, it’s a far cry from the -40+% dropoff seen toward the end of 2011.)

"The second half of the year continues to show reduced order and billing levels for the 2012 spending cycle," said Dan Tracy, senior director of SEMI Industry Research and Statistics. Industry watchers already were expecting a pullback in demand especially in 3Q12 (and so are the chipmakers themselves), with mixed feelings about a possible bump in 4Q12.

SEMI’s still sticking with its official forecast issued at SEMICON West which predicts a -2.6% decline for the year. "We expect 2012 equipment revenues to decline slightly with total spending for front-end and back-end semiconductor equipment globally remaining at the $40 billion or greater level for the third consecutive year," reiterated Tracy.

SEMI is growing increasingly bullish, however, for 2013, with initial projections of 17% growth in equipment spending.

  Billings Bookings Book-to-bill
March 1,287.6 1,445.7 1.12
April 1,458.7 1,602.8 1.10
May 1,539.3 1,613.7 1.05
June (f) 1,535.7 1,424.3 0.93
July (r) 1,442.8 1,234.6 0.86
August (p) 1,335.5
 1,120.6
 0.84

Semiconductor bookings and billings, 3-month averages. (Source: SEMI)

Flexible circuitry promises a host of innovative biomedical, security, wearable and other products. To date, flexible circuits have offered only limited performance because plastic substrates aren’t compatible with the high temperatures/harsh processes needed to make high-performance CMOS devices.

Some attempts have been made to fabricate high-performance CMOS on silicon substrates and then transfer the devices to plastic, but this has been complex and expensive. At the International Electron Devices Meeting (IEDM), for the first time, a way around this will be unveiled. IBM researchers will demonstrate high-performance state-of-the-art CMOS circuits —including SRAM memory and ring oscillators—on a flexible plastic substrate. The image above is a photo of the final 100-mm-diameter flexible ETSOI circuit on plastic.

The extremely thin silicon on insulator (ETSOI) devices had a body thickness of just 60 angstroms. IBM built them on silicon and then used a simple, low-cost room-temperature process called controlled spalling, which essentially flakes off the Si substrate. Then they transferred them to flexible plastic tape.

The devices had gate lengths of <30 nm and gate pitch of 100 nm. The ring oscillators had a stage delay of just 16 ps at 0.9 V, believed to be the best reported performance for a flexible circuit. A slight degradation of delay for the flexible sample after the layer transfer comes from degradation of p-FET performance due to strain effects.

The image below is a cross-sectional view taken by a TEM electron microscope after selective removal of the residual silicon, confirming the structural integrity of the device.

 

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