Category Archives: Materials and Equipment

The 58th annual International Electron Devices Meeting (IEDM) will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.

Highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include Intel’s unveiling of its industry-leading trigate manufacturing technology; a plethora of advances in memory technologies from numerous companies; IBM’s demonstration of high-performance logic technology on flexible plastic substrates; continuing advances in the scaling of transistors to vanishingly small sizes, and breakthroughs in many other areas that will continue to move electronics technology forward.

“The IEDM can be a crystal ball looking into the future of technology evolution. Leading-edge technologies and novel devices reported at the conference will shine light on the industrial mainstream in the next three-to-five years,” said Tzu-Ning Fang, IEDM 2012 Publicity Chair and Senior Member, Technical Staff, at Spansion, Inc. “This year’s program shows a tremendous amount of work being done in emerging technologies, including novel materials such as molybdenum sulfide, new structures, 3D NAND memories, wider use of III-V materials, MRAM, nanowires and more.”

Besides the IEDM technical program, attendees will enjoy evening panel sessions, Short Courses, award presentations and other events, as follows:

90-Minute Tutorials — Saturday, Dec. 8

Back by popular demand for the second year, the IEDM will hold 90-minute tutorial sessions on emerging topics presented by experts in the fields. They are meant to bridge the gap between established textbook-level knowledge and the leading-edge research as presented during the conference. The tutorial sessions will be presented in parallel in two time slots. Advance registration is required.

2:45-4 p.m.

High Mobility Channel CMOS Transistors – Beyond Silicon by Shinichi Takagi, University of Tokyo

Fundamentals of GaN Based High Frequency Power Electronics by Tomas Palacios, M.I.T.

Spintronics for Embedded Non-Volatile Electronics by Tetsuo Endoh/Tohoku University and Arijit Roychowdhury/Intel

4:30-6:00

2D semiconductors – Fundamental Science and Device Physics by Ali Javey, University of California, Berkeley

Scaling Challenges of Analog Electronics at 32nm and Beyond by Mustafa Badaroglu/IMEC and Bram Nauta/University of Twente

Beyond Charge-Based Computing by Kaushik Roy, Purdue University

Short Courses — Sunday, Dec. 9

The IEDM offers two day-long short courses on Sunday, prior to the technical sessions. They provide the opportunity to learn about emerging areas and important developments, and to benefit from direct contact with expert lecturers. Advance registration is required. This year’s courses are:

Emerging Technologies for Post-14nm CMOS

Circuit and Technology Interaction

Plenary Presentations — Monday, Dec. 10

IEDM 2012 will open on Monday, Dec. 10 at 9 a.m. with three plenary talks:

Flexible Bio-Integrated Electronics by John A. Rogers, University of Illinois

State of the Art and Future Prospects in Display Technologies by Joo-Tae Moon, Senior VP, Director R&D Center, Samsung Display Company

Ultimate Transistor and Memory Technologies: Core of a Sustainable Society by Luc Van den hove, CEO and President IMEC

Emerging Technologies Session — Tuesday morning, Dec. 11

This year’s Emerging Technologies session is on the topic Spintronics: Magnetic Materials and Device Applications, organized by Stefan De Gendt of IMEC. Invited speakers from academia and industry will discuss the challenges, prospects and recent advances in spin-based technology, devices and systems. Following the discovery of the giant magnetoresistance (GMR) effect more than a decade ago, this field has witnessed a veritable revolution encompassing materials and physical phenomena. Electronic devices based on spin transport are expected to play a major role in future information and communication technologies, as spintronic devices will use the spin degree of freedom to store, transport and process information. Papers in this session are:

Spin Transport in Graphene: Fundamental Concepts and Practical Implications by Abdelmadjid Anane et al, Unité Mixte de Physique CNRS/Thales

Thermal Spin Transport and Applications by S. Y. Huang et al, Johns Hopkins/National Tsing Hua University/Academia Sinica

Progress of STT-MRAM Technology and the Effect on Normally-Off Computing Systems, by H. Yoda et al, Toshiba

 Spin Transport in Metal and Oxide Devices at the Nanoscale, by Subir Parui et al, Zernike Institute for Advanced Materials

Error Immunity Techniques for Nanomagnetic Logic, Brian Lambson et al, University of California, Berkeley/Lawrence Berkeley National Lab

Boolean and Non-Boolean Computation With Spin Devices, Mrigank Sharad et al, Purdue University

Luncheon Presentation — Tuesday, Dec. 11

The IEDM Luncheon presentation will be given by Ajit Manocha, CEO of GLOBALFOUNDRIES, Inc., on the topic Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!

Evening Panel Sessions — Tuesday evening, Dec. 11

The IEDM will offer attendees two evening panel discussions. Audience participation is encouraged, with the goal of fostering an open and vigorous exchange of ideas. The panel topics are:

"Will Future Non-Volatile-Memory Contenders Disrupt NAND?" moderated by Al Fazio, Intel

 “The Mighty Little Transistor: FinFETs to the Finish or Another Radical Shift?” moderated by Suresh Venkatesan, GLOBALFOUNDRIES.

Entrepreneurs Lunch — Wednesday noon, Dec. 12

New for 2012 is an entrepreneurs lunch. The speaker will be Weili Dai, cofounder of Marvell Technology Group and Vice President and General Manager of Marvell’s Communications and Consumer Business. One of the most successful women entrepreneurs in the world, she was named No. 89 on the Forbes list of “The World’s 100 Most Powerful Women” earlier this year.

Further information

For registration and other information, interested persons should visit the IEDM 2012 home page at www.ieee-iedm.org.

Singapore’s A*STAR’s Institute of Microelectronics (IME), and Hitachi Chemical Co., will be collaborating on a joint research program to develop high performance material technologies for thin wafer processing for 3D IC packaging.

"Our expertise, experience and infrastructure in 2.5D/3D IC process-integration, thin-wafer-handling, and assembly flow provide a compelling value proposition for advanced materials manufacturers to test their products and overcome key technical barriers in the commercialization of 2.5D/3D IC technology,” said Prof. Dim-Lee Kwong, Executive Director of IME. “IME is in a strong position to enable materials development that is increasingly critical to ramping advanced packaging technologies to high volume manufacturing.”

The Interconnect and Packaging Program (IPP) at IME focuses on strategic research areas in the research and development of 3DIC and TSV technologies, including: 3D stacking with chip-to-wafer (C2W) and wafer-to-wafer (W2W) bonding technologies, embedded wafer level packaging, integrated passive device (IPD) with Si or polymer substrate, MEMS packaging, electrical, thermal, mechanical design, materials, process and reliability.

Due to the temperature-hermeticity-sensitivity of the MEMS/MOEMS devices and the thermal-stress effects of the 3D stacked dies, there is a critical need for lower wafer bonding temperatures of below 200°C. At IME, the current R&D focus on low-temperature processes includes: Wafer-to-wafer bonding of hermetic sealed MEMS/MOEMS devices, and chip-to-wafer bonding of 3D stacking with TSV technology and microbump interconnects.

3D research at IME is also focused on TSV formation, including:

•           Dielectric isolation materials and processes

•           High-speed via architectures and filling methods

•           Electrical design and characterization of Si-interposer

•           Global/local design and modeling of interconnects of Cu/ultra low-k large chips

•           Microbump interconnection design, materials, assembly processes and reliability

“IME has strong background technologies of microelectronics, especially in IC packaging technologies, and Hitachi Chemical has many kinds of material for the electronics. I believe this joint research between IME and Hitachi Chemical will contribute greatly to the progress in advanced 3D IC packaging technologies.” said Shun-ichiro Uchimura, Vice President and CTO of Hitachi Chemical.”

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September 10, 2012 – EV Group (EVG), St. Florian, Austria, has updated its modular EVG 150 automated resist processing system to address specific needs for backend lithography, conformal coating, and planarization. The new system was announced at last week’s SEMICON Taiwan.

The newest version of the EVG150 high-volume coater/developer performs spin coating, developing, spray coating and lift off on 50-200mm wafers, enabling up to four wet process modules combined with two stacks of hot plates, chill plates, and vapor prime modules. Two key additions include EVG’s OmniSpray technology (with proprietary ultrasonic nozzle), which allows the conformal coating of high topography surfaces (e.g. ultra-thin, fragile, or perforated wafers) and can result in up to 80% reduced material consumption vs. traditional spin coating, according to the company. The other key addition is the NanoSpray coating technique to coat surfaces with vertical sidewall angles — for example, processing through-silicon vias (TSV) with polymer liners and photoresist.

EVG reps summarized the additions for SST:

  • A modular design allowing roll-in/-out of process modules, for enhanced uptime and serviceability

  • A new spray coating module (the company’s OmniSpray technology) with x,y (raster) spray coating

  • A new module for the company’s proprietary "NanoSpray" process for coating blind vias

  • A new structural frame with most chemicals stored within the main frame, to shorten point-of-use and optimize process control

  • CIM Framework software, to help meet rigorous requirements for uptime, process control, and fab automation

"Close collaboration with our customers made it clear that the next logical step for our coater/developer technology was to create a universal approach for high-volume processing of devices with more complicated structures and topographies," stated Markus Wimplinger, EV Group’s corporate technology development and IP director.

 

Left: Vias with 1:5 aspect ratio, conformally coated with NanoSpray. Right: Top edge of
spraycoated cavity (cavity 150

September 4, 2012 – Ultra Tec Manufacturing has released a new endpoint detection module for its ASAP-1 IPS selected area preparation system, for improving electronic package decapsulation and sample preparation.

The patent-pending hardware/software enhancement to the ASAP-1 IPS provides the capability to quantify and act upon the capacitive and/or resistive properties of electronic device and packaging materials, in order to enhance the sample preparation process. Such "controlled microsurgery" with interactive endpinting opens the door for improved resolution in various microscopy techniques (SQUID, INSB thermography/lock-in, thermal laser stimulus) without fully exposing the die topside or by stopping a few microns before target on silicon from the backside.

Ultra tec’s ASAP-1 IPS is a digital sample preparation system for the decapsulation, thinning and polishing of packaged and wafer-level devices. The new endpoint module will be available for demos at the upcoming International Symposium for Testing and Failure Analysis (ISTFA) conference in Phoenix, AZ, Nov. 11-15).

A 4

September 4, 2012 — Wafer probe card maker FormFactor, Livermore, CA, has agreed to acquire fellow probe card supplier MicroProbe, San Jose, CA, for $100M in cash and $16.8M in stock. The deal, subject to customary conditions, is expected to close by the end of this year.

MicroProbe generated $87.3M in revenue for its fiscal 2011 (ended Dec. 31), with 46% Y/Y growth and a non-GAAP EBITDA profit margin of 20%.

The combined entity will, according to the companies, be the industry-leading supplier of advanced system-on-chip (SOC) probe cards, with technology leadership in both memory and SOC probe card markets. The entity also will see "improved and immediately accretive financial performance" by the beginning of 2013, they claim.

FormFactor was unseated as the longtime top nonmemory probe card supplier in VLSI Research rankings earlier this year; it now ranks second with $162M in 2011 sales, with Microprobe listed fourth. Combined they would rival Japan’s Micronics ($242M) which assumed the top spot. VLSI projects probe card sales will be flat in 2012 but overall growing steadily over the next five years, reaching $1.5B by 2016.

"This merger is a transformational event for FormFactor," stated FormFactor CEO Tom St. Dennis. "The combined company will have the technology and resources to address semiconductor test requirements across the entire advanced probe card space."

"This merger enables our world-class teams to accelerate innovation in wafer test across our customer base and provides compelling opportunities for our combined employees," explained Mike Slessor, CEO of MicroProbe, who will become SVP and executive officer of the combined companies.

"Together, we are in position to focus on delivering leading wafer probe solutions to meet the needs and roadmaps of logic and memory semiconductor device manufacturers," added FormFactor chairman Carl Everett.

Bruker said that a leading semiconductor supplier purchased multiple ContourGT-X 3D optical microscope systems for its packaging factories in Asia and North America to support copper wire bond inspection and process control needs.  According to Bruker, the production-level speed of the ContourGT-X can lower manufacturing costs and assists in solving critical problems in the transition to copper-based processes from more expensive gold-based processes. “Since copper is harder and more brittle than gold, our customers need to precisely monitor the correct amount of force applied to the bond connecting the die to the package lead-frame or substrate,“ said Mark R. Munch, Ph.D., president of the Bruker Nano Surfaces division.

“In addition to the inherent 3D optical metrology advantages of the ContourGT-X, we have added a lot of features that are specifically designed to aid wire bonding applications,” explained Rob Loiterman, Executive Vice President and General Manager of Bruker’s Stylus and Optical Metrology business. “For example, a line engineer can create specific recipes that are automatically linked via operator ID, material ID, or lot/inspection ID. These software controls provide accurate real-time identification and flagging of good and bad product so our customers can ensure the reliability of their products, while taking advantage of the lower cost of copper.”

Kulicke & Soffa Industries, Inc. (Nasdaq: KLIC) launched its next generation manual wire bonder series, the iBond5000.  The series, which is based on the company’s 4500 line, includes ball, wedge and dual-capability bonding options. Targeted applications include optoelectronic modules, hybrids/MCMs, microwave products, discrete devices/lasers, chip-on-boards, leads, sensors, and high power devices.

Improved features of the iBond5000 include the addition of a multi-core ARM based processor and 7” touch screen.  With the improved electronics management, there are also more ways to connect to the iBond5000 via two USB ports for a mouse, keyboard or disk on key; or via Ethernet which allows for centralized management, access to an applications backup server, and capability for remote support and profile sharing.  For those that prefer working with physical controls, an optional analog panel is available.  The system enables saving and loading of custom files, along with factory preconfigured profiles, for storing, cataloging, and re-using golden processes.

Hesse & Knipps, Inc., the Americas subsidiary of Hesse & Knipps Semiconductor Equipment GmbH, added the HBK08 Loop Former Bondhead to its BONDJET BJ935 and BONDJET BJ939 fully automatic heavy wire bonders. It is designed to support growing requirements for high density module bonding, enabling extremely long wire loops, special wire loop formations and minimal wire distances for fine pitch bonding in addition to multi-stitch bonding. 

The HBK08 Loop Former Bondhead enables the formation of loops or wire bridges with lengths up to 40mm and low loop heights with considerably higher wire stability than previously possible on any heavy wire bonder. A controlled bend induced into the wire by the loop former of the bondhead during the loop trajectory within <50 ms creates a considerably steeper loop fall in the back part of the wire bridge compared to conventional loop forms. With this loop formation, the distance of the wire bridge to the neighboring live circuit paths can be increased, creating a positive influence on the design rules of power modules.

Fine pitch heavy wire bonding – for example 600 µm pitch for 400 µm wire – requires a significantly smaller wire guide. The HBK08 Bondhead incorporates a symmetrical (closed) wire guide with a 70° guide angle to implement considerably larger loops with minimal distances.

Other key features of the HBK08 Bondhead include:

•  Boxlight – a coaxial illumination source attached directly to the bondhead minimizes the distance to the object being illuminated, allowing homogenous illumination of highly reflective surfaces up to a 5° tilt.

•  Slim “Wire” Cutter – a specialized wire cutter developed for fine pitch heavy wire bonding incorporates a considerably steeper front-cut angle.

•   Air “Wire” Cut – this feature enables "touch-free" wire cutting that eliminates surface touchdown, enabling the use of front-cut on highly sensitive chip surfaces.

•   3 Mil Wire Capability – Addressing the worldwide increase in demand for 3 mil wire, the new bondhead processes gold, aluminum and copper bonding wire with diameters from as small as 3 mil up to 20 mil (75 μm up to 500 μm).

Hesse & Knipps will demonstrate the new features available on the BJ935 Fully Automatic Heavy Wire Bonder at the upcoming 45th International Symposium on Microelectronics (IMAPS) in Booth No. 210. IMAPS 2012 is scheduled for September 9 – 13, 2012 at the San Diego Town & Country Convention Center in San Diego, California, USA.

August 24, 2012 — The Securities and Exchange Commission (SEC) adopted a rule mandated by the Dodd-Frank Wall Street Reform and Consumer Protection Act to require companies to publicly disclose their use of conflict minerals that originated in the Democratic Republic of the Congo (DRC) or an adjoining country.

The regulatory reform law directed the Commission to issue rules requiring certain companies to disclose their use of conflict minerals that include tantalum (Ta), tin (Sn), gold (Au), or tungsten (W) if those minerals are