Category Archives: Materials and Equipment

A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).  “The biggest trend for the last couple of years has been 3D and TSV and it continues to be that way,” said David McCann of GLOBALFOUNDRIES and ECTC conference chair.  This year, the conference features a set of sessions specifically on 3D TSVs, with minimal overlap.  There’s also an additional session specifically on interposers, otherwise known as 2.5D. “The industry really wants to see 2.5D happen as an easier way to do 3D before all the 3D tools are in place,” McCann said. “The struggle is over how much is an interposer going to cost.”

Presently, that struggle appears to be between glass and silicon, where glass is a less expensive alternative. “Glass would be a cheaper approach to silicon interposers, but is limited to line space and via diameter,” McCann said. “Glass is not able to get as dense as silicon.” He said there may be a bifurcated market on interposers, where the high end is on silicon, and the low end is on glass. High end applications are devices such as microprocessors, which need high density, 1 micron lines and spaces. Low end devices are capabilities such as RF.  

In terms of when TSVs will move into volume production for mainstream applications, McCann said that RF devices that already have TSVs because they have backside contact. Next, memory devices are in line to for TSV production. “I think there will be more and more memory stacks,” he said. Fabricating a memory stack internally for a memory company is easy (at least compared to alternative approaches) in that it doesn’t require an outside standard to be able to do the connection between the devices. “Next will be wide I/O or whatever wide I/O morphs into, maybe wide I/O2, where you get an apps processor with a wide I/O DRAM on top of it,” McCann said. “I think we’ll see those starting in 2013, first products in the industry and 2014 for adoption into 20nm. And then, following that, it’s very dependent upon standards. Wide I/O standard is critical for getting multiple memory suppliers to supply memory or a consuming company to use multiple suppliers,” he said.  “Standards are going to enable products and those first 3D products are going to use devices that already exist and put TSVs into them.”

The real potential of 3D integration will come around 2017 or 2018, McCann believe, when heterogeneous stacks with different devices with different functions, such as memory, digital, analog , RF and power, are integrated in a stack. “There will be design tools that optimize the design of those devices for placement of blocks, TSVs and bumps  for optimal performance. In the first products, we won’t have so much optimization, but more enablement, and then where we all really want to get to is that optimization of performance, “ McCann said. “What that will look like is say a bit of memory just above a processing cell, right where you want it. Or the analog the right where you want it to be placed with this very short vertical interconnect to the circuitry that it needs to communicate with. We’ll get to optimal block placement when the tools start getting available to help us co-design devices from different manufacturers for optimal performance.”  

McCann acknowledged that testing these complex 3D stacks will be a major challenge, saying is revolves very much around IP. “If you think about DRAM and how it’s tested, it’s all internal to the DRAM company and it’s very tightly protected IP. Nobody wants to let that outside, understandably. Then you start thinking about 2.5D and 3D where you’ve got integrated memory – how do you do that? The assembly of those is not going to be at the memory manufacturer,” he said.

McCann believe stacked memory will evolve in two stages. The first stage will be it will be shipped as a completed component so that the memory company can continue to adhere to the business model of shipping a completed, tested, repaired device — a know good die.” That small stack will be placed on an apps processor for 3D, or on an interposer for 2.5D,” he said. The second part of it is what IP is needed for both the microprocessor and the memory to enable test. “We’ll start seeing test IP blocks from the foundries and the memory companies to enable test by using the processor to test the memory . I think we’re still exploring what that looks like. I can’t tell you what that’s going to end up looking like, but it’s clear that we’ve got to enable that together to enable the products,” McCann said.  

May 29, 2012 — Rudolph Technologies Inc. (NASDAQ: RTEC), back-end macro defect inspection tool supplier, will deliver 14 NSX Series 320 inspection systems to a large outsourced semiconductor assembly and test (OSAT) provider.

The inspection tools will be installed in Q2, at multiple steps in wafer-level chip-scale packaging (WLCSP) production.

The packaging house chose to order NSX 320 systems following a competitive evaluation, in which they noted its high speed and efficient, easy-to-use operating procedures.

This is a new product for Rudolph. The NSX320 System performs defect inspection and 2D bump metrology, and acquires on-the-fly defect images at production speeds. WLCSP lines require flexibility for handling substrates in various formats while collecting detailed defect and 2D metrology information during the inspection process, said Nathan Little, vice president and general manager of Rudolph

“The Dangerous Disappearing Defect” is the first article in a new series called Process Watch. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.

Finding and classifying defects on a wafer is a statistics game. The defect pareto—the bar graph showing the number of defects by type caught by the defect inspector and identified by the e-beam review system—drives the actions of the defect engineers in the fab. However, it’s not necessarily the tallest bar in the graph that tells the experienced defect engineer how to fix a defect problem. Far too often, the tallest bar is the insidious “SNV”—SEM Non-Visual. Some fabs bluntly label this category “Not Found.”

It might be more accurate to call the category “Not Found Again.” The defect inspection system did indeed find these defects and reported them in the KLARF, the output file that lists the locations of the defects detected on the wafer along with some descriptive information such as the size of the scattering signal associated with them. The “Not Found” problem arose when the wafer was moved to the e-beam review system to identify defect type. As the e-beam review system drove to the sites of the defects found by the inspection tool, sometimes it didn’t see a defect. This situation can arise for any of several reasons. First, the inspection system could have experienced a glitch, a result of electrostatic discharge or system noise, and therefore reported a false event. Second, misalignment between the coordinate system of the inspector and that of the e-beam review system could have resulted in the defect lying outside the field of view (FOV) of the e-beam review system. Third, the inspection system could have detected a defect at a previous layer that’s covered by a film transparent to the (optical) inspection system but not to the e-beam review system. Fourth, the defect could have arisen from nuisance variation, such as line-edge roughness, that shows up as a defect when the inspector uses a die-to-die detection algorithm, but is not evident in a review image, which is viewed alone. In any of these cases, the defect will be classified as “Not Found” or “SNV.”

SNV Type One: False events. As defined above, false events are a rare occurrence for today’s wafer inspection systems. Advances in signal processing algorithms, mechanical and electrical subsystems, and system integration have virtually eliminated false events. (False events are not to be confused with nuisance defects, which are defects arising from real, physical phenomena on the wafer—that defect engineers have designated as not affecting yield, performance or reliability. Examples of nuisance defects besides line-edge roughness might include particles that reside in open areas and bridges within dummy pattern. Nuisance defects can be culled from defects-of-interest (DOI) through multiple means, including choice of wavelength, aperture and polarization in the inspection recipe, and by various defect classification schemes post-detection. Nuisance defects like particles on open areas might be successfully re-detected by the e-beam review system, then binned or classified as nuisance, or they might be SNV, like line-edge roughness.)

SNV Type Two: Field-of-View Errors. For previous-generation inspection and review tools, insufficient coordinate accuracy often meant that the e-beam review tool had to search for each defect using a large field of view, then “zoom in” to image the defect with sufficient resolution to allow its classification. This strategy had two drawbacks: 1) it was very time-consuming, and thus limited the number of defects that could be reviewed on a wafer so that a statistically representative defect population was nearly impossible to attain; and 2) with a large FOV, the resolution of the image was too low to find the smallest critical defects. It didn’t matter that the ultimate resolution of the review tool was a couple of nanometers; if that resolution had to be compromised while the system was searching for defects, a significant number of defects would be missed. Defect engineers began to realize that, while resolution of the e-beam system is necessary for defect classification, the tool’s ultimate resolution is useful only if the defects of interest can be located reliably. 

Recent advances in stage accuracy on the wafer inspection and review tools, and improved communication between the tools, have now made it possible for e-beam review tools to drive directly to the location of the defect using a sub-micron field of view. The latest e-beam review tools can now reliably and efficiently locate the smallest yield-critical defects reported by the latest inspection systems and, without zooming in, image these defects for classification. This breakthrough has had a tremendous effect on the reduction of SNV counts, and the redistribution of these counts to appropriate defect classes (see Figure). Having a defect pareto that more accurately represents the defects on the wafer allows defect engineers to direct their efforts toward solving the most critical problems.

SNV Types 3 and 4: Previous-Layer Defects and Nuisance Variation. With the matter of false events out of the way, and having ensured that the review system is looking in the right place, we are left the problem of separating previous-layer defects—which truly should be SEM non-visual—from SNV nuisance, i.e. defects correctly imaged by the e-beam review tool but difficult to identify as defects from the review image. If the layer inspected is transparent to the wavelength band of the optical inspection tool, then the possibility that the defect is from the previous layer should be considered. In some cases the previous layer was also inspected, in which case defect source analysis (DSA) can be used to compare the locations of the previous layer’s results to those of the current layer. If the possibility of previous-layer defects has been ruled out, the expertise of the defect engineer is essential for determining the source of the “defect.” If it’s nuisance variation, it may be possible to hone the defect classification schemes to disposition nuisance variation defects into their own category in the defect pareto. Alternatively, the defect engineer may need to adjust the recipe of the inspection system to lower its capture rate for these SNV defects, through choice of a different aperture, wavelength band or polarization mode.

Why does it matter that the SNV defects are properly categorized? Defect engineers act on the information given by the defect pareto, and a high SNV count can disguise or hide real problems. For example, some of these mysterious, disappearing defects may be important DOI lying just outside the field of view of a previous-generation review tool. A misleading defect pareto can result in a delay in getting a new process to yield, or even a delay in getting a new chip to market. Using every means possible to ensure that the defect pareto properly represents the defects on the wafer—especially those defects that affect device yield, performance or reliability—gives fabs the best chance to bring their products to market profitably and on time.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Christina Wang is a senior product marketing manager in the e-beam technology division at KLA-Tencor.


Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

May 25, 2012 — THE BEST rankings from VLSIresearch identify the highest-rated suppliers of wafer processing, assembly, and test equipment. Chipmakers applauded their suppliers with increased ratings this year, according to a survey by VLSIresearch.

Wafer processing equipment supplier rankings are available here.

Suppliers of assembly equipment
Rank Company Rating
1 Hitachi High-Technologies 9.05
2 F&K Delvotec 8.51
3  Kulicke & Soffa 7.70
4 ASM International 7.61
Source: VLSIresearch 2012 Customer Satisfaction Survey.

Hitachi High-Technologies, a leading die bonder supplier, retained its #1 position for the second year in a row with an excellent rating of 9.05. This rating also earned Hitachi High-Tech the highest rating among all THE BEST Suppliers of 2012. The company topped all categories, earning its highest ratings among all assembly equipment suppliers in 14 of 15 categories. The company

The 10th Annual MEMS Technology Symposium sponsored by MEPTEC (MicroElectronics Packaging and Test Engineering Council) was held May 23 at the San Jose Holiday Inn. This year’s theme was “Sensors: A Foundation for Accelerated MEMS Market Growth to $1 Trillion.” Registered attendance was ~230.

The conference opened with a keynote address by Prof. Kristofer Pister, UC Berkeley speaking on sensory swarms. Inexpensive, wireless sensor networks have moved out of the lab and are being implemented in myriad applications. A refinery in Richmond, CA has methane gas sensors at every valve to monitor emissions. Parking spaces in San Francisco and Hollywood are tagged with car sensors to provide dynamic signage directing drivers to open spaces; this system also communicates with a smart phone app (“Parker”) to take you to specific open spaces. Rail cars have temperature and vibration sensors on every truck for predictive and preventive maintenance. Wireless sensors in the field are projected to top 1.1 billion units by 2015, up from 168 million units in 2010.

Janusz Bryzek, VP Fairchild Semiconductor, revisited his theme of accelerating the MEMS market to $1 Trillion and 1 trillion units. A $1 wireless sensor unit will require a 20¢ internet access module. The HP notion of a central nervous system for the earth will call for an average of ~1,000 sensors for every person. Smart phones have spurred the initial growth burst for MEMS, but the internet of things represents the “largest growth opportunity in the history of business.” Factors slowing MEMS market development include relatively slow MEMS process R&D cycles, and a lack of industry standards for manufacturing, packaging and testing. The fusion of computing, communication and sensing has been characterized as the third industrial revolution by Vijay Ullal of Maxim. While manufacturing jobs continue to be outsourced, the profitability and job creation potential at the innovation, design and marketing end remains a lucrative economic driver for the US.

Robert Haak of MANCEF described the implementation of the $1T MEMS roadmap. The key technologies needed for success include RF, chemical measurements, energy sourcing, inertial measurements, pressure measurements, acoustic sensors and displays. The industry roadmap infrastructure needs to evolve to a 3rd generation that focuses on products that are conceived at the interface of more than one technology. Specific roadmaps proposed are sensors, data transfer and data processing equipment. These are proposed to have a 15 year outlook with a 5 year review cycle.

Richard Friedrich of HP Labs spoke of the aforementioned central nervous system for the earth, CeNSE: awareness through a trillion MEMS sensors. The subtitle of his talk proclaimed this as the decade of sensing and sense-making. True more for technology than for politics. The infrastructure behind this enterprise will require about 1,000x more bandwidth than today’s internet has available. His vision projects ~150 sensors for every person on the planet, fewer than the second speaker but with a focus specifically on CeNSE applications. A MEMS nanofinger substrate for surface enhanced Raman scattering  (SERS) provides a signal enhancement factor of 1011, enabling a detection sensitivity of 0.02 parts per trillion. The use of people as sensors is manifest in real time analysis of Tweets for regional tuning of marketing campaigns. The HP Social Computing Lab claims 97% accuracy in predicting movie revenues based on the response to pre-release advertising. Work is underway to simulate the human brain visual cortex using a system with 64,512 cores that has demonstrated the ability to learn without being taught. The root objective of a CeNSE network is to convert the flood of data into insight that leads to action. Skynet?

Greg Galvin, CEO of Kionix, presented another perspective of sensing the future on the road to a $1T market. They focus solely on inertial sensors, which had a 2004-2011 unit CAGR of ~100%. Unit prices of accelerometers, compasses and pressure sensors are already well below $1, with gyroscopes to follow by 2015. MEMS components have been averaging 2% of the end cost of products that use them. His conclusion was that a $1T market for MEMS over the next 10 years is unlikely, even though a 1T unit market is probably, and a $1T market for MEMS-enabled devices is a given.

Jérémie Bouchaud of IHS iSuppli couched his perspective as a “MEMS revolution: from billions to trillions?” The 5 year MEMS CAGR is presently running at 9.7% for revenue overall and 20.7% for shipments. Smart phones by themselves have a 17.8% revenue CAGR, and are a significant market driver. MEMS microphones are another beneficiary of smart phones, which now include multiple microphones for both speaking and for background noise suppression. Despite the myriad growth opportunities, he believes the prospect of a $1T MEMS market will require price points ≤5¢ per unit, and an expansion of the market definition to include sensors for temperature, light, humidity, UV and others.

The afternoon keynote was delivered by Steve Nasiri, founder of InvenSense, a big player in the motion interface MEMS market. Just 3 applications, mobile handsets, media tablets and gaming represent a $2.4B market by 2015. The gyro market was slow to get started until Apple put one in the iPhone in 2010. Within a year, over 70 other models were on the market with gyros, even though some didn’t seem to know what to do with them. The wearable sensor market for remote patient monitoring, home monitoring, sports & fitness will push to $150M by 2015. Does your mother live too far away to tell you not to slouch? A shirt with an embedded posture sensor can handle that for her. InvenSense has just announced an open platform infrastructure to facilitate rapid MEMS applications development.

Jean-Christophe Eloy of Yole Développement provided a status of the MEMS industry with a focus on new drivers and the path to new opportunities. The overall MEMS market is ~$10B now, growing to ~$21B by 2017. While the MEMS markets continue to grow, they are still only ~10% of the value of the end markets they enable. Accelerometer / gyroscope systems with 6 degrees of freedom (DOF) have largely been displaced by newer systems with 9 or 10 DOF. All of the growth notwithstanding, he remains skeptical of a $1T MEMS device market.

Stephen Breit of Coventor took us to the software design side of the business with his comments on realizing the full potential of MEMS design automation. If invention is the first wave, and manufacturing differentiation is the second wave, then the third wave is going to be innovation in design and integration. This is the catalyst that will be needed and has the potential to drive the hyper growth if the industry is to hit the $1T mark. Simulation of the integrated MEMS system will make it possible to compress the development cycle from the 2009 benchmark of 4-5 years. This vision includes process design kits and MEMS design kits (modules) similar to the design efficiencies achieved in ASICs. Coventor has a partnership with IMEC that was facilitated by IMEC’s integrated SiGe CMOS + MEMS integration scheme.

Russell Shumway of Amkor took us to the end of the production line with a discussion of high volume assembly and test solutions to support a rapidly growing MEMS market. He anticipates that there will be a greater tendency toward package standardization over the next 10-20 years, but the variety of packaging options is so large that the diversity will still be formidable.

Tristan Joo, Co-Chair of Mobile SIG of the Wireless Communications Alliance reviewed a few case studies of fusing sensors into mobile operating systems. Current smart phones already contain 12-18 sensors, including inertial, optical, touch, audio, magnetic, geo-positional and environmental. The future has a context-aware sensory data cloud in store for us. Smart phone apps that take full advantage of these sensors amount to less than a 0.5% share of apps downloads across all iPhone, Android and Windows OS platforms. I myself can use my smart phone as a bubble level, an audio dB sound meter, a thermometer, a compass, a ruler, a document scanner and a mechanical energy harvester to recharge my battery. But I’m a geek.

The remaining scheduled time comprised six brief presentations by companies showcasing new applications under the banner of “MEMS for the Rest of Us.”

Hillcrest Labs provides motion control systems for consumer electronics and other markets. Their flagship platform is the Freespace® MotionEngine™ that includes a gesture recognition engine and a variety of mobile, gaming and TV applications.

Movea develops data fusion software for processing sensor data into usable information. It is a spin-off of CEA-Leti in France. Fundamental elements of human motion have been compiled into a periodic table, cleverly presented as the Chemistry of Motion.

Sensor Platforms provides data fusion software in their FreeMotion™ library with the objective of being hardware agnostic. He favors mobile devices that respond to human action and context, not in the sense of obeying gestures and commands, but more in the sense of recognizing what’s going on and acting accordingly. For example, when your smart phone calendar says you’re in a meeting, a really smart phone will silence most calls and allow vibration only for a select short list of callers. The end result is to use the available data and context to anticipate intent.

Syride makes a rugged sports-oriented GPS device for tracking speed, elevation and location for hobbies such as surfing, sailing, skiing, skydiving and hang gliding. I use “Map My Walk,” which I will henceforth think of as the couch potato analog of Syride.

VectorNav Technologies is a hardware and software company that takes consumer level motion systems and upgrades them to industrial strength using established aerospace technology. Applications include human exoskeletons for the handicapped, and human motion capture for movies and medical applications. I’m pretty sure I misunderstood when I heard something about a home Cruise missile.

Xsens specializes in sensor fusion software for smart phones, tablets and sports applications. On-body MEMS sensors enable a new paradigm for body motion capture, embodied in a 17 sensor system integrated in a Lycra body suit. The system has already been used in developing video games.

May 23, 2012 – GLOBE NEWSWIRE — Applied Nanotech Holdings Inc. (OTCBB:APNT) uncrated the THERCOBOND family of highly thermally conductive bonding and printed materials for power electronics and photonics packaging. The first 2 products are polymer-based (DTC-P) and ceramic-based (DTC-C).

THERCOBOND materials are designed for power electronic device packaging and dielectric coating, balancing thermal conductivity, thermal diffusivity, thermal expansion, dielectric and insulating properties, wettability, and printability. The thermal interface composites boast a

May 22, 2012 — Indium Corporation acquired a manufacturing facility in Rome, NY, to expand its production capacities of indium-, gallium-, germanium-, and tin-based materials, as well as other compounds.

Growing sales to solar photovoltaic, flat panel display (FPD), semiconductor and packaging, optical fiber, and light-emitting diode (LED) manufacturers necessitated the expansion.

The new facility enables Indium