Category Archives: Materials and Equipment

April 12, 2012 – PRNewswire — The Defense Advanced Research Projects Agency (DARPA) gave Raytheon Company (NYSE:RTN) an 18-month, $1.8 million contract to develop next-generation gallium nitride (GaN) devices on diamond substrates, named Thermally Enhanced Gallium Nitride (TEGaN). The diamond packaging boosts GaN power handling capability by at least 3x, Raytheon reports.

Advanced transistors and monolithic microwave integrated circuits (MMICs) can use TEGaN to reduce thermal resistance, multiplying GaN performance.

The diamond substrates could reduce the cost, size, weight and power of defense electronics. The contract allows Raytheon to develop and vet TEGaN for technology insertion into military systems. Raytheon uses GaN in major radar programs, and enables

April 12, 2012 — Adhesives maker DELO introduced DELOMONOPOX die attach adhesives, promising strong mechanical/environmental protection, low-temperature cure, and compatibility with various chip packaging substrates.

The DELOMONOPOX adhesive family for die attach adhere to all smart card substrates including silicon, epoxy and gold, as well as new substrates, such as PEI, PET and PEN. DELOMONOPOX adhesives cure in seconds at low temperatures.

When used for bonding and encapsulating chips in smart card modules, the adhesives mechanically safeguard the chips and the contacting area from pressure, bending and torsion. They also protect the die from physical influences and environmental conditions such as humidity, cold or heat.

DELO

April 11, 2012 — Intel Corporation (NASDAQ:INTC) announced its 2011 Intel Preferred Quality Supplier (PQS) awards, selecting 19 of its thousands of suppliers. Two suppliers received Intel’s Achievement Award for their extraordinary accomplishments in the areas of velocity, customer orientation and reduced cycle time supporting Intel’s semiconductor fab, packaging, and related activities. Intel announced 9 winners of the company’s Supplier Continuous Quality Improvement (SCQI) award for outstanding commitment to quality and performance excellence.

“2011 was a year that tested all aspects of the supply chain from core challenges of business continuity and affordability to the need for continuous innovation, velocity improvements and growing expectations of sustainability,” said Jaclyn A. Sturm, vice president, Technology and Manufacturing Group and general manager of Global Sourcing and Procurement. 

Also read: Intel, Samsung, TSMC semiconductor capex in 2012

Preferred Quality Suppliers: 

  • Advantest Corporation supplies testers, test handlers, and test interface products.
  • Applied Materials, Inc. supplies semiconductor manufacturing equipment, software and support services.
  • ASML supplies semiconductor lithography equipment.
  • Cabot Microelectronic Corporation supplies chemical mechanical polishing slurries.
  • Daewon Semiconductor Packaging Industrial Co., Ltd. supplies plastic injected molded trays.
  • DISCO Corporation supplies cutting, grinding, and polishing equipment and services.
  • DuPont AirProducts NanoMaterials L.L.C. supplies chemical mechanical planarization slurries.
  • Ebara Corporation supplies electroplaters, chemical mechanical polishers and pumps and abatement systems.
  • FUJIFILM Electronic Materials supplies formulated chemicals, developers, precursors, slurries and advanced photoresists.
  • KLA-Tencor Corporation supplies inspection and metrology capital equipment and services.
  • Marvell Semiconductor supplies application-specific integrated circuit semiconductor products and engineering resources.
  • Mitsubishi Gas Chemical Company, Inc. supplies chemicals for semiconductor device manufacturing.
  • Murata Manufacturing Co., Ltd. supplies multi-layer ceramic capacitors.
  • Rofin-Baasel supplies laser mark equipment.
  • Samsung Electro-Mechanics Co., Ltd. supplies flip chip substrates.
  • Siliconware Precision Industries Co., Ltd. supplies semiconductor assembly and test services.
  • STATS ChipPAC Ltd. supplies full turnkey packaging and test services.
  • TAIYO YUDEN CO., LTD. supplies ceramic capacitors, inductors, and filters.
  • Tosoh Quartz Inc. supplies quartzware for semiconductor wafer processing equipment.

Achievement winners:

  • Nikon Corporation awarded for velocity.
  • Powertech Technology Inc. awarded for customer orientation & cycle time reduction.

"This year’s Intel Preferred Quality Supplier award winners have truly distinguished themselves by driving and executing to world-class supply chain performance in execution, innovation and quality," said Sturm. "Intel’s 2011 have excelled across an extremely demanding set of expectations, and have distinguished themselves as industry leaders in technology innovation, supply chain excellence, and corporate responsibility," added Robert Bruck, corporate vice president and general manager of Technology Manufacturing Engineering. 

The PQS award is part of Intel’s Supplier Continuous Quality Improvement (SCQI) program that encourages suppliers to innovate and continually improve. To qualify for PQS status, suppliers must score at least 80% on a report card that assesses performance and ability to meet cost, quality, availability, delivery, technology and environmental, social and governance goals. Suppliers must also achieve 80% or greater on a challenging improvement plan and demonstrate solid quality and business systems. Additional information about the SCQI program is available at www.intel.com/go/quality.

Intel (NASDAQ:INTC) is a world leader in computing innovation. The company designs and builds the essential technologies that serve as the foundation for the world’s computing devices. Learn more at www.intel.com.

Check out Analog Devices Inc.’s (ADI) top suppliers of 2011 here.

Visit the Semiconductors Channel of Solid State Technology!

April 11, 2012 — Agilent Technologies Inc. (NYSE: A) launched Express Test for ultra-fast, high-precision nanomechanical testing on thin films, low-k materials, composites, and more. It allows 100 indents on 100 surface sites in 100 seconds.

Express Test is used on the Agilent Nano Indenter G200 for nanoscale mechanical testing. The option allows the Nano Indenter G200 to be operated in controlled-force or controlled-displacement mode, with point-and-shoot testing. The Nano Indenter G200 must be configured with an Agilent Dynamic Contact Module II indentation head, Agilent

April 10, 2012 — The 2012 Symposia on VLSI Technology and Circuits, June 12-14 (Technology) and 13-15 (Circuits), will take place in Honolulu, HI, with microelectronics manufacturing and circuit development research presentations. To foster joint interactions among device technologists and circuit/system designers, the technical programs of both symposia will overlap this year, and joint focus sessions on important topics will be held for the first time in the Symposia’s history.

More than 200 presentations will be given for approximately 1000 attendees. Short courses will occur prior to each symposium, with invited speakers addressing the industry’s most important issues. Evening rump sessions will spane a range of topics at the leading-edge of technology and circuit design. The VLSI Technology Symposium will be preceded by a satellite Silicon Nanoelectronics Workshop on June 10-11.

CMOS scaling and new 3D memory structures are highlights at this year’s Symposium on VLSI Technology, said Ming-Ren Lin, GLOBALFOUNDRIES, and General Chair.

The VLSI Circuits program will cover intelligent automotive vision systems, medical electronics, and diverse other applications, said Ajith Amerasekera, Texas Instruments, and General Chair, adding that more “universal topics” will also be covered, such as energy-efficient electronics and wireless communications interfaces.”

Short Courses

VLSI Technology Short Course (June 11), 14nm CMOS Technology & Design Co-Optimization and Memory.  This course will comprise 6 lectures given by distinguished speakers, covering state-of-the-art technology and circuit design for 14nm-generation CMOS.

VLSI Circuits Short Courses (June 12) — Two parallel full-day courses will be given by 12 distinguished international speakers from industry and academia.

– Designing in Advanced CMOS Technologies

– Ultra Low Power SoC Design for Future Mobile Systems

A single registration fee covers both, and participants can switch between the two. Afterward, a roundtable for both Circuits Courses will be held to foster interaction and discussion with all speakers.

New VLSI Symposia Technology/Circuits Joint Focus Sessions

The new Technology/Circuits Joint Focus Sessions are devoted to advanced device and circuit design co-optimization, a key ingredient for future progress.

– Memory (Wednesday morning, June 13)

– 3-D System Integration (Wednesday afternoon)

– Emerging Non-Volatile Memory (Wednesday afternoon)

– Advanced SRAM (Thursday morning, June 14)

– Design in Scaled Technologies (Thursday morning)

– Design Enablement in Scaled CMOS (Thursday afternoon)

– Embedded Memory (Thursday afternoon)

The Symposium on VLSI Technology will hold a special focus session Tuesday afternoon, June 12 on Low-Power and Steep Subthreshold Technology. The Symposium on VLSI Circuits will hold a special focus session Friday morning, June 15, Flash Memory.

Plenary Sessions

The Symposium on VLSI Technology will open with two invited plenary talks. First, Mike Mayberry of Intel will share his view through the “fog” of CMOS technology scaling, and identify directions for novel switching devices and new methods for computation.  Then, Prof. Ichiro Yamada of the University of Tokyo will describe how advances in information and communication technologies and micro-electro-mechanical devices (MEMS) can be leveraged to address the rapidly growing issues of the aging population and lifestyle-related diseases.

The Symposium on VLSI Circuits will open with two invited plenary talks by renowned experts. The Evolution of Next Generation Data Center Networks for High Capacity Computing will be given by Nicholas Ilyadis, Vice President & CTO of the Infrastructure and Networking Group at Broadcom. He will discuss the challenges of modern cloud computing and how they can be resolved by redefined network topologies and their underlying technologies and silicon solutions. The second plenary talk, Technology Innovations for Smart Cities, will be given by Akira Maeda, Chief Technology Officer, Infrastructure Systems Company, Hitachi, Ltd. He will discuss the technology innovations needed to realize “smart” cities, with emphasis on applications such as sensing, highly parallel processing, and mobile broadband communication for sophisticated social infrastructure systems. 

Evening Rump Sessions

The Symposium on VLSI Technology will hold two rump sessions in parallel on Tuesday evening, June 12 to foster open discussion of challenging R&D issues.

– Evolution of FinFET and Beyond? moderated by G. Yeap of Qualcomm and Y. Miyamoto of Tokyo Institute of Technology, will deal with the future of FinFET and other advanced transistor designs, such as ultra-thin body and ultra-thin BOX SOI, Ge and III-V transistors, tunnel FETs and other concepts.

– Patterning in Non-Planar World — EUV, DW or Tricky-193? moderated by G. Vandenberghe of IMEC and M. Tomoyasu of Tokyo Electron, will debate the future of patterning technologies.

The Symposium on VLSI Circuits also will hold two parallel rump sessions, on Thursday evening June 14.

– Is VLSI Innovation Dead? will feature seven experts (from IBM, Intel, AMD, NTT, and MIT, Shizuoka and Stanford Universities) discussing why companies in fields such as web software or server/OEMs are in the headlines, while semiconductor companies are noticeably absent. In short, the question for discussion is, is VLSI semiconductor innovation fine, dead, dying, or does it just need a kick-start?

– Will the Future Have More Analog or Digital Processing? Panelists from Analog Devices, Broadcom, Renesas Electronics, Xilinx, UC-Berkely and University of Tokyo will discuss whether the overall trend to digital circuit implementations is irreversible, or if the push toward digital circuits replacing analog counterparts is already finished. Digital circuits at new technology nodes don’t exhibit the same energy scaling as in the past, while analog-to-digital converter energy efficiency, for example, has improved more than 500-fold in the last decade.

A joint rump session will take place on Tuesday evening, Scaling Challenges Beyond 1xnm DRAM and NAND Flash Revolution?, moderated by R. Shrivastava of SanDisk and N. Lu of Etron. It will give the audience an opportunity to learn about future directions and issues for advanced memory technologies, including DRAM and NAND flash. The organizers of the VLSI Technology rump sessions (Thomas Skotnicki – STM and Katsura Miyashita – Toshiba) and of the VLSI Circuits rump sessions (Mark Bauer – Micron and Nicky Lu – Etron) invite all attendees of both VLSI Symposia to participate.

Luncheon

On Thursday, June 14, a luncheon sponsored by both Symposia will feature Nano-Satellites, CubeSats, and the Next Space Generation by Prof. James Cutler of the University of Michigan. He will discuss recent exciting trends in the space community, which are opening up access to space and sparking a wide variety of innovation globally. His talk will include stories of success and failure, and corresponding emerging challenges for the VLSI community will be highlighted.

Banquet

On Wednesday evening, June 13, a joint banquet will be held to provide an informal, relaxed atmosphere for information exchange between technologists and circuit designers.

The VLSI Technology Symposium began in 1981, while the VLSI Circuits Symposium was added in 1987. The two meetings have been held together ever since, rotating annually between Japan and Hawaii. The VLSI Technology Symposium is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, in cooperation with the IEEE Solid State Circuits Society. The VLSI Circuits Symposium is sponsored by the IEEE Solid-State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers and the IEEE Electron Devices Society. Visit www.vlsisymposium.org

Visit the Semiconductors Channel of Solid State Technology!

April 10, 2012 — Research organization CEA-Leti and passive component maker IPDiA developed an atomic layer deposition (ALD) process to apply medium-k dielectric layers on a metal-insulator-metal capacitor architecture, enabling 3D capacitors. The project took less than 2 years.

ALD enables conformal coating of high aspect ratio surfaces and exact thickness control at the atomic level. A capacitance density of 550nF/mm2 was obtained by keeping leakage current and parasitic levels as low as in the 250nF/mm2 PICS3 product.

The PICS high-density capacitors utilize vertical space to increase the capacitor surface, and therefore capacitance, without increasing the device footprint. Temperature, voltage, and aging tests revealed stability with this ALD-based process. The PICS capacitors show very low parasitic elements (ESR, ESL) and can outperform MLCCs, tantalum capacitors, or other discretes in a much smaller volume, the partners report.

Initial applications include high-reliability devices in medical, harsh environment, automotive, communication, industrial, and defense/aerospace markets. Examples include DC/DC converter and decoupling functions within limited space: IC decoupling, MEMS, sensors, memory sticks, smartcards, etc.

IPDiA unveiled its results at the Device Packaging 2012 conference in Scottdale, AZ, USA.

IPDiA and CEA-Leti will now work on stabilizing the ALD process and readying the product for market. The goal is 1

April 10, 2012 — Barclays Capital compiled its 2011 analysis of semiconductor wafer fab equipment (WFE) spending, with a look at the top players and underlying trends by process step. Here, Barclays’ CJ Muse looks at the growth areas for semiconductor test.

Overall semi test intensity (% of total WFE spending) fell in 2011, from ~7% to ~5.5.

Within the test market, system on chip (SoC) test continues to climb as a percentage of overall test, rising from ~43% share in 2007 to ~64% in 2011. Memory test has continued to shrink as a percentage of the overall market, though it stayed roughly flat year-over-year in 2011.

For information on Teradyne’s LitePoint acquisition and other top test players, read Wafer fab equipment leaders in 2011 and expectations for 2012

Next in the series: Lithography trends

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April 6, 2012 – BUSINESS WIRE — Materials supplier Rogers Corporation (NYSE: ROG) shared an update on its restructuring and streamlining initiatives, which are expected to save about $13 million (annualized savings) by Q4.

Rogers made improvements in supply chain and manufacturing operations efficiencies, focused on cost reduction across its businesses, and reduced headcount through a voluntary retirement program and the elimination of some positions.

As a result of the reorganization, product development, marketing and sales resources are now better aligned with its growth businesses: Printed Circuit Materials, High Performance Foams, and Power Electronics Solutions. Additional resources have been allocated to marketing and new business development activities to stimulate growth and expand revenue opportunities. Rogers will continue its active partnering and acquisition strategy for several of its core businesses.

Among the other improvement initiatives that concluded in the first quarter was the liquidation of the Company