Category Archives: Materials and Equipment

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced it has received an order from the University of Tokyo for its EVG810LT plasma activation system for compound semiconductor research. Installed at the university’s Takagi & Takenaka Laboratory, the EVG810LT augments the laboratory’s research focused on developing novel MOSFET and electronic-photonic integrated circuits (EPICs) using III-V-on-insulator (III-V-OI) and germanium-on-insulator (GeOI) substrates. These advanced material substrates are designed to exceed the performance of conventional silicon semiconductors as well as silicon photonics, where III-V materials such as indium phosphide (InP), indium gallium arsenide (InGaAs) and germanium are bonded to silicon wafers. The EVG810LT activates a wafer surface using plasma for low-temperature direct wafer bonding, and has been utilized by other customers in high-volume manufacturing of silicon-on-insulator (SOI) wafers and backside illuminated CMOS image sensors.

“The miniaturization of semiconductor devices is reaching its physical limitations, and shrinking transistor (scaling) in line with Moore’s Law is not sufficient enough to address future demands for higher performance of LSI devices,” noted Dr. Mitsuru Takenaka, associate professor at the Takagi & Takenaka Laboratory with the University of Tokyo. “3D integrated circuits with III-V compound semiconductors or germanium stacked freely on silicon semiconductors are expected to be among the breakthroughs to enhance the performance of the LSIs after the end of Moore’s Law. In support of our efforts, we adopted EV Group’s plasma activation system, the EVG810LT, to help us achieve lower temperature and high-quality wafer bonds.”

Commenting on today’s announcement, Hiroshi Yamamoto, representative director of
EV Group Japan K.K., said, “It is a great honor that our system was selected to support the University of Tokyo’s leading-edge LSI device research. The innovative results at The Takagi & Takenaka Laboratory are expected to address the fundamental issues that the semiconductor industry currently faces. Based on our company’s Triple-i philosophy of ‘invent, innovate and implement’, EV Group has been working with universities and R&D facilities that are active in advanced fields. We will continue to provide the Takagi & Takenaka Laboratory with the technical support they need to succeed with their leading-edge research.”

The emergence of the Internet of Things (IoT), Big Data and artificial intelligence (AI) is fueling a new wave of demand for electronic devices with lower power consumption, higher performance, and greater functionality. To meet this demand, the semiconductor industry is evaluating the benefits of incorporating new materials with silicon-beyond pure silicon-based wafers. This shift is paving the way for future market growth of compound semiconductors, as well as more efficient manufacturing technologies to achieve maximum end-device performance. For example, metal-organic chemical vapor deposition (MOCVD) processes, where a thin film of II-VI or III-V material is deposited on a substrate by heteroepitaxial growth, can result in inconsistent wafer formation. This compromises the integrity of the wafer surface and ultimately impacts end-device performance. Direct wafer bonding with plasma activation is a promising solution to enable heterogeneous integration of different materials and to realize high-quality engineered substrates.

EVG will showcase the EVG810LT system at the SEMICON Japan exhibition being held December 13-15 at the Tokyo Bit Sight – Tokyo International Exhibition Center in Tokyo, Japan.

Leti, a research institute of CEA Tech, today announced it has created the world’s first microfluidic circuit for cooling a particle detector, perhaps paving the way to a revolutionary, new detector technique at the Large Hadron Collider. This world-first event has been developed for CERN, the European nuclear research organization.

This breakthrough cooling system is part of CERN’s NA62 Gigatracker (GTK), a silicon pixel detector used to measure the arrival time and the position of incoming beam particles in the world’s largest particle accelerator. The NA62 detector is designed to study the “very rare” decay of kaons, subatomic particles made of quarks. Understanding these decays will help physicists check some of the predictions that the Standard Model of particle physics makes about short-distance interactions. Specifically, NA62 will measure the rate at which the charged kaon decays into a charged pion and a neutrino-antineutrino pair.

The Standard Model of particle physics explains how the basic building blocks of matter interact, governed by four fundamental forces in nature: gravity, electromagnetism and the strong and weak nuclear forces.

“The very rare decay of Kaons is sensitive to contributions coming from new particles and therefore represents a powerful way of searching for new physics,” said Augusto Ceccucci, NA62 spokesperson. “This technique complements the direct approach of the LHC detectors, and is a key component in CERN’s programs to probe the ultimate constituents of matter and understand the laws of nature.”

The NA62 is comprised of a set of three innovative silicon pixel detectors, whose job is to measure the arrival time and the position of the incoming beam particles. Installed in the heart of the NA62 detector, the silicon sensors are cooled down to approximately minus-20 degrees Celsius by a microfluidic silicon device developed by Leti and CERN researchers. The cooling system is required to remove the heat produced by the readout chips the silicon sensor is bonded to. The NA62 Gigatracker has a cooling plate on top of which both the silicon sensor and the readout chip are bonded.

In 2012, after CERN chose Leti to supply the microfluidic devices, CERN provided an initial fabrication process-flow that Leti’s Silicon Specialty Solutions (Leti-3S) program implemented in its own flow with its expertise in silicon processing, strictly following CERN’s technical specifications.

Leti-3S scientists demonstrated for the first time in the field of high-energy physics (HEP) the possibility of using silicon microfluidic devices for thermal management of silicon pixel detectors and their read-out electronics in LHC experiments.

Leti’s work included using deep silicon plasma-etching processes for microchannel production, its expertise at bonding silicon wafers at microscopic levels, and further grinding and thinning. In addition, Leti built titanium-nickel-gold contacts to connect the coolers to the NA62 device.

“The challenge was above all that we had only two pieces per wafers because of their large dimensions, meaning that two defects could result in a zero-percent yield,” said Catherine Charrier, project leader at Leti. “Maintaining the quality of the coolers on the centimeter dimensions, while respecting micrometric specifications, was a real challenge that we were able to overcome.”

Since being selected by CERN to work on NA62, Leti has contributed to the development of several types of cooling devices.

“Producing these silicon coolers provides us the opportunity to contribute to the scientific communities that use large instruments, which will expand Leti’s scope of operation,” Charrier said.

The hows and whys of resin bleed-out (RBO) are discussed, as well as the impact it makes and how to control it.

BY RONGWEI ZHANG, ABRAM CASTRO and YONG LIN, Semiconductor Packaging, Texas Instruments Inc., Dallas, TX

Die attach pastes, which consist of resin, curing agent, catalyst, filler and additives, have been extensively used to attach die onto lead frames in various electronic packages such as small outline integrated circuit (SOIC), thin-shrink small outline package (TSSOP), quad flat package (QFP) and quad-flat no-lead (QFN). One of the issues commonly encountered during package assembly is resin bleed-out (RBO), or epoxy bleed out (EBO). RBO is the separation of some formulation ingredients in the paste from the bulk paste (see FIGURE 1). Depending on die attach paste formulations and lead frame surface chemistry and morphology, bleeding ingredients can be solvents, reactive diluents, low-molecular-weight resins, catalysts, and additives like adhesion promoter. Resin bleed out tends to occur on high energy surfaces such as metal lead frames without any organic coating. In particular, if plasma cleaning is utilized to remove the contaminants prior to assembly, the bleeding issue may become more pronounced due to the increase in surface energy. Bleed-out can occur once die attach pastes are dispensed on to lead frames or during thermal curing. As microelectronics continue to move towards smaller form factor, higher reliability and higher performance, control of RBO becomes increasingly critical for packages where there is a very little clearance between die and die pad edge, or between one die and another in multi-chip modules (MCMs).

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How resin bleed-out occurs

When die attach paste is dispensed onto a solid surface like lead frame surface, the paste will typically wet the surface partially. The adhesive force between die attach paste and lead frame surface causes the paste to spread while the cohesive force within the bulk paste will hold the ingredients together and avoid contact with a lead frame surface. The adhesive and cohesive forces are the intermolecular forces such as hydrogen bonding and Van der Waals forces. So the degree of wetting will depend on the balance between adhesive force and cohesive force. Bleed-out occurs when the adhesive force of some formulation ingredients to the substrate is stronger than the cohesive force within the paste. The driving force for bleed out is to minimize the surface energy of the substrate by wetting.

Impact of resin bleed-out

Resin bleed-out can cause several issues if it is not well controlled.

• If the formulation ingredients bleed from the periphery of the die attach pastes and covers the wire bonding area, then issues like non-stick on pad (NSOP) and weak wire bond can occur. It can also be an issue if bleeding occurs from the die attach fillet along die edge to the die top, contaminating the bond pad on die top surface [1].

• Resin bleed-out may affect the adhesion of mold compound to die pad or mold compound to die top surface, both of which can lead to delamination. In particular, die top delamination is strictly not allowed in wire-bonded packages because it can cause the ball bond to be mechanically lifted, thereby leading to electrical failures during temperature cycling [2].

• As the formulation ingredients bleed out of the bulk paste, the composition of die attach paste under die may change accordingly. This can impact the adhesion of die attach to lead frame adversely, leading to an adhesive failure [3].

Influence of surface roughness

There are many factors that can cause resin bleed-out, such as low surface tension of die attach pastes, high surface energy of metal lead frames, surface contami- nation, surface porosity and surface roughness. Here we will focus on the impact of surface roughness, which is critical to achieve high package reliability. Two die attach pastes were dispensed onto three lead frames with different surface roughness. The surface roughness of these three lead frames was characterized by Atomic Force Microscopy (AFM) using the roughness average (Ra) and the roughness ratio (r) (FIGURE 2). The roughness average (Ra) represents the arithmetic average of the deviations from the center plane. The roughness ratio is the ratio between the actual 3-D surface area calculated by AFM and the flat surface. The 3D morphologies of lead frames are shown in FIGURE 3. It was found that (a) there is a good correlation between the roughness ratio and resin bleed-out. As the surface roughness ratio increases, the bleeding becomes increasingly worse; (b) LF1 and LF2 have almost same Ra, but the bleeding performance of DA3 and DA4 are different. This indicates that the roughness average is not a good index for RBO; (c) DA4 is more resistant to bleed out than DA3.

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The relationship between surface roughness and the wettability has been described by Young equation (Equ. 1) and Wenzel equation (Equ. 2).

cos0y=(YS-YSL)/YL (1)0
cosöm=rcos0y (2)

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Where Ys, YL, YSL are surface tensions of the solid, liquid and interfacial tension between die attach paste and lead frame, respectively; 0y is the Young contact angle, 0m is the measured contact angle, and r is the roughness ratio. As the surface roughness increases, the better the wetting, and the worse the bleed-out if the contact angle is < 90o [4]. This is the case for die attach paste on a metal surface without anti-EBO coating.

Approaches to control resin bleed out

There are several approaches to control or eliminate resin bleed-out. These approaches include modifying formulation by selecting appropriate anti-EBO, using die attach film (DAF)/B-stage epoxy, controlling surface roughness, creating mechanical barrier, and lowering the surface energy of lead frames by surface coating.

• Modifying formulations. Generally, anti-bleeding agents are added to die attach pastes to reduce or eliminate RBO. Different anti-bleeding agents may have different working mechanisms. Some anti- bleeding agents are added to enhance the cohesiveness of the pastes while others are added to form a thin layer with a surface energy lower than the pastes themselves on a lead frame surface [5]. Therefore, tailoring die attach adhesives with appropriate anti-bleeding agents is critical to prevent RBO on different types of lead frames, while maintaining high adhesion to metal lead frames to achieve high reliability.

• Die Attach Film/B-stage Epoxy. The simplest and most effective way to eliminate RBO is to use die attach films or B-stage materials. However, there are limitations associated with this approach. These can include high material cost and capital investment, difficulty to achieve high adhesion and thus high reliability, and limited thermal performance of these materials.

• Mechanical barriers. In some cases, grooves on lead frames are designed in between die attach area and wire bond area to reduce resin bleed-out, as shown in FIGURE 4. This is a simple and cost-effective process. However, this approach may not work well if the bleeding is severe. Similarly, some low surface energy insulating film around a chip can be printed to confine the un-cure pastes to the space defined by the printed pattern [5].

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• Vacuum baking. Vacuum baking of ceramic substrates with gold or other metal surfaces has been reported to reduce bleed-out. Several mechanisms were proposed: (a) through removal of polar surface contaminant, which promotes bleed-out of lighter organic resin by dipole attraction or chemical reaction [6]; (b) through reducing the surface energy of the plating surface by the formation of Ni2O3 [7]; (c) through producing a coating of hydrocarbon by oil back streaming toreduce the surface energy [8]. The method is not recommended either due to lack of controllability or due to the detrimental effect on wire bonding quality [7]. A more controlled method to reduce or eliminate RBO is to treat the surface with known chemicals and controlled processes, as discussed below.

• Low surface energy coating. Roughened lead frames have been utilized to enhance package reliability, particularly to meet Automotive Grade 0 requirements or beyond, as they increase surface contact area and enhance mechanical interlocking. As shown in Fig. 2, a small increase in roughness can result in a severe bleed-out. Therefore, increasing surface roughness will promote bleed-out if there is no anti-EBO on the surface. According to Young’s equation, decreasing surface energy will increase the contact angle, i.e. decreasing the wetting of the surface. Therefore, in roughened lead frame manufacturing, a solution of low surface energy material is used to treat roughened lead frames to lower their surface energy to reduce or eliminate RBO. Alternatively, a thin layer of film can be deposited onto the assembly surface by gas plasma technology to modify the surface energy [9]. FIGURE 5 shows water contact angles of lead frames with or without anti-EBO treatment. The anti-EBO coating will increase the contact angle on standard lead frame as explained by Young’s equation. Compared with standard lead frames, roughened lead frames have an increasing roughness and the anti-EBO coating on roughened lead frames further increases contact angle significantly. This can be explained by Wenzel equation, which demonstrates that adding surface roughness will increase surface hydrophobicity if the surface is chemically hydrophobic. In addition, Fig. 5 shows the resin bleed-out performances of a die attach paste (DA2) on these three types of lead frames. Bleed out was observed on the standard lead frame without anti-EBO, but there was no bleeding on both standard and roughened lead frame with anti-EBO coating. The low surface energy anti-EBO coating eliminates resin bleed out.

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Summary

This article provides an understanding of how bleeding occurs, the impact of bleeding, and methods to control bleeding. Bleeding is the result of the interaction between die attach pastes and metal lead frames. In particular, we studied the influence of surface roughness on RBO of different die attach materials, and found that there is a good correlation between the roughness ratio and bleed-out performance. Reducing the surface roughness will reduce or eliminate RBO. It is noteworthy that there is a line between reducing roughness to achieve no RBO and increasing roughness to ensure excellent delamination performance for lead frames without Anti-EBO. In terms of die attach pastes, the most effective way to control RBO seems to be the surface coating with anti-RBO without affecting other performances like delamination, or combining this method with others to provide an even better solution.

References

1. B. Neff, J. Huneke, M. Nguyen, P. Liu, T. Herrington, S. K. Gupta, “No bleed die attach adhesives”, IEEE International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005, pp. 1-3.
2. R. W. Zhang, Y. Lin, A. Castro, “Solving delamination in lead frame- based packages”, Chip scale review, 2015, pp. 44-48.
3. S. Kanagavel, D. Hart, “Optimization of die attach to surface-enhanced lead frames for MSL-1 performance of QFN packages”, Chip scale review, 2017, pp. 35-38.
4. J.-C. Hsiung, R.A. Pearson, T.B. Lloyd, “A surface energy approach for analyzing die attach adhesive resin bleed,” J. of Adhesion Science and Technology, 2003, 17, No. 1, pp. 1-13.
5. H. Schonhorn, L. H. Sharpe, “Liquids with reduced spreading tendency”, US Patent 4,483,898.
6. J. Ireland, “Epoxy bleedout in ceramic chip carriers”, Int. J Hybrid Microelectron., 1982, 5, pp. 1-4.
7. M. R. Marks, J. A. Thompson, R. Gopalakrishnan, “An experimental study of die attach polymer bleedout in ceramic packages”, Thin Solid Film, 1994, 252, pp. 54-60.
8. N. Tan, K. H. H. Lim, B. Chin, A. J. Bourdillon, “Engineering surface in ceramic pin grid array packaging to inhibit epoxy bleeding”, The Hewlett-Packard Journal, 1998, pp. 81-89.
9. M. Burmeister, “Elimination of epoxy resin bleed through thin film plasma deposition”, Proceeding of the 36th international IMAPS conference, Boston, MA, 2003, pp. 780-785.

A new illumination technology compares favorably to conventional bright field illumination.

BY GURVINDER SINGH, Director, Product Management, Rudolph Technologies, Inc., Wilmington, MA

A new optical technique can reveal defects and contaminants that escape conventional inspection technologies in many advanced packaging applications. As wafer level packaging (WLP), and especially fan-out wafer and panel level packaging (FOWLP/FOPLP), gains broader accep- tance, certain classes of defects that are characteristic of these processes present significant challenges to standard optical inspection tools. A new optical technology demonstrates increased sensitivity to transparent defects, such as residual dielectric films and photoresist, which are only marginally visible with conventional tools. At the same time, it is less sensitive to nuisance defects, such as those caused by the varying contrast and texture of grains in metal films, that should correctly be ignored.

Challenges in advanced packaging applications

Advanced packaging processes often involve the use of front-end-like technologies in back-end applications. Fan-out packaging is no exception, and, not surpris- ingly, it is following a similar development path, with increasing circuit complexity accompanied by shrinking circuit geometries. Redistribution layer (RDL) line widths, which were around 20μm in early implementations, will soon reach 2μm and are unlikely to stop there. Just as front-end processes placed increasing emphasis on enhanced process monitoring and control, advanced packaging processes will be forced to include more and better inspection and metrology capability at critical steps to maintain control and improve yields.

Advanced packaging processes, such as fan-out, face unique challenges that, for inspection systems, result in overcounting nuisance defects and undercounting yield-robbing critical defects. These advanced packaging techniques make extensive use of metal and organic polymers. Layers of metal are used to define conductive paths and organic polymer dielectric materials are used to provide insulation between conductors and planar surfaces between the layers. Dark field and bright field inspection results often include tens of thousands of nuisance defects. These occur because the inspection algorithms are designed to find random aberrations in highly repeatable patterns and the variable grain patterns of metal conductors appear as defects when are not. If not excluded, their large numbers can quickly overwhelm the real defects. Metal grain features can be as large as 50μm, much larger than RDL lines, which are currently as small as 2μm, and likely to reach 1μm in the near future.

Another class of defects that has proven difficult for conventional optical inspection techniques is caused by the presence of organic residues left after etching and descumming operations. They are hard to find because these materials tend to be transparent at visible wavelengths, yielding little signal in bright field and dark field inspection. They can be especially troublesome when they occur on contacts such as bumps and pillars. The new illumination method effectively eliminates nuisance noise from metal surface textures and enhances signal strength from organic defects.

ClearfindTM technology

The results presented here were all acquired using a FireflyTM inspection system (Rudolph Technologies) that incorpo- rates the new Clearfind (CF) illumination technology1. The new method takes advantage of the fact that many organic polymers exhibit distinctive optical properties that are not present in metals, silicon or other common inorganic materials used in semiconductor manufacturing. These properties tend to be unique to organic molecules displaying a high degree of conjugation, such as polycyclic aromatic hydrocarbons, and in linear or branched chain organic polymers with multiple regularly interspersed pi-bonds. This phenomenon results in the generation of a readily detectable, high color-contrast signal when the feature is appropriately illuminated against a metallic or other inorganic surface. The emission tends to be anisotropic and therefore less sensitive to surface topography that could potentially direct most ordinary bright field or dark field reflected light away from the detector. This results in increased sensitivity to organic residues and reduced sensitivity to interference from surrounding features. The method has the additional advantage of being relatively insensitive to signal variations caused by metal grains. FIGURE 1 presents a simplified illustration comparing the new technology to traditional white light inspection.

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The light source for the new technology is laser based, rather than the broadband source typically used in white light inspection systems. Thus, the light output is more stable in terms of both spectral range and output power. Autofocusing of the samples is accomplished using a patented high speed, near infrared-based laser triangulation system that maintains a constant distance between the imaging optics and the area being scanned. Images are acquired at high speed with a high-resolution camera. The result images compared in this article using bright field, dark field and CF technology were all acquired on the same inspection platform using different illumination techniques.

Through Silicon Via (TSV)

The sample is a 300mm silicon wafer with revealed TSV pillars2. TSV nail diameter is about 8μm and the distance between TSVs is about 56μm. The TSVs are on the backside of the wafer and the front side of the wafer is attached to a carrier.

In FIGURE 2a, the top shows a bright field image of two TSVs. The TSV on the left, circled in red, is covered with unetched organic residue and the TSV on the right, circled in green, is completely exposed. In the bright field image both TSVs look good and the residue is not visible. The images at the bottom left of figure 2 were acquired with CF technology and show the same TSVs. The TSV on the left, circled in red, has a bright blob while the one on the right, circled in green, is completely dark. The organic residue remaining on the left TSV now emits a readily detectable signal.

FIGURE 2b shows the inspection result from the full TSV wafer. The dots on the wafer map represent defect locations. There is a heavy concentration of organic residue on TSVs on the right side of the wafer. Metal pads approximately 35μm in diameter will be placed on top of the TSVs. Any organic residue between the TSV and the pad can cause deplanarization, which may result in connectivity issues when the die is stacked together. In addition, organic residue can increase the resistance of the contact when the die is stacked. If the defects are found before the next process step the wafer can be reworked.

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Under Bump Metal (UBM)

The sample is a 300mm wafer with RDL and under bump metallization (UBM). The UBM pads are about 50μm wide. In FIGURE 3a, the bright field image of two UBM pads shows the left pad is completely exposed and the right pad is covered with unetched organic film. However, the film is transparent and both pads look good in this image. Note the random metal texture visible in the bright field image, which adds noise and makes sensitive inspection for small defects more difficult. The image at lower left, acquired with CF technology, shows the same pads. The left pad, with no residue, appears black. The right pad, covered by residue, is significantly brighter. Also note that the metal texture seen in the bright field image with absent in CF illumination, permitting sensitive inspection for defects down to the pixel level.

FIGURE 3b shows a map of the full wafer where there is a heavy concentration of defects on UBM pads near the edge of the wafer. As in the TSV example, residue remaining on the UBM pads can cause increased resistance or loss of connectivity to a bump deposited on the pad. Bumps deposited on the residue are higher than normal bumps, leading to loss of coplanarity and connectivity issues. If the problem is found before starting the bump process, the wafer can be reworked and the residues removed.

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Redistribution Layer (RDL)

The sample is a 300mm molding compound wafer for fan-out packaging. FIGURE 4a shows a bright field image that includes a UBM pad and several RDL lines. The middle image shows the same area viewed with the new illumination technology. In the bright field image, the metal of the UBM pad and the RDL lines is very similar to the underlying metal visible through an interposed transparent film. The texture and graininess of the metals add noise to the image, increasing the difficulty of detecting small defects. Inspection with bright field illumination resulted in high nuisance defect counts without finding real process issues on the wafer. In FIGURE 4b, the top surface metal features, RDL and UBM, stand out against the background of the transparent film, while the underlying metal features are barely visible. FIGURE 4c shows a full wafer map acquired using CF technology and reveals a rectangular pattern that corresponds to the reticle of the lithography tool. The rectangular pattern was not visible in the bright field wafer map.

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FIGURE 5 shows additional RDL inspection results on the same wafer. CF technology revealed thinner lines toward the lower left corner of the reticle pattern. Ultimately, it was determined that these thinner lines were caused by a defect in the condenser lens of the lithography tool. The improved contrast between the first layer metal features in the underlying organic film, and the reduced noise, permitted more accurate and sensitive measurements using the new illumination technology. A bright field inspection of 20 wafers containing the same defect did not detect any thinner lines.

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Photoresist

The sample is a 300mm patterned silicon wafer from a large memory manufacturer3. It contains die approximately 11.7mm x 7.6mm in size, and containing arrays of about 9,000 metal pillars, each pillar approximately 22μm in diameter. The customer was interested to know if the new illumination technology would find defects not found by bright field inspection. FIGURE 6a shows a wafer map overlaying bright field defects (blue triangles) and CF defects (green triangles). In both cases the defects appear to be randomly distributed and not clustered. As depicted by the bar chart in FIGURE 6b, bright field illumination found 2,279 defects compared to 289 defects found by CF technology. Most interestingly, only 32 of the defects found by CF technology were also found with bright field inspection. 257 defects would have been missed by bright field inspection. The bar chart (FIGURE 6c) shows the size distribution of defects discovered by both techniques. Bright field inspection found a very large number of small defects (less than 5μm) and more defects larger than 25μm. Defects found by the CF technology were between 5-25μm in size.

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FIGURE 7 compares CF technology results (top) and bright field results (bottom). Each vertical pair shows a defect missed by bright field inspection and detected by CF technology. The enhanced brightness and circular shape of the defects detected by the new method strongly imply that they are associated with polymer residues. The enhanced brightness of the defects against the very black background is a unique and valuable feature of CF technology. Overall, these results demonstrate the value of supplementing bright field inspection with CF technology. All of the defects found by CF technology were of sufficient size to impact yield.

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Conclusion

Results shown here demonstrate the benefits of imaging with the new CF illumination technology when compared to conventional bright field illumination. The new technology allows detection of transparent organic residues that are not visible with bright field illumination.

It was also shown to detect types and sizes of defects that were not detected by bright field inspection. Equally important, its ability to reduce noise caused by metal texture and graininess significantly improves its sensitivity to small defects on metal features and dramatically reduces the detection of nuisance defects.

References

1. Gurvinder Singh, et al, “Advanced packaging lithography and inspection solution for next generation FOWLP-FOPLP processing”, IEEE Xplore, October 2016.
2. Woo Young Han, et al, “Inspection challenges in wafer level packaging”, International Wafer Level Packaging Conference, October 2017
3. Jonathan Cohen, et al, “Photoresist residue detection in advanced packaging”, International Wafer Level Packaging Conference, October 2017

The semiconductor industry continued its upward trend in the third quarter of 2017, notching 12 percent sequential growth with strength across all application markets, according to IHS Markit (Nasdaq: INFO). Global revenue totaled $113.9 billion, up from $101.7 billion in the second quarter of 2017.

As memory prices remain high and the wireless market continues to see strong demand through the fourth quarter, 2017 is shaping up to be a record-breaking year for the semiconductor industry. IHS Markit projects that semiconductor revenue will reach a record-high $428.9 billion in 2017, representing a year-over-year growth rate of 21 percent.

Key growth drivers

All application end markets posted sequential growth over the prior quarter, with wireless communications and data processing categories leading the pack.

Revenue from wireless applications grew faster sequentially in the third quarter of 2017 than any of the other high-level application markets. Semiconductor revenue from wireless applications was a record high $34.8 billion in the third quarter, representing nearly 31 percent of the total semiconductor market. IHS Markit anticipates an even bigger fourth quarter for wireless applications, projecting $37.5 billion in revenue — and more than $131 billion for the full-year 2017.

As the wireless market evolves, this growth can be attributed to a number of factors. ”More complex and comprehensive smartphone systems on a chip are supporting applications such as augmented reality and computational photography,” said Brad Shaffer, senior analyst for wireless semiconductors and applications at IHS Markit. “Premium smartphones have increasing amounts of memory and storage. The radio frequency content in these smartphones has also grown considerably over the past few product generations, with many high-end smartphones now supporting gigabit LTE mobile broadband speeds.”

The memory markets proved once again to be the driving force and highest-growing segment for semiconductors in the third quarter of 2017. “The DRAM industry had another record quarter with $19.8 billion in revenue, exceeding the prior record by more than $3 billion,” said Mike Howard, director for DRAM memory and storage research at IHS Markit. “Prices and shipments were up during the quarter as strong demand for mobile and server DRAM continued to propel the market.”

Top_5_memory

The NAND industry had another record quarter as well, growing 12.9 percent in the third quarter of 2017, with total revenue reaching $14.2 billion. “Pricing was flat in the quarter, as seasonally strong demand driven by the mobile and solid-state drive segments was able to offset moderate shipment growth,” said Walter Coon, director for NAND flash technology research at IHS Markit. “The market is expected to soften exiting 2017 and into early next year, as the industry transition to 3D NAND technology continues to progress and the market enters a traditionally slower demand period.”

Manufacturer moves

Samsung officially passed Intel to become the number-one semiconductor supplier in the world in the third quarter of 2017, growing 14.9 percent sequentially. Intel now comes in at number two, with SK Hynix securing the third rank in terms of semiconductor revenue for the third quarter.

top_5_semiconductor

Among the top 20 semiconductor suppliers, Apple and Advanced Micro Devices (AMD) achieved the highest revenue growth quarter over quarter by 46.6 percent and 34.3 percent, respectively.

There was a good deal of market share movement within the top 10 suppliers throughout the third quarter as well. In terms of semiconductor revenue, Qualcomm surpassed Broadcom Limited to secure the number-five spot, while nVidia made its way into the top 10 ranking for the first time ever. At this time last year, the top five semiconductor companies controlled 40 percent market share of the entire industry. The top five gained 4.2 percent more market share this year over last year, while comprising three memory companies instead of the previous two.

More information on this topic can be found in the latest release of the Semiconductor Competitive Landscaping Tool (CLT) from the IHS Markit Semiconductor Competitive Landscape CLT Intelligence Service.

Semiconductor test equipment supplier Advantest Corporation (TSE:6857) has developed the M4171 handler to meet the mobile electronics market’s needs for cost-efficient thermal control testing of ICs with high power dissipation during device characterization and pre-production bring up.  This portable, single-site handler automates device loading and unloading, thermal conditioning and binning in engineering labs, where most testing today involves manual device handling. It also features an active thermal control (ATC) capability typically available only on larger footprint, more costly production-volume handlers.

The M4171 can be used to remotely conduct device handling and thermal control from anywhere around the world through a network connection.  In addition to requiring fewer operators and lowering labor costs, this handler maximizes system utilization among working groups in different locations.

The combination of automated device handling, wide-temperature ATC capabilities from -45° C to 125° C and remote operation make the M4171 unique.  It can run multi-mode test processes (Single Insertion Multiple Temperature), automated testing, automatic ID testing, output tray re-testing and manual testing, both pre-defined and user defined.

The Tri Temp Technology on the M4171 enables the users to operate over a broad range of temperatures which greatly increases any lab’s efficiency.  The system uses direct device-surface contact, which enables quick temperature switching for fast ramp up and ramp down and improves cycle temperature testing by over 40 percent compared to manual thermal-control solutions.

The M4171 handler is compatible with the V93000 and T2000 platforms as well as other testers.  Other features include a 2D code reader, a device rotator and a high contact force option.  Operation is simple with an intuitive, easy-to-use GUI that includes pre-defined functions.

“By bringing cost-efficient automated testing into the lab and enabling our customers to get higher utilization from their installed base, we are providing substantial productivity advantages,” said Toshio Goto, executive officer and manager of the Device Handling business unit at Advantest.  “As our first single-site ATC handler, the M4171 is opening new market opportunities for us in device characterization within labs and benchtop environments.”

 

DARPA’s new initiative


November 8, 2017

BY DR. PHIL GARROU, Contributing Editor

Earlier this year, DARPA’s Microsystems Technology Office (MTO) announced a new Electronics Resurgence Initiative (ERI) “to open pathways for far-reaching improvements in electronics performance well beyond the limits of traditional scaling.” Key to the ERI will hopefully be new collab- orations among the commercial electronics community, defense industrial base, university researchers, and the DoD. The DoD proposed FY 2018 budget reportedly includes a $75 million allocation for DARPA in support of this, initiative. It is reported that in total we are looking at a $200,000MM program.

The program will focus on the development of new materials for devices, new architectures for integrating those devices into circuits, and software and hardware designs for using these circuits. The program seeks to achieve continued improvements in electronics performance without the benefit of traditional scaling. Bill Chappell, director of DARPA’s Microsystems Technology Office (MTO), which will lead the program, announced

“For nearly seventy years, the United States has enjoyed the economic and security advantages that have come from national leadership in electronics innovation…..If we want to remain out front, we need to foment an electronics revolution that does not depend on traditional methods of achieving progress. That’s the point of this new initiative – to embrace progress through circuit specialization and to wrangle the complexity of the next phase of advances, which will have broad implications on both commercial and national defense interests.” He continued: “We need to break away from tradition and embrace the kinds of innovations that the new initiative is all about…”

The chip research effort will complement the recently created Joint University Microelectronics Program (JUMP), an electronics research effort co-funded by DARPA and SRC (Semiconductor Research Corporation). Among the chip makers contributing to JUMP are IBM, Intel Corp., Micron Technology and Taiwan Semiconductor Manufacturing Co. SRC members and DARPA are expected to kick in more than $150 million for the five-year project. Focus areas include high-frequency sensor networks, distributed and cognitive computing along with intelligent memory and storage.

The materials portion of the ERI initiative will explore the use of unconventional materials to increase circuit performance without requiring smaller transistors. Although silicon is used for most of the circuits manufactured today, other materials like GaAs, GaN and SiC have made significant inroads into high performance circuits. It is hoped that the initiative will uncover other elements from the Periodic Table that can provide candidate materials for next-generation logic and memory components. One research focus will be to integrate different semiconductor materials on individual chips, and vertical (3D) rather than planar integration of microsystem components.

The architecture portion of the initiative will examine circuit structures such as Graphics processing units (GPUs), which underlie much of the ongoing progress in machine learning, have already demonstrated the performance improvement derived from specialized hardware architectures. The initiative will explore other opportunities, such as “reconfigurable physical structures that adjust to the needs of the software they support.”

The design portion of the initiative will focus on devel- oping tools for rapidly designing specialized circuits. Although DARPA has consistently invested in these appli- cation-specific integrated circuits (ASICs) for military use, ASICs can be costly and time-consuming to develop. New design tools and an open-source design paradigm could be transformative, enabling innovators to rapidly and cheaply create specialized circuits for a range of commercial applications.

As part of this overall Electronics Resurgence Initiative, DARPA had their kickoff meeting for the CHIPS program (Common Heterogeneous Integration and Intellectual Property (IP) Reuse). The CHIPS vision is an ecosystem of discrete modular, IP blocks, which can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of such IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. The CHIPS program hopes to develop the design tools and integration standards required for modular integrated circuit (IC) designs.

Program contractors include Intel, Micron, Cadence, Lockheed Martin, Northrop Grumman, Boeing, Synopsys, Intrinsix Corp., and Jariet Technologies, U. Michigan, Georgia Tech, and North Carolina State.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $107.9 billion for the third quarter of 2017, marking the industry’s highest-ever quarterly sales and an increase of 10.2 percent compared to the previous quarter. Sales for the month of September 2017 were $36.0 billion, an increase of 22.2 percent over the September 2016 total of $29.4 billion and 2.8 percent more than the previous month’s total of $35.0 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

highest ever sales

“Global semiconductor sales increased sharply year-to-year in September, and year-to-date sales through September are more than 20 percent higher than at the same point last year,” said John Neuffer, SIA president and CEO. “The industry posted its highest-ever quarterly sales in Q3, and the global market is poised to reach its highest-ever annual revenue in 2017.”

Regionally, year-to-year and month-to-month sales increased in September across all markets: the Americas (40.7 percent year-to-year/5.9 percent month-to-month), China (19.9 percent/2.5 percent), Europe (19.0 percent/1.8 percent), Asia Pacific/All Other (16.8 percent/1.9 percent), and Japan (11.9 percent/0.5 percent).

“The Americas market continued to stand out, notching its largest year-to-year sales increase in more than seven years,” Neuffer said. “Standouts among semiconductor product categories included memory products like DRAM and NAND flash, both of which posted major year-to-year growth in September, as well as Logic products, which enjoyed double-digit growth year-to-year.”

Piezoelectric materials are used for applications ranging from the spark igniter in barbeque grills to the transducers needed by medical ultrasound imaging. Thin-film piezoelectrics, with dimensions on the scale of micrometers or smaller, offer potential for new applications where smaller dimensions or a lower voltage operation are required.

Researchers at Pennsylvania State University have demonstrated a new technique for making piezoelectric microelectromechanical systems (MEMS) by connecting a sample of lead zirconate titanate (PZT) piezoelectric thin films to flexible polymer substrates. Doctoral candidate Tianning Liu and her co-authors report their results this week in the Journal of Applied Physics, from AIP Publishing.

Electroded thin-film PZT on a flexible polyimide substrate of relatively large area. Credit: Tianning Liu

Electroded thin-film PZT on a flexible polyimide substrate of relatively large area. Credit: Tianning Liu

“There’s a rich history of work on piezoelectric thin films, but films on rigid substrates have limitations that come from the substrate,” said Thomas N. Jackson, a professor at Penn State and one of the paper’s authors. “This work opens up new areas for thin-film piezoelectrics that reduce the dependence on the substrate.”

The researchers grew polycrystalline PZT thin films on a silicon substrate with a zinc oxide release layer, to which they added a thin layer of polyimide. They then used acetic acid to etch away the zinc oxide, releasing the 1-micrometer thick PZT film with the polyimide layer from the silicon substrate. The PZT film on polyimide is flexible while possessing enhanced material properties compared to the films grown on rigid substrates.

Piezoelectric devices rely on the ability of some substances like PZT to generate electric charges when physically deformed, or inversely to deform when an electric field is applied to them. Growing high-quality PZT films, however, typically requires temperatures in excess of 650 degrees Celsius, almost 300 degrees hotter than what polyimide is able to withstand without degrading.

Most current piezoelectric device applications use bulk materials, which hampers miniaturization, precludes significant flexibility, and necessitates high-voltage operation.

“For example, if you’re looking at putting an ultrasound transducer in a catheter, a PZT film on a polymer substrate would allow you to wrap the transducer around the circumference of the catheter,” Liu said. “This could allow for significant miniaturization, and should provide more information for the clinician.”

The performance of many piezoelectric thin films has been limited by substrate clamping, a phenomenon in which the rigid substrate constrains the movement of the piezoelectric material’s domain walls and degrades its properties. Some work has been done crystallizing PZT at temperatures that are compatible with polymeric materials, for example using laser crystallization, but results thus far have led to porous thin films and inferior material properties.

The released thin films on polyimide that the researchers developed had a 45 percent increase in remanent polarization over silicon substrate controls, indicating a substantial mitigation in substrate clamping and improved performance. Even then, Liu said, much work remains before thin-film MEMS devices can compete with bulk piezoelectric systems.

“There’s still a big gap between putting PZT on thin film and bulk,” she said. “It’s not as big as between bulk and substrate, but there are also things like more defects that contribute to the lower response of the thin-film materials.”

Fibers made of carbon nanotubes configured as wireless antennas can be as good as copper antennas but 20 times lighter, according to Rice University researchers. The antennas may offer practical advantages for aerospace applications and wearable electronics where weight and flexibility are factors.

The research appears in Applied Physics Letters.

The discovery offers more potential applications for the strong, lightweight nanotube fibers developed by the Rice lab of chemist and chemical engineer Matteo Pasquali. The lab introduced the first practical method for making high-conductivity carbon nanotube fibers in 2013 and has since tested them for use as brain implants and in heart surgeries, among other applications.

The research could help engineers who seek to streamline materials for airplanes and spacecraft where weight equals cost. Increased interest in wearables like wrist-worn health monitors and clothing with embedded electronics could benefit from strong, flexible and conductive fiber antennas that send and receive signals, Pasquali said.

The Rice team and colleagues at the National Institute of Standards and Technology (NIST) developed a metric they called “specific radiation efficiency” to judge how well nanotube fibers radiated signals at the common wireless communication frequencies of 1 and 2.4 gigahertz and compared their results with standard copper antennas. They made thread comprising from eight to 128 fibers that are about as thin as a human hair and cut to the same length to test on a custom rig that made straightforward comparisons with copper practical.

“Antennas typically have a specific shape, and you have to design them very carefully,” said Rice graduate student Amram Bengio, the paper’s lead author. “Once they’re in that shape, you want them to stay that way. So one of the first experimental challenges was getting our flexible material to stay put.”

Contrary to earlier results by other labs (which used different carbon nanotube fiber sources), the Rice researchers found the fiber antennas matched copper for radiation efficiency at the same frequencies and diameters. Their results support theories that predicted the performance of nanotube antennas would scale with the density and conductivity of the fiber.

“Not only did we find that we got the same performance as copper for the same diameter and cross-sectional area, but once we took the weight into account, we found we’re basically doing this for 1/20th the weight of copper wire,” Bengio said.

“Applications for this material are a big selling point, but from a scientific perspective, at these frequencies carbon nanotube macro-materials behave like a typical conductor,” he said. Even fibers considered “moderately conductive” showed superior performance, he said. Although manufacturers could simply use thinner copper wires instead of the 30-gauge wires they currently use, those wires would be very fragile and difficult to handle, Pasquali said.

“Amram showed that if you do three things right — make the right fibers, fabricate the antenna correctly and design the antenna according to telecommunication protocols — then you get antennas that work fine,” he said. “As you go to very thin antennas at high frequencies, you get less of a disadvantage compared with copper because copper becomes difficult to handle at thin gauges, whereas nanotubes, with their textile-like behavior, hold up pretty well.”