Category Archives: Materials and Equipment

The annual revenue from the global IC testing and packaging industry for 2017 is estimated to grow by 2.2% to reach US$51.73 billion, according to the latest research from TrendForce. Furthermore, providers of outsourced semiconductor assembly and test (OSAT) are projected to represent a share of 52.5% in the year’s total revenue.

The IC testing and packaging industry is expected to register recovery and growth in 2017 in contrast to the 2016 revenue result that showed a slight annual decline. This year, the main revenue driver has been the increase in the amount of IC components demanded for mobile devices. The strong demand for IC components has also expanded the deployment of advanced packaging solutions that offer higher levels of integration and higher numbers of I/O connections. In sum, the rising quantity and quality of demand during this year has benefited the IC testing and packaging industry revenue-wise.

The projected revenue ranking of the top 10 OSAT providers for 2017 is overall similar to the 2016 ranking. This year’s top three in sequence are ASE, Amkor and JCET. Among the top 10, PTI has gained enormously from the memory boom caused by the combination of tight market supply, application growth for high-performance computing and strong demand for high-density storage products. PTI also has the advantage of having a strong relationship with the memory giant Micron. TrendForce estimates that PTI’s annual revenue growth for this year will reach an impressive 26.3%, putting the company in the fifth place of the ranking.

osats

China’s IC backend service providers are focusing on developing their technologies as their progress in overseas mergers and acquisitions slows

TrendForce’s survey of the testing and packaging industry in 2017 also finds that there are now much fewer M&A targets for Chinese companies because of the increasing level of competition and consolidation activities in the global semiconductor sector. Furthermore, the barriers against Chinese companies for making overseas acquisitions using domestic capital have also been raised. Thus, Chinese IC backend service providers are shifting their focus away from trying to get technologies and market shares via overseas M&As. Instead, they are investing their resources in developing technologies related to fan-out processing and system-in-package (SiP) integration. They eventually want to get their solutions verified by potential clients, proving that they have the in-house expertise to be competitive in the market.

Chinese testing and packaging companies continue to gain processing capacity for packaging technologies that are high-end (e.g. flip chip and bumping) and more advanced (e.g. fan-in, fan-out, 2.5D interposer and SiP). Because of the progress in both technology development and M&As, Chinese service providers such as JCET, TSHT and TFME are projected to rise above the industry’s average in their revenue performances this year with double-digit growth rates.

Additionally, China’s IC testing and packaging industry will be supported by the growing number of domestic fabs in the coming year. TrendForce forecasts that China’s monthly 12-inch wafer capacity will increase by about 162,000 pieces before the end of 2018. This 180% increase from the current capacity level will give a sizable injection of demand into the domestic testing and packaging market.

 

The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel, may go down as one of the most memorable editions for the sheer variety and depth of its talks, sessions, courses and events.

Among the most-anticipated talks are presentations by Intel and Globalfoundries, which will each detail their forthcoming competing FinFET transistor technology platforms in a session on Wednesday morning. FinFET transistors are a major driver of the continuing progress of the electronics industry, and these platforms are as important for their commercial potential as they are for their technical innovations.*

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations, along with other events.

“Those who attend IEDM 2017 will find much that is familiar, beginning with a technical program describing breakthroughs in areas ranging from mainstream CMOS technology to innovative nanoelectronics to medical devices. The Sunday Short Courses are also a perennial favorite because they are not only comprehensive but are also taught by accomplished world experts,” said Dr. Barbara De Salvo, Scientific Director at Leti. “But we have added some new features this year. One is a fourth Plenary session, on Wednesday morning, featuring Nobel winner Hiroshi Amano. Another is a revamped Tuesday evening panel. Not only will it focus on a topic of great interest to many people, it is designed to be more open and less formal.”

Other features of the IEDM 2017 include:

  • Focus Sessions on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current Status and Perspectives.
  • A vendor exhibition will be held, based on the success of last year’s event at the IEDM.
  • The IEEE Magnetics Society will again host a joint poster session on MRAM (magnetic RAM) in the exhibit area. New for this year, though, is that the Society will also hold its annual MRAM Global Innovation Forum on Thursday, Dec. 7 at the same hotel, enabling IEDM attendees to participate. (Refer to the IEEE Magnetics Society website.) The forum consists of invited talks by leading experts and a panel discussion.

Here are details of some of the events that will take place at this year’s IEDM:

90-Minute Tutorials – Saturday, Dec. 2
These tutorials on emerging technologies will be presented by leading technical experts in each area, with the goal of bridging the gap between textbook-level knowledge and cutting-edge current research.

  • The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Venkatesh Sundaram, Associate Director, Georgia Tech 3D Systems Packaging Research Center
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, Imec

Short Courses – Sunday, Dec. 3
The day-long Short Courses provide the opportunity to learn about important developments in key areas, and they enable attendees to network with the industry’s leading technologists.

Boosting Performance, Ensuring Reliability, Managing Variability in Sub-5nm CMOS, organized by Sandy Liao of Intel, will feature the following sections:

  • Transistor Performance Elements for 5nm Node and Beyond, Gen Tsutsui, IBM
  • Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture, Steve CH Hung, Applied Materials
  • Sub-5nm Interconnect Trends and Opportunities, Zsolt Tokei, Imec
  • Transistor Reliability: Physics, Current Status, and Future Considerations, Stephen M. Ramey, Intel
  • Back End Reliability Scaling Challenges, Variation Management, and Performance Boosters for sub-5nm CMOS,Cathyrn Christiansen, Globalfoundries
  • Design-Technology Co-Optimization for Beyond 5nm Node, Andy Wei, TechInsights

Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang of TSMC, will feature the following sections:

  • Embedded Non Volatile Memory for Automotive Applications, Alfonso Maurelli, STMicroelectronics
  • 3D ReRAM: Crosspoint Memory Technologies, Nirmal Ramaswamy, Micron
  • Ferroelectric Memory in CMOS Processes, Thomas Mikolajick, Namlab
  • Embedded Memories Technology Scaling & STT-MRAM for IoT & Automotive, Danny P. Shum, Globalfoundries
  • Embedded Memories for Energy-Efficient Computing, Jonathan Chang, TSMC
  • Abundant-Data Computing: The N3XT 1,000X, Subhasish Mitra, Stanford University

Plenary Presentations – Monday, Dec. 4

  • Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
  • Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL
  • System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC

Plenary Presentation – Wednesday, Dec. 6

  • Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University. Dr. Amano received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting. His talk will be preceded by the Focus Session on silicon photonics.

Evening Panel Session – Tuesday evening, Dec. 5

  • Where will the Next Intel be Headquartered?  Moderator: Prof. Philip Wong, Stanford

Entrepreneurs Lunch
Jointly sponsored by IEDM and IEEE EDS Women in Engineering, this year’s Entrepreneurs Lunch will feature Courtney Gras, Executive Director for Launch League, a local nonprofit focused on developing a strong startup ecosystem in Ohio. The moderator will be Prof. Leda Lunardi from North Carolina State University. Gras is an engineer by training and an entrepreneur by nature. After leaving her job as a NASA power systems engineer to work for on own startup company, she discovered a passion for building startup communities and helping technology-focused companies meet their goals. Named to the Forbes ’30 Under 30′ list in 2016, among many other recognitions and awards, Gras enjoys sharing her stories of founding a cleantech company with young entrepreneurs. She speaks on entrepreneurship, women in technology and clean energy at venues such as TEDx Budapest, the Pioneers Festival, and the IEEE WIE International Women’s Leadership Conference.

 

Toshiba Corporation (TOKYO:6502) today announced that its board of directors has approved a further investment by Toshiba Memory Corporation (TMC), a wholly-owned subsidiary that manufactures Flash memory, in manufacturing equipment for the Fab 6 clean room under construction at Yokkaichi Operations. TMC will invest approximately 110 billion yen as a second investment in Fab 6 for the installation of additional manufacturing equipment in the Phase-1 clean room.

Production at Fab 6 will be entirely devoted to BiCS FLASH, Toshiba’s innovative 3D Flash memory. As Toshiba announced in its August 3, 2017 release “Update on Toshiba Memory Corporation’s Investment in Production Equipment for Fab 6 at Yokkaichi Operations”, TMC has previously invested approximately 195 billion yen in Fab 6 as its first investment covering the installation of manufacturing equipment in the Phase-1 clean room and the construction of the Phase-2 clean room.

Demand for TMC’s next generation 3D Flash memory devices is expected to increase significantly due to growing demand for enterprise SSDs in datacenters, SSDs for PCs, and memory for smartphones; TMC expects this strong market growth to continue in 2018. TMC’s investment timing will position it to capture this growth and expand its business.

The investment in Fab 6 will enable TMC to install manufacturing equipment for 96-layer 3D Flash memories, including deposition and etching equipment.

There is no change in the FY2017 Financial Forecast announced on Aug 10, 2017, as the impact of the additional investment will be realized after FY2018. However, the FY2017 investment plan for Toshiba Corporation Storage & Devices Solutions Segment will be revised from 330 billion yen, as announced on August 10, to 400 billion yen by accelerating a part of the investment previously planned for FY2018. This will be used with the remaining 40 billion yen in the FY2017 investment plan, bringing this second investment to 110 billion yen. As announced on March 17, 2016 announcement “Notice of Construction of New Semiconductor Fabrication Facility,” Toshiba decided on a construction and equipment investment plan for the new fabrication facility, with an estimated cost of approximately 360 billion yen from FY2016 to FY2018. The company will update its investments plans to reflect any subsequent changes.

TMC has recently asked SanDisk, its collaborator in three joint ventures for investment in manufacturing equipment at TMC’s Yokkaichi Operations, whether it intends to jointly participate in this second investment for the Phase-1 clean room in the Fab 6 facility.

The global CMOS image sensor market is expected to grow at a CAGR of more than 12% during the forecast period, according to Technavio’s latest market research.

In this market research report, Technavio covers the market outlook and growth prospects of the global CMOS image sensor market for 2017-2021. The market is further categorized into four application segments, including consumer devices, automotive, security, and industrial. The consumer devices segment accounted for close to 83% of the market share in 2016.

“The market is characterized by a technological shift from charged CCD sensors to CMOS because of the simple manufacturing process and low costs. Though CCD sensors offer better features, such as great light sensitivity and quality, their adoption is low because of their complicated design and high-power consumption. The consumer device segment will remain the key market driver during the forecast period owing to the increase in the demand for mobile-related applications,” says Chetan Mohan, a lead sensors research expert from Technavio.

CMOS image sensor market in Americas

The CMOS image sensor market in the Americas is expected to maintain its steady growth trajectory in the coming years. The early adoption of new technologies and gadgets drives the market growth. In addition, the region has a large consumer base for consumer electronics, such as tablets and smartphones.

The high rate of industrial automation in the US drives the demand for CMOS image sensors as they are widely used in automated manufacturing and process machinery. The US and Canada boast of a strong healthcare sector which will lead to demand for a large number of medical devices that are integrated with CMOS image sensors.

“The growing demand for camera-enabled phones in South America will drive the market in the region. The government in South America is also focusing on urbanization and improving healthcare sectors. The increasing use of these sensors in automobiles and medical equipment is expected to have a positive impact on the market in the region,” says Chetan.

CMOS image sensor market in APAC

The region is expected to grow at the highest CAGR, owing to the presence of many manufacturing units for consumer electronic devices. In addition, APAC has the largest customer base for consumer devices. Rising disposable incomes have led to increased consumer spending capacity, which has further fueled the demand for latest gadgets. China, Japan, Taiwan, South Korea, and India are the key revenue contributors to the market in the region. These countries have numerous consumer electronics manufacturing units.

The presence of numerous semiconductor manufacturers in Japan, Taiwan, Korea, and China, will fuel market growth. In addition, the availability of low-cost labor and setting up of production facilities by global vendors are factors that will have a positive impact on the market in the region.

CMOS image sensor market in EMEA

EMEA will exhibit the lowest growth compared with other regions because of the low concentration of image sensor manufacturers and small consumer base. Germany is among the leading nations in the region. The country has numerous leading car manufacturers that offer CMOS sensing technology in their vehicles. The technology ensures passenger safety and promotes the development of intelligent vehicle systems. The country plans to automate a majority of the industrial process by the end of the forecast period. Advanced R&D in the medical field will also drive the demand for image sensing technology. South Africa is expected to account for the highest contribution to the market share in this region.

The top vendors in the global CMOS image sensor market as highlighted in this market research analysis are:

  • Sony
  • Samsung
  • OmniVision Technologies
  • ON Semiconductor

SEMICON Europa 2017 will take place in Munich for the first time, co-located with productronica (14-17 November in Munich, Germany). SEMICON Europa will showcase the critical issues shaping the entire electronics manufacturing supply chain. Fourexecutive keynotes will share their thought leadership on current opportunities for Europe: Maria Marced, president, TSMC Europe; Stefan Finkbeiner, CEO, Bosch Sensortec; and Frank M. Rinderknecht, founder and CEO of Rinspeed Inc.

“Innovations in semiconductor manufacturing are at the heart of the value chain driving innovations enabling key future growth drivers in Mobile, Automotive, Medical, passive and intelligent computing as well as AR and VR,” stated Laith Altimime, president, SEMI Europe. SEMICON Europa programs, sessions, and speakers will illuminate this year’s theme “Empowering Innovation and Shaping the Value Chain.”  Highlights of SEMICON Europa include:

  • Fab Management Forum: Quality Challenges – Solutions for Tomorrow ─ Topics include:Future of digital vehicles and requirements for quality and availability of semiconductors with Daimler AG, an analysis of Human failure and mindset change by European School of Management and Technology (ESMT) Berlin, and how innovative sensor and analytics solutions enable new applications in the fab of tomorrow by KINEXON GmbH.
  • Advanced Packaging Conference: Electronics Packaging and Test for Future Mobility ─With Yole Développement on the dynamics of the advanced packaging ecosystem, Robert Bosch GmbH on automotive, Infineon Technologies on packaging for automotive ─ challenges and solutions, RoodMicrotec GmbH on wafer and final test in the new era of electronics, and STMicroelectronics on packaging challenges for robust miniaturization.
  •  Power Electronics Conference: From Materials to Systems,The Latest Innovations ─Covering power electronics applications for Automotive by Fraunhofer Institute for Integrated Systems and Device Technology IISB, a forecast of the next five years to reveal how technology development will shape the power electronics market by Yole Développement, and  Cambridge University on Silicon and Wide bandgap devices in power electronics.
  • New! Materials Conference: Connected World ─ New Material Challenges and Solutions ─Includes a keynote by Christophe Maleville, SOITEC, on how to better optimize performance, power budget and cost to meet applications requirements; plus presentations from Volkswagen AG on the need for new industry alliances in automotive, FUJIFILM on maximum utilization of chemically amplified resist, and Dow Chemical on the information age and connectivity enabled by advanced electronic materials. The free Webinar “Connected World: New Material Challenges and Solutions – Market Update and Outlook“ is planned on 27 September.
  • New! European Connect2Car Forum ─ A new Forum in collaboration with SAE International. Insights for automotive OEM and supplier executives, consumer electronics leaders, mobile application developers, and aftermarket entrepreneurs focusing on enhancing the driver experience and accelerating the deployment of connected and autonomous vehicle technologies.
  • New! 2017FLEX Europe “Be Flexible” ─ New collaboration between FLEX and Fraunhofer EMFT. Insights on innovative solutions for flexible and stretchable systems by Würth Elektronik GmbH,  technology and applications of chip-film patch for hybrid systems in foil by IMS CHIPS, new capabilities and applications of flexible components by E Ink Corporation, and insight on how potentials of System-in-Package technologies will affect the future by Bosch.

SEMI and Messe München Joint Press Conference will take place on 14 November at 11:00-12:00, at Messe München Press Conference Center.

By Dave Anderson, president, SEMI Americas

The SEMI Strategic Materials Conference (SMC) is the industry’s premier event devoted to technology and business drivers of materials in the electronics supply chain. Slated for September 18-20 in San Jose, Calif., the 18th annual SMC “offers a unique chance to network and discover opportunities in and around the industry in a year where dramatic growth has returned to the semiconductor market,” observes SMC 2017 co-chair Mark Thirsk of Linx Consulting, who will provide opening remarks at the conference.

SMC features three distinguished keynote speakers: AMD’s CTO, Mark Papermaster, will discuss “The Future of Semiconductors: Moore’s Law Plus.”  Next, Lam Research’s CTO, Dave Hemker, will present “The Next Level: Is it Time for Equipment and Materials Suppliers to Collaborate More?” describing how the current market environment is having a rippling effect across the supply chain. “As the continuation of Moore’s Law becomes ever-more challenging, closer, earlier collaboration between materials suppliers, equipment makers, and semiconductor manufacturers becomes necessary,” says Hemker.   SMIC’s Sunny Hui, senior VP of Marketing, will kick off day two telling the audience how to “Collaborate to Win in China.”

The first day’s agenda features “Economic and Market Trends: The Consolidation Game (M&A), China, 200mm & More,” with speakers from Applied Materials, Credit Suisse, Linx Consulting, and SEMI China.

Detailing Heterogeneous Integration for Performance and Scaling, UCLA’s Subramanian S. Iyer will describe how adapting silicon-inspired processing, integration, and materials to advanced packaging constructs may be the key to perpetuating Moore’s Law.

The Future of Materials Market in China will focus on the state of China’s semiconductor materials industry, government policies, growth opportunities for suppliers, and best practices for companies operating in this expanding environment.  Hear from Dow Chemical, Konfoong Materials International (KFMI) and SMIC.

More than twenty program sessions will explore the developments driving industry growth and enabling innovative new materials for today’s evolving electronics industry. The conference agenda also includes:

  • Process Challenges at 5nm & Beyond: Insights from ARM, Samsung, and TSMC.
  • Universities − Innovation Drivers: Viewpoints from Stanford University, University of California Berkeley, and University of Chicago.
  • Materials Supply Chain Challenges in Adjacent Industries: Perspectives from Linde Group, PARC (Xerox), and Pixelligent Technologies
  • Heterogeneous Integration − Design to New Materials & Packaging: Insights from ASE Group, imec, and UCLA

SMC 2017 will close with an Executive Panel discussion addressing emerging material challenges for each participant’s company and the segment within which it operates. Executives from Intel, Tokyo Electron, TSMC and Versum Materials will share their views on how the industry can collectively address challenges through focused R&D investment, collaboration throughout the vertical supply chain, and the application of innovative business strategies to ensure a win-win for all companies across the extended supply chain.

I hope to see you at the SEMI Strategic Materials Conference this month. Learn more and register here.

Note: The SEMI Strategic Material Conference (SMC) is organized by the Chemical and Gas Manufacturers Group, a SEMI not-for-profit Special Interest Group comprised of leading manufacturers, producers, packagers, and distributors of chemicals and gases used in the electronics industry.

 

To perpetuate the pace of innovation and progress in microelectronics technology over the past half-century, it will take an enormous village rife with innovators. This week, about 100 of those innovators throughout the broader technology ecosystem, including participants from the military, commercial, and academic sectors, gathered at DARPA headquarters at the kickoff meeting for the Agency’s new CHIPS program, known in long form as the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies program.

Many future microelectronics systems could be assembled with a library of plug-and-play chiplets that combine their respective modular functions with unprecedented versatility.

Many future microelectronics systems could be assembled with a library of plug-and-play chiplets that combine their respective modular functions with unprecedented versatility.

“Now we are moving beyond pretty pictures and mere words, and we are rolling up our sleeves to do the hard work it will take to change the way we think about, design, and build our microelectronic systems,” said Dan Green, the CHIPS program manager. The crux of the program is to develop a new technological framework in which different functionalities and blocks of intellectual property—among them data storage, computation, signal processing, and managing the form and flow of data—can be segregated into small chiplets, which then can be mixed, matched, and combined onto an interposer, somewhat like joining the pieces of a jigsaw puzzle. Conceivably an entire conventional circuit board with a variety of different but full-sized chips could be shrunk down onto a much smaller interposer hosting a huddle of yet far smaller chiplets.

Central to the design and intention of the program is the creation of a new community of researchers and technologists that mix-and-match mindsets, skillsets, technological strengths, and business interests. That is why the dozen selected prime contractors for the program include large defense companies (Lockheed Martin, Northrop Grumman, and Boeing), large microelectronics companies (Intel, Micron, and Cadence Design Systems), other semiconductor design players (Synopsys, Intrinsix Corp., and Jariet Technologies), and university teams (University of Michigan, Georgia Institute of Technology, and North Carolina State University). What’s more, many of these prime contractors will be working with additional partners who will extend the village of innovators working on the CHIPS program.

“If the CHIPS program is successful, we will gain access to a wider variety of specialized blocks that we will be able to integrate into our systems more easily and with lower costs,” said Green. “This should be a win for both the commercial and defense sectors.”

Among the specific technologies that could emerge from this newly formed research community are compact replacements for entire circuit boards, ultrawideband radio frequency (RF) systems, which require tight integration of fast data converters with powerful processing functions, and, by combining chiplets that provide different accelerator and processor functions, fast-learning systems for teasing out interesting and actionable data from much larger volumes of mundane data. “By bringing the best design capabilities, reconfigurable circuit fabrics, and accelerators from the commercial domain, we should be able to create defense systems just by adding smaller specialized chiplets,” said Bill Chappell, director of DARPA’s Microsystems Technology Office.

“The CHIPS program is part of DARPA’s much larger effort, the Electronics Resurgence Initiative, in which we are striving to build an electronics community that mixes the best of the commercial and defense capabilities for national defense,” Chappell said. “The ERI, which will involve roughly $200 million annual investments for the next four years, will nurture research in materials, device designs, and circuit and system architecture. The next round of investments are expected this September as part of the broader initiative.”

Dow Corning, a developer of silicones, silicon-based technology and innovation and a wholly owned subsidiary of The Dow Chemical Company (NYSE: DOW), today announced that it received the prestigious Global Supplier Award from The Bosch Group, a worldwide supplier of technology and engineering services. Issued every two years, Bosch’s coveted awards recognize companies that have demonstrated outstanding performance in the manufacture and supply of products or services to Bosch – especially in terms of quality, pricing, reliability, technology, and continuous improvement. Bosch recognized 44 companies from 11 countries this year.

“We are delighted and very proud that Bosch has recognized Dow Corning’s commitment to its success with this prestigious award,” said Jörg Kersten, Dow Corning’s global key customer manager for The Bosch Group. “Like Bosch, we believe that long-term partnerships and close collaboration are the key to mutual success. It continues to be our privilege to work alongside their industry-leading team of innovators, and support their mission to be a top global engineer of automotive and electronic components.”

Karl Nowak, president of Corporate Sector Purchasing and Logistics at Bosch, informed Dow Corning via a letter that it had received the honor. Nowak’s letter read, in part: “Success in an increasingly connected and digitalized world requires strong and reliable partnerships. Your company’s outstanding performance and exemplary teamwork in 2015-16 contributed to Bosch’s success. To demonstrate our appreciation to you and your employees, we would like to honor you with the Bosch Global Supplier Award.”

Bosch officially bestowed its awards at a gala award ceremony held on July 12 in Stuttgart, Germany, and hosted by Robert Bosch GmbH’s executives and board members. Patrick McLeod, global business director, Dow Performance Silicones, and Wiltrud Treffenfeldt, chief technology officer, EMEAI at Dow, attended to accept the award on behalf of Dow Corning.

North America-based manufacturers of semiconductor equipment posted $2.29 billion in billings worldwide in June 2017 (three-month average basis), according to the June Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in June 2017 was $2.29 billion. The billings figure is 0.8 percent higher than the final May 2017 level of $2.27 billion, and is 33.4 percent higher than the June 2016 billings level of $1.72 billion.

“Through the first half of the year, 2017 equipment billings are 50 percent above the same period last year,” said Dan Tracy, senior director, Industry Research & Statistics, SEMI.  “While month-to-month growth is slowing, 2017 will be a remarkable growth year for the semiconductor capital equipment industry.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
January 2017
$1,859.4
52.3%
February 2017
$1,974.0
63.9%
March 2017
$2,079.7
73.7%
April 2017
$2,136.4
46.3%
May 2017 (final)
$2,270.5
41.8%
June 2017 (prelim)
$2,288.9
33.4%

Source: SEMI (www.semi.org), July 2017
SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

 

Multitest’s new 0.3 mm pitch Atlas contactor successfully passed a demanding customer production floor evaluation. The customer’s evaluation measures confirmed that the Atlas did reduce the customer’s cost of test while improving test yield and increasing throughput. Based on the evaluation results, the customer ordered a significant number of Atlas 030 contactors to support their new product WLCSP production ramp.

The customer is a long time user of Multitest contactors and after reviewing the new Atlas design they were eager to evaluate it. It is the added strength of the Atlas cruciform tip that captured the customer’s attention.  Not only is the Atlas mechanically superior, the Atlas offers electrical performance that allows the customer to test to the true performance of the device. The evaluation ended with the customer placing an order for a significant quantity of Atlas 030 contactors.
The key to the WLCSP Atlas’s high performance, high reliability and superior electrical contacting is the combination of increased mechanical tip strength and short probe electrical performance.  Atlas WLCSP test contactors achieve mechanical reliability with a rigid “cruciform” tip applied to Multitest’s QuadTech flat probe technology.  The Atlas 030 offers a short electrical path, with lower capacitance and inductance that is ideal for functional and AC parametric testing of WLCSP devices that require high system bandwidth and throughput gains in large multisite test applications.

The cruciform tip provides increased tip rigidity with a much greater immunity to breakage than traditional WLCPS probes used in earlier-generation test sockets. The Atlas 030 has 0.310 mm of compliance for bump structures that requires a larger compliance window for reliable contacting in high parallel test applications.

Bert Brost, Senior Product Managers, explains: “We are very proud of the positive result of the evaluation. The evaluation by the customer confirmed what we already knew, the Atlas 030 contactor is a high performance solution for WLCSP testing.”