Category Archives: Metrology

April 4, 2012 – PRNewswire — Metrology tool supplier Nova Measuring Instruments Ltd. (NASDAQ:NVMI) will provide the production tools of record (PTOR) performing chemical mechanical polishing (CMP) metrology at a leading semiconductor foundry.

This is the foundry’s first implementation of an integrated metrology solution in production. They performed a proof of concept evaluation, finding improvement in production yields and return on investment (ROI). The initial order for multiple tools will be delivered over Q1 and Q2.

The foundry is currently a customer of Nova’s advanced stand-alone metrology tools and MARS modeling software for semiconductor production in various technology nodes, at different process steps.

The integrated metrology platform adoption will lead to more business as the foundry extends its integrated metrology deployment in current and future nodes, said Gabi Seligsohn, president and CEO of Nova.

Nova Measuring Instruments Ltd. makes advanced integrated and stand-alone metrology tools for the semiconductor manufacturing industry. Nova is traded on the NASDAQ & TASE under the symbol NVMI. Website: http://www.nova.co.il.

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April 2, 2012 – BUSINESS WIRE — Bruker Corporation (NASDAQ:BRKR) acquired all of the shares of SkyScan N.V., a scientific instruments company serving materials science and life sciences/pre-clinical imaging needs.

SkyScan makes advanced, high-resolution micro computed tomography (micro-CT) systems for 3D X-ray imaging, including 3D imaging of electronic components; synthetic materials, ceramics, and other materials; new devices such as microsensors and fuel cells; and medical and geological applications.

Financial details of the buy were not disclosed, but Bruker expects it to add approximately $13 million in revenue for the remainder of 2012. SkyScan will be renamed Bruker microCT NV, providing CT instruments under the SkyScan brand. It will operate at its Belgium facility under the same management, with founder and CEO Dr. Alexander Sasov taking on the title managing director and CEO. Bruker will invest in additional micro-CT applications and demo centers worldwide.

SkyScan micro-CT 3D X-ray imaging tools will now be sold through Bruker

Keithley Instruments, Inc. introduced the Model 2657A High Power System SourceMeter® instrument, which is optimized for high voltage applications such as testing power semiconductor devices, including diodes, FETs, and IGBTs, as well as characterizing newer materials such as gallium nitride (GaN), silicon carbide (SiC), and other compound semiconductor materials and devices. It is also useful for characterizing high speed transients and performing breakdown and leakage tests on a variety of electronic devices at up to 3,000V.


The instrument offers a flexible, four-quadrant voltage and current source/load coupled with precision voltage and current meters. It combines the functionality of multiple instruments in a single full-rack enclosure: semiconductor characterization instrument, precision power supply, true current source, 6-1/2-digit DMM, arbitrary waveform generator, voltage or current pulse generator, electronic load, and trigger controller, and is fully expandable into a multi-channel, tightly synchronized system via Keithley’s TSP-Link® technology. The Model 2657A can source or sink up to 180W of DC power (±3,000V@20mA, ±1500V@120mA). The Model 2657A also offers 1fA resolution, allowing it to make fast, accurate sub-picoamp measurements even when sourcing up to 3000V.

Price starts at $17,900 USD, depending on configuration and geography. Shipments will begin in May, with lead times of two weeks ARO. ACS Basic Edition software: $5,000 USD. Model 8010 High Power Test Device Fixture: $6,500 USD.

The future of electronics is increasingly being shaped by two major trends: mobile computing and the “internet of things.” The pervasiveness of mobile is fairly obvious, with 1.2 billion units expected to ship in 2014. The internet of things is less obvious, but slowly becoming a reality. The idea is that all objects in our environment are equipped with sensors and identifying devices and connected to the internet.  And I’m talking about everything, from buildings to freeways to food containers to medicine.

When the internet of things becomes a reality, companies would not run out of stock, as involved parties would know which products are required and consumed. Mislaid and stolen items would be easily tracked and located, as would the people who use them.

At the recent Common Platform Technology Forum — produced by Global Foundries, Samsung and IBM — Simon Segars, executive vice president and general manager of the physical IP division at ARM, spoke about the impact of the internet of things and mobile computing on the way electronics are designed and used. “Microcontrollers and sensors are getting embedded into pretty much everything we interact with,” he said. “You’re going to need very small and very power-efficient technology, and a power-efficient wireless network to bring it all together.”

Segars said changes in computing requirements will transform how chips in servers, wireless communication networks and mobile phones are designed. “It’s the case in pretty much any form of electronics, if you know what you’re doing, dedicated hardware is the best way of saving power. This is why you have a video engine and a graphics engine in your phone — because it’s very expensive to do it on a general purpose computer. The same holds true for servers. If you know what you’re doing, you might as well build yourself some dedicated hardware to do it,” he said. Servers of the future could potentially be powered by SoCs instead of dedicated, big processors. “This is a great thing for the fabless industry because the fabless world knows how to make SoCs really well,” he said.

Similarly, rather than get “fixated” by the apps processor in mobile phones, Segars said it’s important to pay attention to the other chips used, such as smaller control chips used to manage battery power or the touch screen, for example. “These aren’t necessarily manufactured on the most leading edge digital process,” he said. “These are using older, more mature processes which can drive higher voltages. There’s a need for continual evolution on that kind of process technology, because it’s going to be required for a long time.”

As far as the “internet of things” goes, Segars said it’s a “bit like science fiction right now,” but it’s probably going to happen. Sensors will be built into buildings, the freeway, and into the environment in general, detecting what is going on in the world. “It’s going to generate just a phenomenal amount of data which is going to back to all those servers, and it’s going to need processing and be delivered to you in a way that’s actually useful so you can make some decisions. All of this is driving the demand for semiconductors, driving the demand for lower power electronics and driving the demand for future higher bandwidth wireless devices between all these devices,” he said.

Phones are now outselling PCs and are the primary mechanism for people engaging with the outside world. Segars said this is driven by the technology innovations. “By continually driving power consumption down, we’ve been able to come up with these really small form factors, devices that are always on and always connected to the outside world. It’s really been quite staggering,” he said.

He noted that, while the technology has evolved, the industry behind that technology has evolved a lot as well. In the 70s, companies were vertically integrated.  Today, the industry has desegregated from companies that did everything to these tiers of companies who have specialized. “The benefits of that specialization have been improved economies of scale and companies that have been profitable in their own right without having to do everything,” he said.

He also commented on the need to look at the supply chain in a new light. “It’s easy to think of this as a stack, from somebody doing design down to somebody doing manufacturing and building equipment, but it’s much more complex than that. In order to not lose efficiency as you fragment into this desegregated world, it become very important for companies to collaborate in what they’re doing. If you own everything, the good news is you can tweak absolutely everything because it’s all yours. But that’s very expensive. If you don’t own everything, you have to rely on all of these companies in your supply chain to actually work together and drive out potential inefficiencies.”   

According to Segars, a better way to think about the industry today is a circle where all these companies in different industries are working together to provide an overall complete solution. “The really smart people have realized they have to share a lot of information to make what they do as best as it can possibly be to feed into this supply chain so the end product can be the best it possibly can be. “

Segars gave a tip of the hat to the high costs of building new fabs and to conduct R&D. Earlier in the forum, Samsung’s Ana Hunter put a price tag of a new fab at $7.5 billion. Segars help up EUV as an example. “Before EUV really gets unleashed on the world on a production scale, the R&D costs for EUV will be well over $1 billion.”

The real question though is whether the semiconductor can continue going down the same path given these high costs and approaching physical limits. “We’ve seen over the history of the semiconductor industry the costs of transistors go down, roughly halving about every 18 months for decades. These costs are going non-linear. The concern is that if we are unable to do anything about that, if we’re not able to continue to drive out inefficiencies, then you have to ask yourself the question, ‘Are transistors going to get more expensive?’ If that’s the case, then that really disrupts how the semiconductor industry has evolved for many, many decades,” Segars said.

 Simon Segars joined the board in January 2005 and was appointed EVP and General Manager of the Physical IP Division in September 2007. He has previously been EVP, Engineering, EVP, Worldwide Sales and latterly EVP, Business Development. He joined ARM in early 1991 and has worked on many of the ARM CPU products since then. He led the development of the ARM7 and ARM9 Thumb® families. He holds a number of patents in the field of embedded CPU architectures.

March 21, 2012 — Worldwide semiconductor manufacturing equipment spending is projected to total $38.9 billion in 2012, an 11.6% decline from 2011 spending of $44 billion, according to Gartner, Inc.

“Weak market conditions in the second half of 2011 caused pullbacks in expansion plans throughout the semiconductor manufacturing industry,” said Klaus Rinnen, managing vice president at Gartner. “This investment weakness will continue through the first half of 2012 and will surge in the second half of the year. We’re basing these assumptions on the aggressive spending plans announced by the major semiconductor manufacturers. There is a risk that some capacity expansion plans will slip from the second half of 2012 into 2013.”

“Downward pressure on utilization rates is easing, with the result that utilizations will begin to climb upwards again in the second quarter of 2012,” Rinnen said. “Once the supply is balanced, DRAM and foundry manufacturers will need to begin to increase spending to meet an increase in demand, as the PC market rebounds and consumers begin spending as the economy stabilizes.”

Gartner analysts said worldwide semiconductor manufacturing equipment spending will return to double-digit growth in 2013 when spending is projected to total $43 billion, a 10.5% increase from 2012 (see the table). Worldwide semiconductor capital spending is forecast to total $60.9 billion in 2012, down 7.3% from 2011 spending of $65.8 billion in 2011. Capital spending is expected to grow 3.5% in 2013.

Also read: Semiconductor fab equipment spending to hit a record in 2013 from SEMI

Table. Worldwide Semiconductor Manufacturing Equipment Spending Forecast, 2011-2016 (Millions of Dollars). SOURCE: Gartner, March 2012.

 

2011

2012

2013

2014

2015

2016

Semiconductor Capital Spending ($M)

65,754.4

60,937.4

63,042.4

66,863.6

62,540.2

67,894.4

Growth

16.3%

-7.3%

3.5%

6.1%

-6.5%

8.6%

Capital Equipment ($M)

44,041.6

38,926.6

43,030.4

46,293.1

42,862.6

46,474.4

Growth

8.4%

-11.6%

10.5%

7.6%

-7.4%

8.4%

Wafer Fab Equipment ($M)

35,822.4

31,289.5

33,487.0

37,100.0

34,090.8

36,542.5

Growth

13.3%

-12.7%

7.0%

10.8%

-8.1%

7.2%

Wafer-Level Packaging and Assembly Equipment ($M)

1,472.7

1,404.9

1,893.7

2,034.1

2,214.0

2,646.9

Growth

17.2%

-4.6%

34.8%

7.4%

8.8%

19.6%

Die-Level Packaging and Assembly Equipment ($M)

4,311.9

3,997.3

4,766.1

4,305.4

3,859.5

4,004.4

Growth

-12.0%

-7.3%

19.2%

-9.7%

-10.4%

3.8%

Automated Test Equipment ($M)

2,434.5

2,234.8

2,883.6

2,853.6

2,698.3

3,280.6

Growth

-14.9%

-8.2%

29.0%

-1.0%

-5.4%

21.6%

Other Spending ($M)

21,712.8

22,010.8

20,012.0

20,570.5

19,677.6

21,420.0

Growth

36.7%

1.4%

-9.1%

2.8%

-4.3%

8.9%

The wafer fab equipment (WFE) market closed out 2011 with spending up 13.3%, based on strong momentum in the first half, however, WFE spending is forecast to decrease 12.7%. WFE spending in 2012 will primarily be on leading-edge technology, as the 20mm and 28/32 nm ramp up.

Gartner analysts said wafer fab manufacturing capacity utilization will decline into the low-80% range by the middle of 2012, before slowly increasing to about 90% by the end of 2012. Leading-edge utilization will return to the low 90% range by the second half of 2012, providing for a positive capital investment environment.

Back-end equipment markets (which include wafer-level packaging and assembly equipment, die-level packaging and assembly equipment, and automated test equipment) will see a modest decline in 2012, but it will be followed by growth and sales of more than $9.5 billion in 2013.

“Above market action in advanced packaging will not be sufficient for a positive growth rate this year, but it will be the driver for growth in 2013,” Rinnen said.

The capital spending forecast estimates total capital spending from all forms of semiconductor manufacturers, including foundries, and back-end assembly and test service companies. This is based on the industry’s requirements for new and upgraded facilities to meet the forecast demand for semiconductor production. Capital spending represents the total amount spent by the industry for equipment and new facilities, as well as the outlay for land, buildings, furnishings, etc… Capital equipment spending includes all equipment needed to process, inspect, and test and package the chip.

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends. More information on Gartner’s semiconductor research can be found in the Gartner Semiconductor Manufacturing Focus Area at http://www.gartner.com/technology/core/products/research/markets/semiconductorManufacturing.jsp. Gartner, Inc. (NYSE: IT) is a leading information technology research and advisory company.

March 21, 2012 — A clean, contamination-free semiconductor wafer processing environment is critical to maximize yield. As wafer circuitry and geometries shrink, particles become more likely to cause defects and yield loss. Particles generated during wafer processing by equipment component failure, wafer mishandling, excessive vibration, or other process irregularity can all contribute to defects.

Reducing or eliminating particle contaminants is an important step in tool qualification and chip manufacturing monitoring. Semiconductor tool operators must identify particles inside fab tools, as well as wafer storage and transport environments, for optimum operating conditions.

As part of its ongoing particle monitoring procedures, a high-volume 200mm wafer fab used a standard wafer monitoring method to regularly spot check 10,000 cassettes and lot boxes used in its wafer manufacturing operations. Cassettes and lot boxes were pulled for cleaning every 150 cycles; tools also were monitored for particle residue. Random checks were performed when particle problems were suspected. Using particle monitor wafers to inspect cassettes and lock boxes required two technicians for set-up and execution: placing monitor wafers inside each unit for one hour to collect contaminates, running monitor wafers through a surface scanner, and manually recording results.

Figure 1a, L to R. Particle monitor wafers, benchtop counter, and handheld counter. While surface scanning is currently the industry standard for particle detection, bench top and hand held airborne particle counters are also used because of their relatively low cost and easy operations. However, these technologies are limited in reach inside equipment and offer little or no information about the location of contamination in the tool.
Figure 1b. The airborne particle sensor (APS) wireless particle detection system.

 

While accurate, the particle monitor wafers proved time-consuming, resource-intensive and inefficient for the large amount of cassettes and lot boxes that the fab re-qualifies on an ongoing basis. Monitoring each cassette or lot box with a monitor wafer took at least one hour; daily throughput averaged 8 cassettes or lot boxes; that required 16 technician hours. The monitor wafer process did not provide remote real-time feedback, so one operator was needed for tool operation and another for set up, running the surface scan, and recording results.

The 200mm fab initiated a Manufacturing Monitor Program to find an alternative that would reduce qualification time, improve throughput, and provide statistical sampling of production cassettes and lot boxes to meet particles standards.

Portable and benchtop particle counters (Figure 1) offer real-time feedback, but the instruments require either tearing down the fab tool or running a series of test wafers, costing the fab significant downtime and labor. Handheld particle counters are limited by hand reach and require opening the tool.

A wafer-like, wireless airborne particle sensor offered an alternative wafer monitoring methodology for atmospheric tools. It enabled the fab to perform the same manufacturing monitoring tasks in three minutes inside a cassette or lock box that took monitor wafers one hour. Combining the flexibility of monitor wafers and the real-time capability of benchtop counters, the airborne particle sensor (APS) goes deep inside a tool and remotely communicates real-time data to a laptop.

Initially, the 200 mm fab utilized the APS in two different test condition scenarios: cassettes new from washer vs. cassettes in production; and lot boxes new from washer vs. lot boxes in production.

Figure 2. APS test results when comparing newly washed cassette vs. older production cassette in new lot box. Results show that cassettes remaining in production too long have excessive particles.

By comparing the particulates gathered on newly washed and production cassettes and lot boxes, the fab determined if process tools attracted more particles from cassettes/lot boxes that were in production for specific periods of time. Figure 2 shows a comparison particle count reading conducted by the APS in a production cassette and a newly washed cassette (Test time: 3 minutes). These results were consistent with output generated with monitor wafers over an hour of test time (see the table). Both metrology methods confirmed that cassettes remaining in production too long have excessive particle contamination.

Table. Comparison of time required to monitor cassettes and lot boxes using wafer monitors vs. the airborne particle sensor.

 

Compared to the fab’s previous monitoring method, the wireless airborne particle sensor more quickly measured numerous combinations of potential particle source elements, such as older production/newly washed cassettes and older production/newly washed lot boxes to determine the presence of particle sources and counts. Since the airborne particle wafer provided real-time feedback, operators could take a 3-minute reading and move on to the next unit for testing. The APS required just one operator vs. at least two for the monitor wafers.

Based on results from its comprehensive qualification project, the fab monitoring team replaced monitor wafers with airborne particle sensors as part of its pre-qualification process in checking cassette and lot box for particles to determine suitability for production.

The combination of fast particle counting, reduced technician operation requirements, and real-time output allowed the fab to increase test throughput by 20x, at half the manpower requirements. After adopting the airborne particle sensor for its manufacturing monitoring process, the fab estimated a reduction of monthly time spent on particle monitoring from 240 hours to 10 hours.

Particle monitoring as a troubleshooting tool at 300mm fab
While the APS proved successfully in increasing throughput efficiency for the 200mm fab in measuring tool particulate contamination as part of its prequalification procedures, the sensor also served as an effective troubleshooting tool for a 300 mm fab experiencing a high wafer defect rate of unknown origin. To determine the source of contamination, the fab wanted an effective troubleshooting and prequalification tool prior to using monitor wafers for final vacuum tool particle qualification.

Figure 3. The APS discovers the source of particle contamination within a 300mm fab in real-time.

Benchtop and handheld counters did not offer the reach to identify and isolate the source of particles in this fab scenario. Using monitor wafers during this stage of tool qualification would require segregation and running a separate monitor for each chamber, buffer, and load lock, a time-consuming option. The APS offered accessibility inside the process tools without opening the chambers, and provided real-time feedback on exactly when and where contaminants occurred.

The fab used the APS to scan the wafer path as it went through Chambers A and D, and performed additional spot checks of doors, handoffs, and robot motions. Placed into the tool generating wafer defects, the APS initially moved from the load-port, FI, load-lock and into the buffer. In these sections, the APS deemed particles at an acceptable average of 0.1 cumulative particles per second. When running through the Chamber A door, the APS immediately identified that the door was shedding particles and causing contamination problems (Figure 3). As a result, the fab replaced the Chamber A door slider assembly, which was not yet scheduled for preventative maintenance.

While the fab continues to use monitor waters in vacuum conditions for final qualification, the APS saves significant time in identifying particle contamination sources during tool pre-qualification stages.

Allyn Jackson, CyberOptics Semiconductor, can be reached via the company’s website at www.cyberopticssemi.com.

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March 19, 2012 – BUSINESS WIRE — Advantest Corporation (TSE:6857, NYSE:ATE) began producing micro electro mechanical system (MEMS) relays, shipping samples in April 2012. The MEMS relays will be used in semiconductor testing equipment, high-speed communications devices, high-frequency wave measurement equipment and their components.

Mass production will begin in January 2013.

Advantest manufactures the MEMS with its proprietary deposition technology, creating 1µm-thick piezoelectric film. This enables a smaller form factor and lower actuation voltage (12V) compared to high-frequency wave relays using electromagnetic or electrostatic actuation. The MEMS device is available in 5.4 x 4.2 x 0.9mm or 2.9 x 3.4 x 0.9mm form factors.

The MEMS are not easily affected by ambient static electricity, like electrostatic relays. The relay also has high reliability, using contact-point control technology honed in Advantest’s semiconductor testing equipment. Using Advantest’s high-frequency measurement technology, the relay can handle up to 20GHz high-frequency transmission, with 50Ω characteristic impedance.

Advantest now plans to introduce products outside the semiconductor testing area, in fields such as automotive and pharmaceutical/medical care.

Advantest provides automatic test equipment (ATE) for the semiconductor industry and measuring instruments used in the design and production of electronic instruments and systems. More information is available at www.advantest.com.

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March 19, 2012 – GLOBE NEWSWIRE — ATE provider LTX-Credence Corporation (Nasdaq:LTXC) released the Diamondx test platform for application-specific standard products (ASSP) and the DragonRF for radio frequency (RF) devices. In addition, LTX-Credence launched a SerDes test instrument and new testing software.

The Diamondx tool increases tester throughput, offers better multi-site test capability, and has lower capital expenditure and operations costs than comprable tools, according to LTXC. The tool boasts a small footprint with an energy-efficient, air-cooled design. Diamondx is a universal slot architecture that allows for 20-slot, 40-slot and 60-slot configurations. It is compliant with Integrated Multi-System Architecture (IMA) technology, making it upgradeable on the production floor as needed. The tester can accommodate over 5000 pins, and be configured with a range of instruments. Its high-speed data bus is based on PCI-Express-2 industry standard to support high data, high site count and the emergent adaptive test data payload requirements

The Diamondx SerDes instrument Dx-HSIO debuts with the Diamondx platform. It offers 8 lanes of SerDes test capability to 6.4Gbps, enabling lower-cost embedded-clock SerDes lane testing. The Dx-HSIO performs parametric testing of SerDes Tx and Rx ports, aiming for the mobility and consumer ASSP markets.

The Diamondx platform was designed with customer input, and purchase orders are in for testers, said David Tacelli, president and CEO at LTX-Credence. Deployment will soon occur at key outsourced semiconductor assembly and test (OSAT) providers.

LTX-Credence’s next-generation RF tester, DragonRF, targets low cost-of-test for RF devices. Universal RF ports with optional Port to Pin adapter enabling configurations up to 128 RF pins. DragonRF can be configured with 16, or 32 universal vector RF ports per module, with an optional port to pin expander doubling the number of RF ports to 64 pins. The flexible architecture enables price, test coverage, and time balancing. LTXC boasts that the tester’s RF switching technology provides industry-leading settling times. DragonRF provides 6GHz modulated source, 8GHz measure, less than 1ms settling time, and up to 8 receiver paths each with an analog bandwidth exceeding 200MHz for octal site parallel RF measurements. The RF generators are compact to save power and space. DragonRF has been designed to work across multiple test platforms. It will be available in Q2 2012.

The LTXC semiconductor testing software platform Unison features a common graphical test programming environment for Diamond, X-Series, and future product offerings; fast test program development with tools to streamline the validation process of complex system-on-chip and system-in-package devices; a flexible test program structure to serve an entire device family across wafer sort, final test, and different site counts; and the ability to run legacy test programs in the Unison software environment without modification.

Unison is currently available for Diamond test platform and will be available on other test systems later this year.

The Diamondx supports the DragonRF and the Unison test program development environment runs on the Diamondx along with existing Diamond and X-Series test platforms.

LTX-Credence is a global provider of ATE products for wireless, computing, automotive and entertainment market segments. Additional information can be found at www.ltxc.com.

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March 15, 2012 — VLSIresearch released its 2011 Top Semiconductor Equipment suppliers rankings, noting important acquisitions and strong spending in lithography tools in 2011. Semiconductor equipment spending was driven by aggressive capacity expansion in the foundry and logic sectors, mostly driven by mobile device production.

Also read: Semiconductor manufacturing equipment sales rose 9% in 2011

Capacity expansions in the memory sector were limited; strong pricing pressure reduced profitability for memory suppliers, prohibiting expansion.

Table. 2011 top semiconductor equipment suppliers (Worldwide sales, semiconductor equipment and service, $M). SOURCE: VLSIresearch inc Chip Market Research Services.
2011
rank		 Location Company 2011 sales
1 EU ASML 7877.1
2 NA Applied Materials* 7437.8
3 JA Tokyo Electron 6203.3
4 NA KLA-Tencor 3106.2
5 NA Lam Research 2804.1
6 JA Dainippon Screen Mfg. Co. 2104.9
7 JA Nikon Corporation 1645.5
8 JA Advantest** 1446.7
9 EU ASM International 1443.0
10 NA Novellus Systems 1318.7
11 JA Hitachi High-Technologies 1138.7
12 NA Teradyne 1106.2
13 NA Varian Semiconductor Equipment*** 1096.3
14 JA Hitachi Kokusai Electric 838.4
15 NA Kulicke & Soffa 780.9
Total top 15   40347.7
Year-over-year
growth		   13%
* Applied Materials (AMAT) includes Varian revenues for Nov 1 to Dec 31, 2011.
** Advantest includes Verigy’s revenues from July 1 to Dec 31, 2011.
*** Varian includes revenues as an independent company from Jan 1 to Oct 31, 2011.
(2011 Exchange rates).

Lithography spending enabled ASML to become the largest equipment supplier. ASML and fellow lithography equipment supplier Nikon grew 27% combined. Overall, the top 15 semiconductor equipment suppliers grew 13% in 2011.

Mergers & acqusitions: Advantest closed the Verigy acquisition in July; Applied Materials acquired Varian Semiconductor in November.

Japanese equipment suppliers recorded higher than average growth rates, with Advantest out front with 28% sales increase in 2011. Advantest saw the large increase thanks to its Verigy acquisition, and strong SOC test equipment sales in North America.

VLSIresearch inc provides market research and economic analysis on the technical, business, and economic aspects within nanotechnology and related industries. Website: http://www.vlsiresearch.com.

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The 2012 Common Platform Technology Forum took place March 14 at the Santa Clara Convention Center, with registration topping 1200 attendees by noon. The Common Platform is a Samsung /IBM/GlobalFoundries foundry services entity created to provide a common design space with an assured production capability.

The meeting kicked off with Ana Hunter, Samsung’s foundry business VP. The Common Platform had its roots in 65nm, and is presently working with 20nm gate-last and 14nm FinFET. Pre-revenue investment in the 20nm to 14nm range approaches $10B, with $1-2B in process development, $250M in IP & design libraries, $100M in chip design and $7B in fab construction.

Gary Patton, VP of SRDC at IBM, gave the first keynote with prognostication on the kind of technology development that is in the pipeline beyond traditional CMOS scaling. We are presently in the 3D decade, both in terms of 3D transistor design and 3D packaging integration. Next will be the decade of nanotechnology materials, in which the critical device dimensions do not depend on photolithography. Long-term R&D for this coming decade is already underway, as an extremely long lead time is required for commercialization to manufacturing. In 2011 IBM broke its own US patent record with 6,000 filings, a position it has held for 19 straight years. He hopes EUV will be ready for 10nm, “but we have a dual path.” At 10nm, EUV will provide a bump in k1 factor from 0.15 to 0.55, better that we enjoyed at 90nm. The scanner still needs a 10x improvement in light power, but additional work is needed in photoresist materials and mask fabrication and inspection technology. A new EUV Center of Excellence at Albany CNSE is expected to be operational later this year. Below 80nm, resist development is focusing on directed self-assembly (DSA) of block copolymers. Presently, the 22/20nm work is being done in East Fishkill; 14/10nm at Albany; and 7nm & beyond at Yorktown Research. Fully depleted device structures are the recurring theme going forward. CNT devices provide advantages over FinFETs in terms an order of magnitude reduction in power consumption at the same operating frequency, or an order of magnitude increase in frequency at the same power. With these innovations in design constructs and materials, Gary noted that the transistors are still much more amenable to scaling than interconnects, in which RC performance and structural reliability in both the conductors and the insulators doth protest mightily with scaling. Photonic interconnects on chip continues to be an area of intense development, moving now from fundamental unit performance demonstrations to system integration. The packaging concepts that he reviewed, while challenging, we consistent with advanced packaging concepts that have been progressing over the past five years. TSV is currently in volume manufacturing for power system chips. For stacking large DRAM chips on top of high performance MPU, he expects TSV to be in production within 2 years.

Subi Kengeri, head of the advanced architecture development group, filled in for GlobalFoundries CTO Gregg Bartlett to discuss the convergence of consumer mobility applications enabled by semiconductor technology advances. Foundries are a 300mm leading edge business growing at 15% CAGR. Since 90nm, the time between design start and tape out has been extending as design complexity increases. Design cost has been increasing at a 25% CAGR, whereas fab cost has been increasing at 18%, albeit a much larger number. Smart mobile computing is starting to move into the design driver seat that has up to now been occupied by MPU and GPU functions. Gate last HkMG at 20nm has been selected to meet these needs for 3rd generation HkMG FinFET mobile devices. At 14nm FinFET, you need 100 WPH (wafers per hour) throughput with EUV to break even with 193i with multiple patterning; 180 WPH provides a compelling advantage for EUV.

Jong Shik Yoon, Senior VP Semiconductor R&D at Samsung, spoke on opportunities and challenges in 3D device integration. SOI FinFETs were pioneered by IBM, while Samsung & Intel led the development of bulk FinFETs; the Common Platform supports bulk FinFET. SOI FinFET is used by IBM for server and specialty mobile applications. CNT FET work has been going on at Samsung as well.

Simon Segars, EVP & GM of the ARM Physical IP Division, wrapped up the morning with the fabless design and manufacturing implementation perspective. Industry drivers today are mobile computing, servers and the “internet of things.” Lower cost entry level smart phones represent another billion unit market globally. Mobile networks require about 1 server for every 600 phones, which puts the server demand into perspective, particularly as servers alone become a more significant percentage of world power consumption (still single digits for now). Global internet mobile traffic for 2015 will be about 966 exabytes (that’s a whole lot of gigabytes…). Simon is confident that the collaboration infrastructure that has gotten them to 20nm is extendable to 14nm.

A panel discussion featuring R&D leaders from the 3 Common Platform partners, ARM and CNSE on the R&D pipeline for future semiconductor technology innovation followed lunch. Michael Liehr, VP Research at CNSE pointed out several ways in which the fab there operates like an industrial site, with professors leading engineering teams that function as much like an IDM process development group as a graduate student research group. GlobalFoundries in Malta, NY is currently running 32nm production and 20nm full flow qualification. Work on DSA for photolithography started at IBM in 2000 and is still not ready for prime time. Similarly, copper interconnect development work started at IBM in 1984 and didn’t go into production until 1997, and even then came as a surprise to many outsiders. This is indeed a very long development pipeline.

Rama Divakaruni, IBM Chief Technologist, and Lars Liebmann, IBM Distinguished Engineer, opened a technology session on 14nm technology development with a review of the grand challenges. EUV shows up as a fuzzy transition some time in 2H14 shortly before the 14nm production ramp begins. Development started about 30 years ago in the national labs, but they hope to be able to support integrated process flow development at Albany by YE13. This seems to add gravitas to Gary Patton’s expressed hope that it will actually be ready for 10nm. Triple patterning with 198i is proposed for M1 to maintain design protocols on a path that will provide for a relatively easy return to the EUV goal of single exposure for M1. When pressed for a volume production implementation of EUV, Lars admitted ‘not before 2015’ but could be no more specific.

Yongjoo Jeon, Samsung’s Director of Foundry Technical Marketing gave an overview of their technology offerings at 20nm. Samsung has two versions of the 20nm platform: 20LPE available June 2012 and 20LPM, scheduled for full production May 2013. The 20LPM will use double patterning for isolation, via 0 and minimum pitch M1; both are HkMG gate last. Their 20nm devices are currently 10% below target for DC performance and 20% below target for AC performance, but the root causes are known and the program is considered on schedule to meet its release dates.

Mukesh Khare, Director of Semiconductor Technology at IBM Research, described the innovation pipeline beyond 14nm. Technology elements will include strain, HkMG and FinFET variations to leverage recent innovations, but nanowires will lead the way to a brave new world. We’ve transitioned to a domain in which scaling leads to degradation rather than improvement; new materials and process innovation are required in its place. A silicon nanowire is thought to represent the ultimate extension of the fin structure. The game is already afoot for applying strain to an individual nanowire. Alternative channel material candidates include III-Vs for nFET and Ge and high % Si-Ge for pFET, though challenges remain for silicon integration and contact resistance. Carbon electronics will provide extraordinary carrier mobility and extremely long carrier mean free paths. IBM’s 40nm epitaxial graphene transistor on SiC still holds the RF performance record at 280GHz. Polymer DSA is IBM’s pipeline alternative to EUV. The technology has already been used in the dielectrics used in air gap interconnects. The photoresist analog holds the promise of providing ‘pitch in a bottle.’ The double entendre will be better appreciated on days when it does not work. In combination with 193i, DSA has been used to produce 25nm line/space pairs with excellent line edge roughness.

Michael A. Fury is a Director & Senior Technology Analyst at Techcet Group.