Category Archives: Metrology

In this three-part series, SEMATECH’s authors cover metrology for FinFETs (Read Part 1) and 3D memory devices (Read Part 2), and defect detection capabilities at 22nm. The series appears in the upcoming March 2012 issue of Solid State Technology, along with other metrology-focused pieces from KLA-Tencor and Entegris. Subscribe to Solid State Technology magazine here.

February 23, 2012 — Future challenges for semiconductor defect metrology go beyond merely extending the capability of current technologies to meet International Technology Roadmap for Semiconductors (ITRS) requirements [8]. In recent years, the yield enhancement ITRS chapter has shown that the semiconductor industry consistently arrives at each new technology node without a long-term solution that combines defect sensitivity and throughput requirements at either development, ramp-up, or HVM phases.[8]   Both defect inspection and review are approaching their fundamental limits, which cannot be easily circumvented with gradual improvements on workhorse toolsets [13].

Figure 3. There is a single defect in this 22nm-node SRAM array. Can you find it?

In the specific case of inspection, optical simulations show that the defect contrast signal decays aggressively beyond the 22nm node, and predict that deep ultraviolet (DUV) bright field tools are likely to lack useable signal at or beyond the 11nm node. Wavelength scaling is not expected to provide an acceptable solution, prompting the need to seek alternative technologies that rely on different contrast mechanisms that may bridge this gap: interferometric (phase shift signal) [14], near-field (sub-wavelength resolution), or fast probe microscopy [15]. This path-finding effort will have a steep learning curve in terms of the application space for these techniques and the engineering to translate them into manufacturing-worthy tools. An alternative path to achieve sub-11 nm inspection capability may be electron beam (e-beam) inspection. In this case, the challenge is not resolution but increasing the system throughput by several orders of magnitude, which will most likely require a breakthrough in e-beam column parallelization. Early efforts are currently driven by lithography needs, but could benefit the inspection application space [16].

After defects are found (see Figure 3 for an example), they must be identified and sourced to maintain yield, requiring increasing amounts of off-line lab analysis. As features shrink, the X-ray interaction volume used in EDX for in situ defect analysis is becoming larger than the sizes of critical defects. The only solution appears to be an explosive growth in the workload of the TEM characterization lab. The limitation to TEM is not capability but throughput. TEM requires extensive, time-consuming sample preparation. Moreover, the microscope itself is a complex device that traditionally requires hours of work by a highly skilled operator to obtain good results. The solution therefore is to focus on both problems. To this end, SEMATECH is working with leading suppliers to develop faster sample preparation techniques, by both optimizing existing technologies and testing novel methods such as plasma focused ion beam (FIB) and laser-based milling. SEMATECH is also working in cooperation with its strategic partners to develop higher speed TEM imaging capabilities. This includes testing the latest generation of high sensitivity and high throughput windowless detector systems and developing automated image setup and metrology on critical dimension scanning/tunneling (CD-S/TEM) systems.

Figure 4. Sample image of a high-speed EDX element map taken on a SEMATECH FinFET sample. Total collection time was 4 minutes.

Conclusion
As device technology transitions from traditional scaling to new architectures, new application needs are driving metrology towards evolutionary and revolutionary shifts in technologies and methodologies. Adaptation to new tool paradigms, enhancements of existing technologies, and productivity innovations will be critical to maintain process control and high yield in the coming technology generations. The SEMATECH Advanced Metrology Program is well positioned to develop solutions to address the measurement challenges of next generation devices.

Miss Parts 1 and 2? Check them out:

References
[1] Doyle, B. et al., “Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout,” Symposium on VLSl Technology Digest of Technical Papers, pp. 133-134 (2003).

[2] Vaid, A., et al. “A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM.” Metrology, Inspection, and Process Control for Microlithography XXV. Proceedings of the SPIE, Volume 7971, pp. 797103-797103-20 (2011).

[3] Wang, C., Choi, K., Chen, Y. Price, J., Ho, D., Jones, R., Soles, C., Lin, E., Wu, W.L., Bunday, B. “Nonplanar high-k dielectric thickness measurements using CD-SAXS.” Proc. SPIE, v. 7272, pp 72722M (2009).

[4] De Martino, A., et al., “Comparison of Spectroscopic Mueller Polarimetry, Standard Scatterometry and Real Space Imaging Techniques (SEM and 3D-AFM) for Dimensional Characterization of Periodic Structures,” Proc. of SPIE Vol. 6922, 69221P (2008).

[5] Larson, D.J., and Kelly, T. F., “Nanoscale Analysis of Materials using a Local-Electrode Atom Probe,” Microscopy and Microanalysis Volume: 20, Issue: 3, pp: 59-62 (2006).

[6] Mody, J. et al., “Dopant and Carrier Profiling in FinFET-Based Devices with Sub-Nanometer Resolution,” 2010 Symposium on VLSI Technology, pp. 155-156

Abraham Arceo is a metrology development engineer at SEMATECH Advanced Metrology group. For the past three years he has been involved in film and defect inspection metrology development.

Benjamin Bunday is the project manager of CD Metrology and a Senior Member Technical Staff at SEMATECH (Albany, NY, USA). For ten years he has led SEMATECH/ISMI’s CD-SEM and OCD benchmarking, advanced CD technology evaluation and development efforts, and SEMATECH’s Advanced CD Metrology Advisory Group (AMAG).

Aaron Cordes is a research engineer for Sematech in Albany doing work on AFM, TEM, and focused ion beam metrology. He is also a PhD student with SUNY Albany’s College of Nanoscale Science and Engineering.

Victor Vartanian is a metrology engineer at SEMATECH in Albany, New York. Before coming to SEMATECH, he worked at Freescale Semiconductor in Austin, Texas, where he worked on applications of strained silicon to advanced transistor design and analytical applications of FTIR and mass spectrometry to environmental issues in semiconductor manufacturing and in process optimization.

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February 23, 2012 — SEMI’s International Strategy Symposium (ISS) meets for its Europe session February 26-28 in Munich, Germany. Following are some of the 450mm wafer presentations scheduled to take place. Solid State Technology chief editor Peter Singer will attend the event and share his observations on electroiq.com.

During a working lunch on the 28th, at Hotel Vier Jahreszeiten Kempinski, Jonathan Davis, president, Semiconductor Business Unit, SEMI , will gather presenters from ASM International, Intel, ENIAC, and imec to discuss 450mm:

Jonathan Davis
Every decade or so, leading semiconductor makers adopt a larger wafer standard to improve the productivity of chip making. These periods represent significant industry inflections and typically mark periods of consolidation and capital spending concentration. After several years of debate and analysis, the semiconductor industry is now poised to proceed with more substantive 450mm R&D. The expert panel moderated by SEMI will explore the implications of this looming industry transition for the European semiconductor supply chain and discuss strategies for enduring European competiveness.

Andreas Wild, Executive Director, ENIAC Joint Undertaking
The ENIAC Joint Undertaking is the public-private partnership chartered to contribute to the competitiveness and sustainability of the European nanoelectronics. Bringing together the national public authorities, the European Commission and the R&D actors, the ENIAC JU engaged in establishing a framework that shall enable the European semiconductor equipment and materials manufacturers to continue on their growth path and successfully compete at the cutting edge of 450mm innovation in semiconductors.

Bas van Nooten, Director European Cooperative Programs, ASM International
The European semiconductor equipment & materials industry is an important high tech industry in Europe and employs around 100.000 people. The major market for this industry lays outside Europe (Europe’s part in semiconductor equipment invest has declined to 6% in this millennium) and is dominated by the tier 1 semiconductor companies. The top 3  cover nearly 50% of the total worldwide invest. Therefore, if the world’s dominating semiconductor suppliers, now combined in the G450C consortium, are moving towards 450mm, it is key for the European Equipment and Materials (E&M) industry to be on top of this wafer transition.  The E&M industry has recognised this fact early on and have already established a 450mm initiative, called EEMI450, in 2009. Currently more than 45 companies and institutes have joined this initiative and since 2009 many European 450mm projects have started, the first one already finishing shortly. By this early engagement the European E&M industry strives to be competitive in this new market segment and gain market share.
The EEMI450 White Paper presented to the European Commission in Feb 2012 will be launched and shared with the press.

Paolo Gargini, Intel
The coming transition to 450mm will reduce costs and thereby enable the continuation of Moore’s Law, meaning ever more functionality for unit cost to the end user, and thus continue to expand the existing markets and create brand new ones. This wafer size transition will benefit the entire industry, from tools and materials suppliers to manufacturers, and ultimately, consumers. Several predictions and analysis reports indicate that silicon area demand will remain strong for the foreseeable future, making it imperative that the industry move to a larger wafer size as soon as possible. The transition to 450mm got a big kick start with the recent formation of the G450C, bringing together the leading five chip manufacturers. It is anticipated that G450C will act as a catalyst for the global supplier community around the world by linking with organizations like SEMI, EEMI450 etc. The move to 450mm will require industry-wide collaboration between device makers, consortia and suppliers. 450mm will also be beneficial for the environment, following upon the move last decade to 300mm, which reduced aggregate emissions per die by 43%.

Luc Van den hove, CEO, IMEC
In Europe, we need innovation leadership to keep Europe a global competitive player.
To maintain leadership in healthcare, in automotive, in energy, in communication systems we need leadership on innovation enabled by state-of-the-art technology platforms in more Moore and More than Moore.

We have many strengths in Europe: world-leading R&D institutes, world-leading equipment and material suppliers, and many high-end system companies. We need to strengthen our strengths and change Europe into an innovation engine. European companies have to differentiate themselves by innovative advanced technology.

We are convinced that open innovation is essential to enable an efficient innovation process. It allows very efficient cost sharing, risk mitigation, provides early insights, acceleration, etc. What is really needed for Europe for making the open innovation model work is: build critical mass, work globally with the leaders.

For effective open innovation we need full industry value chain integration (a multidisciplinary approach, innovation nowadays occurs at the boundaries of disciplines…). We can do such research only based on world-class state-of-the-art infrastructure. In order to maintain such innovation leadership position on the longer term, it will be imperative to set up a 450mm R&D and demonstration facility. This will be needed in order to support the entire European eco system (including equipment and material suppliers, …). Such 450mm R&D and demo facility will act as the primary innovation engine 5 to 10 years from now.

In a related presentation, Willy Van Puymbroek, European Commission, will share a short overview of ongoing projects related to 450mm that are financed by the European Union through the seventh Framework Programme.  The results from a study entitled ‘Benefits and Measures to Set Up 450mm Semiconductor Prototyping and to Keep Semiconductor Manufacturing in Europe: The role of Public Authorities and Programmes’ commissioned by the European Commission will be presented. The study puts forward three scenarios for Europe’s involvement in 450mm semiconductor manufacturing. 

Notes from ISS, January 2012, Half Moon Bay, CA:

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IRPS set for April in Anaheim


February 21, 2012

The IEEE International Reliability Physics Symposium (IRPS) is set for April 15, 2012 – April 19, 2012, in Anaheim, CA. The IRPS is celebrating 50 years of ground-breaking semiconductor physics of failure research. Covering advanced materials, 3D integration, product reliability, transistors and circuits, silicon/packaging interactions, MEMS, GaN, and photovoltaics, the technical program promises to bring attendees the latest in semiconductor reliability concerns. For more information and to register online, browse to http://www.irps.org.

In this three-part series, SEMATECH’s authors cover metrology for FinFETs (Part 1) and 3D memory devices, and defect detection capabilities at 22nm (Part 3). The series appears in the upcoming March 2012 issue of Solid State Technology, along with other metrology-focused pieces from KLA-Tencor and Entegris. Subscribe to Solid State Technology magazine here.

February 16, 2012 — The 22nm semiconductor node marks the beginning of a major transition from conventional scaling-driven planar devices to complex 3D transistor architectures, redefining future needs for lithographic, defect, and films metrology solutions for high-volume manufacturing. Future 3D memory devices will include multiple gate-level structures defined by high aspect ratio (HAR) trenches and holes in multilayer stacks, which are major gaps in current metrology technology. No in-line non-destructive metrologies have achieved the sensitivity and resolution to image or measure CD, depth, profile, or contamination of such HAR features [1]. In addition, defect metrology inspection and review suffer from low sensitivity and inadequate throughput even for current 22nm defects of interest. To address these challenges, a robust metrology strategy should encompass the extendibility of conventional techniques that are approaching their fundamental limits, as well as development of new technologies.

Memory producers are migrating beyond planar designs to build multiple levels of gates into 3D structures. These vertical architectures lead to new challenges in semiconductor processing technology [7]. As shown in Figure 2, the basic building blocks of these features are deep, HAR trenches and holes in oxide, silicon, or multiple alternating layers of oxide and silicon.

Figure 2. Left: Diagram of pipe-shaped bit cost scalable (P-BiCS) flash memory cell, which consists of pipe-shaped NAND strings folded in a U shape. This is an example of the types of 3D memory devices that will require HVM metrology. Right: Diagram of various measurement needs on such a structure.
Figure 2. Left: Diagram of pipe-shaped bit cost scalable (P-BiCS) flash memory cell, which consists of pipe-shaped NAND strings folded in a U shape. This is an example of the types of 3D memory devices that will require HVM metrology. Right: Diagram of various measurement needs on such a structure.

3D memory structures present many metrology challenges due to their HAR characteristics. HAR contact holes and trenches at ITRS half-pitch dimensions are known gaps in CD and profile metrology; these same measurement limitations have, to some extent, already been apparent with etched contact holes and shallow trench isolation (STI) trenches in logic for recent ITRS nodes. Furthermore, the problem is increasing with shrinking dimensions. HAR etching is difficult, with 30:1, 40:1, or even 60:1 ARs necessary to form a vertical circuit path among stacked gates.

Process control of the bottom of the CD, profile, and detection of polymeric etch residues is required for HVM. While TSVs may have a similar or higher AR, they are comparatively huge — 3D memory device features will include hole and trench structures with bottom CD sizes at ITRS node dimensions [8], from 0.5 to 2µm deep. This introduces an entirely new set of gaps in metrology capability as the quest for non-destructive measurements of such features has yet to achieve the necessary sensitivity and resolution. Moreover, the physics of these measurements is incompatible with the extremely deep and geometrically confined volumes involved.

Charged particle imaging techniques such as CD-SEM and helium ion microscopy (HeIM) [9] have sensitivity limitations arising from sidewall charging, as only a small fraction of scattered particles follow escape trajectories that reaches the detector. Many optical techniques, especially those that operate off-axis near the critical angle, suffer from a very small fraction of the interrogating light reaching the feature bottom, and reflect upwards to the detector. Thus, in most cases, the various metrology techniques in their present forms will suffer low signal-to-noise ratios (SNRs) on such features.

Many technologies are being explored at SEMATECH to enable HVM of HAR features, including new technologies such as critical dimension small angle X-ray spectroscopy (CD-SAXS) [3], HeIM [9], and through focus scanning optical microscopy (TSOM) [10] and variations of existing technologies, such as Mueller matrix [2] and normal incidence scatterometry (polarized reflectometry), model-based infrared reflectometry (MBIR), high voltage SEM (HV-SEM) [11], environmental SEM (e-SEM) [12], and conventional low-voltage CD-SEM. Results are still forthcoming, but CD-SAXS and scatterometry at normal incidence, MBIR, and HV-SEM may have some capability in this application space. CD-SAXS is currently a lab technique, but X-ray sources with higher brightness offer possibilities for transforming this technique into a feasible HVM metrology tool. MBIR takes advantage of the transparency of the various applicable materials to infrared and thus may have sensitivity to some feature aspects. HV-SEM is being demonstrated as useful in providing the capability to charge HAR holes in such a way that reflected incident or secondary electrons can more easily escape the bottom of the feature. Normal incidence scatterometry may be feasible as more incident light can reach the bottom for potentially improved SNR.

Conclusion, Part 2
Adaptation to new tool paradigms, enhancements of existing technologies, and productivity innovations will be critical to maintain process control and high yield in the coming technology generations. The SEMATECH Advanced Metrology Program is well positioned to develop solutions to address the measurement challenges of next generation devices.

Miss Part 1 on FinFET metrology? Read it here.

Move on to Part 3 on new defect detection technologies here.

References

[1] Doyle, B. et al., “Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout,” Symposium on VLSl Technology Digest of Technical Papers, pp. 133-134 (2003).

[2] Vaid, A., et al. “A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM.” Metrology, Inspection, and Process Control for Microlithography XXV. Proceedings of the SPIE, Volume 7971, pp. 797103-797103-20 (2011).

[3] Wang, C., Choi, K., Chen, Y. Price, J., Ho, D., Jones, R., Soles, C., Lin, E., Wu, W.L., Bunday, B. “Nonplanar high-k dielectric thickness measurements using CD-SAXS.” Proc. SPIE, v. 7272, pp 72722M (2009).

[4] De Martino, A., et al., “Comparison of Spectroscopic Mueller Polarimetry, Standard Scatterometry and Real Space Imaging Techniques (SEM and 3D-AFM) for Dimensional Characterization of Periodic Structures,” Proc. of SPIE Vol. 6922, 69221P (2008).

[5] Larson, D.J., and Kelly, T. F., “Nanoscale Analysis of Materials using a Local-Electrode Atom Probe,” Microscopy and Microanalysis Volume: 20, Issue: 3, pp: 59-62 (2006).

[6] Mody, J. et al., “Dopant and Carrier Profiling in FinFET-Based Devices with Sub-Nanometer Resolution,” 2010 Symposium on VLSI Technology, pp. 155-156

Abraham Arceo is a metrology development engineer at SEMATECH Advanced Metrology group. For the past three years he has been involved in film and defect inspection metrology development.

Benjamin Bunday is the project manager of CD Metrology and a Senior Member Technical Staff at SEMATECH (Albany, NY, USA). For ten years he has led SEMATECH/ISMI’s CD-SEM and OCD benchmarking, advanced CD technology evaluation and development efforts, and SEMATECH’s Advanced CD Metrology Advisory Group (AMAG).

Aaron Cordes is a research engineer for Sematech in Albany doing work on AFM, TEM, and focused ion beam metrology. He is also a PhD student with SUNY Albany’s College of Nanoscale Science and Engineering.

Victor Vartanian is a metrology engineer at SEMATECH in Albany, New York. Before coming to SEMATECH, he worked at Freescale Semiconductor in Austin, Texas, where he worked on applications of strained silicon to advanced transistor design and analytical applications of FTIR and mass spectrometry to environmental issues in semiconductor manufacturing and in process optimization.

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February 15, 2012 — IC manufacturers closed 49 wafer fabs between 2009 and 2011, according to a recent IC Insights’ Global Wafer Capacity 2011-2012 report. Smaller wafer fabs (≤200mm) suffered the most closures, and Japan and North America led the way.

Since mid-2007, the IC industry has been paring down older capacity (i.e., ≤200mm wafers), and this trend began to take hold in 2009. Some of the less-cost-effective small wafer fabs were refurbished to run larger wafers, or to produce non-IC products. This trend away from smaller-diameter wafer fabs will continue in coming years, especially as companies transition to fab-lite or fabless business models.

Most of the 2009-2011 fab closures were 150mm wafer fabs (43%). Fab closures by wafer size: 21 for 150mm, 13 for 200mm, 7 for 125mm, 5 for 300mm, and 3 for 100mm (Figure 1). With Qimonda going out of business in early 2009, its 300mm wafer fabs became the first of their kind to cease commercial operations.

Figure 1. Wafer fab closures 2009-2011, by wafer size. SOURCE: IC Insights.

Regionally, according to the Global Wafer Capacity 2011-2012 report, Japan and North America each saw 17 wafer fabs close, followed by Europe with 12 and South Korea with 3 (Figure 2). One of the wafer fab closures in Japan was a 300mm IC fab operated by Sony, which is being retrofitted and will return to service to produce image sensors for the company. The Qimonda wafer fab in Sandston, Virginia, was the only 300mm wafer fab closed in North American (2009) during this time.

Also read: New installed wafer capacity leader: Taiwan

A total of three 100mm wafer fabs were closed in the three-year span. These included fabs owned by DALSA in Bromont, Ontario, Canada; ON Semiconductor in Piestany, Slovak Republic; and Diodes in Oldham, England.

Figure 2. Wafer fab closures 2009-2011, by region. SOURCE: IC Insights.

IC Insights’ Global Wafer Capacity 2011-12 report features 78 pages and 61 charts/tables of IC wafer capacity analyses and forecasts along with two addendums: a 72-page addendum of 300mm wafer manufacturer profiles; and a 24-page addendum of detailed IC fab specifications. View http://www.icinsights.com/services/global-wafer-capacity/ for more information.

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February 15, 2012 — Tool obsolescence is increasingly important to semiconductor manufacturers running 200mm wafer fab lines, reports ISMI, semiconductor supply chain consortium. ISMI has chartered an Equipment Obsolescence Forum for alternative source solutions for wafer fabs and semiconductor fab equipment manufacturers.

The first forum meeting will be held May 21-22, in San Jose CA.

Replacement parts for 200mm equipment are scarce because the 200mm wafer size has lasted "well beyond its original life term." ISMI identified "a critical vulnerability" for these toolsets still in operation, said Bill Ross, Forum Chair at ISMI.

Also read: Secondary semiconductor equipment: Who’s using 200mm, 300mm tools

The new Equipment Obsolescence Forum will help the semiconductor industry identify and implement ways to locate and replace mission-critical parts. Device and equipment manufacturers will work with ISMI to develop an alternate supply chain for difficult to source or obsolete parts. Equipment manufacturers will come together to avoid equipment obsolescense through innovative ideas, and will examine the financial impact posed by tool obsolescence, and the rate at which it accelerates over time.

The Obsolescence Forum expands on ISMI’s extensive Alternate Parts Sourcing Database, which centralizes information about products and capabilities for voluntarily registered suppliers. It offers data on supplier types, locations, R&D capabilities,  repair and refurbishing availability, factory module and other focus areas.

For more information on ISMI’s Alternate Parts Sourcing Database or for general information on Equipment Obsolescence Forum workshops in 2012, contact Bill Ross, [email protected].

ISMI stands for International SEMATECH Manufacturing Initiative. SEMATECH is an international consortium of leading semiconductor device, equipment, and materials manufacturers. Information about SEMATECH can be found at www.sematech.org.

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February 14, 2012 — Lita Shon-Roy, senior managing partner, Techcet Group and Michael Fury, PhD, director of market development at Vantage Technology Corporation/Techcet and regular ElectroIQ blogger, will present "CMP Market Outlook & New Technology – Dynamic Slurry Metrology," a free webinar at 2 times on February 22, for US/Europe and Asia attendees.

Chemical mechanical planarization (CMP) consumables continue to outpace other electronics assembly materials in year-over-year growth. The market now totals $1.65 billion. Wafer sensitivity to scratching during the CMP process has increased, negatively impacting yields and requiring significant process improvements. One possible methodology to increase yields is continuous, real-time monitoring of particle counts in CMP slurry. Also read: CMP metrics improved by undiluted slurry data

The webinar will cover:

  • Trends in CMP technology development
  • Recent activity in CMP consumables supply chains
  • Preview of the 2012 CMP consumables market outlook
  • New metrology for continuous monitoring of undiluted slurry 
  • Experimental results correlating real-time particle counts with scratches

Two sessions are available for US/Europe and for Asia:
Wednesday, February 22, 2012 9-10AM PST
REGISTER: https://www4.gotomeeting.com/register/613362631

and 7-8PM PST REGISTER: https://www4.gotomeeting.com/register/726615639

Visit Techcet Group’s website to learn more: http://techcet.com/

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February 13, 2012 – MMD Newswire — RAVE N.P. Inc. established a new division, Advanced Technical Instruments or ATI, comprising SEM, AFM, and other analysis tools, as well as custom semiconductor and photomask services such as haze generation systems.

The new division was formed following RAVE’s acquisition of certain assets of the Lake Champlain operation of Applied Research Associates. ATI will be headquartered in Williston, VT. Brian Grenon will lead the new organization as business unit manager. Grenon’s experience is in analytical chemistry sciences, and research in photomask and semiconductor fields.

Core offerings include bio-medical, optical microscope and scientific instrumentation products and advanced analytical services:

  • high-resolution surface and material analysis including scanning electron microscopy (SEM), atomic force microscopy (AFM) and time-of-flight secondary ion mass spectrometry (TOF-SIMS).
  • custom services to the semiconductor and photomask industries such as haze generation systems and samples, enabling photo-induced defects in advanced wafer lithography study.

RAVE N.P., Inc. is a subsidiary of RAVE LLC. RAVE N.P. Inc. also runs the division ECO-SNOW SYSTEMS, which makes precision cryogenic surface process equipment for cleaning applications in the microelectronics industry. RAVE LLC is a global supplier of advanced process solutions to the semiconductor and photomask making industries.

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February 13, 2012 – Marketwire — Oscilloscope maker Tektronix Inc. donated semiconductor test and measurement equipment to Washington State University Vancouver. WSU Vancouver received arbitrary/function generations, a real-time spectrum analyzer, digital phosphor and mixed signal oscilloscopes, Keithley’s semiconductor parameter analyzers, and Fluke’s True-rms multimeters for its $43.5 million Engineering and Computer Science building.

WSU will name its Radio Frequency Research Laboratory and the Basic Electronics Laboratory for Tektronix through 2016.

The WSU Vancouver expansion is part of an economic development project to provide additional workforce-ready engineering graduates for companies in the local high-tech cluster. Students will have access to the same state-of-the-art tools as in the electronics industry, said Dr. Kevin Ilcisin, CTO, Tektronix, noting the growth of high-tech industries across the Pacific Northwest, where WSU is located.

WSU Vancouver received 24 AFG3011 arbitrary/function generators, a RSA3408B real-time spectrum analyzer, a DPO70404C oscilloscope, 5 DPO 2024 oscilloscopes, a MSO3054 mixed signal oscilloscope, two Keithley 4200-SCS Semiconductor Parameter Analyzers, and three Fluke 87V True-rms Multimeters. In addition, WSU Vancouver purchased 19 more DPO2024 oscilloscopes along with 60 PWS2000 Series DC power supplies, supporting accessories and other equipment.

WSU Vancouver has an enrollment of more than 3,000 students. Learn about the school at vancouver.wsu.edu.

Tektronix provides test, measurement and monitoring solutions to solve design challenges, improve productivity and dramatically reduce time to market. Tektronix is a leading supplier of test equipment for engineers focused on electronic design, manufacturing, and advanced technology development. Internet: www.tektronix.com.

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The March 2012 issue of Solid State Technology will feature "450mm wafer transition" from Dr. Brian Trafas, chief marketing officer at KLA-Tencor Inc. (KLAC). Sign up for Solid State Technology here to receive your digital edition. The following is a sneak preview of Dr. Trafas’ article:

The semiconductor industry’s wafer size transition from 300mm to 450mm promises higher yields, with more die per wafer. While 450mm will eventually lower die costs for semiconductor manufacturers, it will not happen without higher die yields. Advanced design rules, increased chip density, new immature process tools, tighter process windows, center-to-edge process variations and wafer edge defects all threaten the promised benefits of 450mm wafer fab. Process control will be critical.

Looking towards the 2018-2019 timeframe, the industry will be well into production at technology nodes smaller than 1X nanometer, furthering industry concern around the right time to move forward with significant R&D investment in 450mm production.

Read more in "Yield challenges & the 450mm learning curve" debuting in the March issue of Solid State Technology. The March issue features other metrology & test articles:

Packaging: Improved copper wire bonding
Bruker authors share how a 3D optical microscope was used in imprint studies aimed at process optimization and sampling.

Evolution or Revolution: Metrology beyond 22nm
SEMATECH investigates the metrology challenges of future nodes, including FinFETs.

Gas purification development
Entegris discusses metrology-aided gas purification for semiconductor chip manufacturing.

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