Category Archives: Metrology

The latest update to the SEMI World Fab Forecast report, published on February 28, 2018, reveals fab equipment spending will increase at 5 percent in 2019 for a remarkable fourth consecutive year of growth as shown in figure 1. China is expected to be the main driver of fab equipment spending growth in 2018 and 2019 absent a major change in its plans. The industry had not seen three consecutive years of growth since the mid-1990s.

Figure 1

Figure 1

SEMI predicts Samsung will lead in fab equipment spending both in 2018 and 2019, with Samsung investing less each year than in 2017.  By contrast, China will dramatically increase year-over-year fab equipment spending by 57 percent in 2018 and 60 percent in 2019 to support fab projects from both multinationals and domestic companies. The China spending surge is forecast to accelerate it past Korea as the top spending region in 2019.

After record investments in 2017, Korea fab equipment spending will decline 9 percent, to US$18 billion, in 2018 and an additional 14 percent, to US$16 billion, in 2019. However both years will outpace pre-2017 spending levels for the region. Fab equipment spending in Taiwan, the third-largest region for fab investments, will fall 10 percent to about US$10 billion in 2018, but is forecast to rebound 15 percent to over US$11 billion in 2019. (Details about other regions’ spending trends are available in SEMI’s latest World Fab Forecast.)

As expected, China’s fab equipment spending is increasing as projects shift to equipment fabs constructed earlier in this cycle.  The record 26 volume fabs that started construction in China in 2017 will begin equipping this year and next.  See figure 2.

Figure 2

Figure 2

Non-Chinese companies account for the largest share of fab equipment investment in China. However, Chinese-owned companies are expected to ramp up fabs in 2019, increasing their share of spending in China from 33 percent in 2017 to 45 percent in 2019.

Product Sector Spending

3D NAND will lead product sector spending, growing 3 percent each in 2018 and 2019, to US$16 billion and US$17 billion, respectively. DRAM will see robust growth of 26 percent in 2018, to US$14 billion, but is expected to decline 14 percent to US$12 billion in 2019.  Foundries will increase equipment spending by 2 percent to US$17 billion in 2018 and by 26 percent to US$22 billion in 2019, primarily to support 7nm investments and ramp of new capacity.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $37.6 billion for the month of January 2018, an increase of 22.7 percent compared to the January 2017 total of $30.6 billion. Global sales in January were 1.0 percent lower than the December 2017 total of $38.0 billion, reflecting normal seasonal market trends. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“After notching its highest-ever annual sales in 2017, the global semiconductor industry is off to a strong and promising start to 2018, posting its highest-ever January sales and 18th consecutive month of year-to-year sales increases,” said John Neuffer, president and CEO, Semiconductor Industry Association. “All major regional markets saw double-digit growth compared to last year, with the Americas leading the away with year-to-year growth of more than 40 percent. With year-to-year sales also up across all major semiconductor product categories, the global market is well-positioned for a strong start to 2018.”

Year-to-year sales increased substantially across all regions: the Americas (40.6 percent), Europe (19.9 percent), Asia Pacific/All Other (18.6 percent), China, (18.3 percent), and Japan (15.1 percent). Month-to-month sales increased slightly in Europe (0.9 percent), held flat in China, but fell somewhat in Asia Pacific/All Other (-0.6 percent), Japan (-1.0 percent), and the Americas (-3.6 percent).

To find out how to purchase the WSTS Subscription Package, which includes comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, please visit http://www.semiconductors.org/industry_statistics/wsts_subscription_package/. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook: https://www.semiconductors.org/forms/sia_databook/.

Jan 2018

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

8.95

8.63

-3.6%

Europe

3.37

3.40

0.9%

Japan

3.24

3.21

-1.0%

China

12.01

12.01

0.0%

Asia Pacific/All Other

10.41

10.35

-0.6%

Total

37.99

37.59

-1.0%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

6.14

8.63

40.6%

Europe

2.84

3.40

19.9%

Japan

2.79

3.21

15.1%

China

10.16

12.01

18.3%

Asia Pacific/All Other

8.73

10.35

18.6%

Total

30.64

37.59

22.7%

Three-Month-Moving Average Sales

Market

Aug/Sep/Oct

Nov/Dec/Jan

% Change

Americas

8.54

8.63

1.1%

Europe

3.36

3.40

1.1%

Japan

3.20

3.21

0.3%

China

11.65

12.01

3.1%

Asia Pacific/All Other

10.33

10.35

0.1%

Total

37.09

37.59

1.4%

Enabling further advancements in metrology, HEIDENHAIN CORPORATION recently donated some equipment to UNC Charlotte’s Center for Precision Metrology (CPM), a world premier university metrology lab.

As part of the UNC Charlotte William States Lee College of Engineering, the Metrology Lab is central to the education and research efforts in the areas of precision engineering and metrology, and includes a wide variety of high-end measurement instruments. Providing measurement research support to the University community and local industry, and already equipped with a HEIDENHAIN KGM grid plate, the HEIDENHAIN donation of a new EIB interface box with cabling and ACCOM software is allowing important upgrades to be realized to the system.

“At UNC Charlotte, the HEIDENHAIN KGM grid encoder is used to demonstrate the measurement of dynamic machine tool errors to the graduate class in Machine Tool Metrology utilizing the ISO230 standard series,” explained CPM Chief Engineer Dr. Jimmie Miller. “As far as R&D with this equipment, other plans involve its utilization by directly connecting to research machine encoders to assess the machine multi-axis position and control. This will enable us to move the assessment metrology loop outside of the control loop for a faster non-interfering independent evaluation.

“The generous support of companies like HEIDENHAIN supporting education and R&D allows us to continue to maintain the CPM capabilities at the state-of-the-art level by utilizing today’s top technologies such as the donated HEIDENHAIN interface equipment and software,” stated Dr. Miller.

Interface electronics from HEIDENHAIN adapt the encoder signals to the interface of the subsequent electronics. They are used when the subsequent electronics cannot directly process the output signals from HEIDENHAIN encoders, or if additional interpolation of the signals is necessary.  Because of their high IP 65 degree of protection, interface electronics with a box design are well suited for a rough industrial environment, for example where machine tools operate. The inputs and outputs are equipped with robust M23 and M12 connecting elements. The stable cast-metal housing offers protection against physical damage as well as against electrical interference.

 

Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2018.

Enabling the AI Era with Materials Engineering

Screen Shot 2018-03-05 at 12.24.49 PMPrabu Raja, Senior Vice President, Semiconductor Products Group, Applied Materials

A broad set of emerging market trends such as IoT, Big Data, Industry 4.0, VR/AR/MR, and autonomous vehicles is accelerating the transformative era of Artificial Intelligence (AI). AI, when employed in the cloud and in the edge, will usher in the age of “Smart Everything” from automobiles, to planes, factories, buildings, and our homes, bringing fundamental changes to the way we live

Semiconductors and semiconductor processing technol- ogies will play a key enabling role in the AI revolution. The increasing need for greater computing perfor- mance to handle Deep Learning/Machine Learning workloads requires new processor architectures beyond traditional CPUs, such as GPUs, FPGAs and TPUs, along with new packaging solutions that employ high-density DRAM for higher memory bandwidth and reduced latency. Edge AI computing will require processors that balance the performance and power equation given their dependency on battery life. The exploding demand for data storage is driving adoption of 3D NAND SSDs in cloud servers with the roadmap for continued storage density increase every year.

In 2018, we will see the volume ramp of 10nm/7nm devices in Logic/Foundry to address the higher performance needs. Interconnect and patterning areas present a myriad of challenges best addressed by new materials and materials engineering technologies. In Inter- connect, cobalt is being used as a copper replacement metal in the lower level wiring layers to address the ever growing resistance problem. The introduction of Cobalt constitutes the biggest material change in the back-end-of-line in the past 15 years. In addition to its role as the conductor metal, cobalt serves two other critical functions – as a metal capping film for electro- migration control and as a seed layer for enhancing gapfill inside the narrow vias and trenches.

In patterning, spacer-based double patterning and quad patterning approaches are enabling the continued shrink of device features. These schemes require advanced precision deposition and etch technologies for reduced variability and greater pattern fidelity. Besides conventional Etch, new selective materials removal technologies are being increasingly adopted for their unique capabilities to deliver damage- and residue-free extreme selective processing. New e-beam inspection and metrology capabilities are also needed to analyze the fine pitch patterned structures. Looking ahead to the 5nm and 3nm nodes, placement or layer-to-layer vertical alignment of features will become a major industry challenge that can be primarily solved through materials engineering and self-aligned structures. EUV lithography is on the horizon for industry adoption in 2019 and beyond, and we expect 20 percent of layers to make the migration to EUV while the remaining 80 percent will use spacer multi- patterning approaches. EUV patterning also requires new materials in hardmasks/underlayer films and new etch solutions for line-edge-roughness problems.

Packaging is a key enabler for AI performance and is poised for strong growth in the coming years. Stacking DRAM chips together in a 3D TSV scheme helps bring High Bandwidth Memory (HBM) to market; these chips are further packaged with the GPU in a 2.5D interposer design to bring compute and memory together for a big increase in performance.

In 2018, we expect DRAM chipmakers to continue their device scaling to the 1Xnm node for volume production. We also see adoption of higher perfor- mance logic technologies on the horizon for the periphery transistors to enable advanced perfor- mance at lower power.

3D NAND manufacturers continue to pursue multiple approaches for vertical scaling, including more pairs, multi-tiers or new schemes such as CMOS under array for increased storage density. The industry migration from 64 pairs to 96 pairs is expected in 2018. Etch (high aspect ratio), dielectric films (for gate stacks and hardmasks) along with integrated etch and CVD solutions (for high aspect ratio processing) will be critical enabling technologies.

In summary, we see incredible inflections in new processor architectures, next-generation devices, and packaging schemes to enable the AI era. New materials and materials engineering solutions are at the very heart of it and will play a critical role across all device segments.

BY AJIT MANOCHA, President and CEO of SEMI

2017 was a terrific year for SEMI members. Chip revenues closed at nearly $440B, an impressive 22 percent year- over-year growth. The equipment industry surpassed revenue levels last reached in the year 2000. Semicon- ductor equipment posted sales of nearly $56B and semiconductor materials $48B in 2017. For semiconductor equipment, this was a giant 36 percent year-over-year growth. Samsung, alone, invested $26B in semiconductor CapEx in 2017 – an incredible single year spend in an incredible year.

MEMS and Sensors gained new growth in telecom and medical markets, adding to existing demand from automotive, industrial and consumer segments. MEMS is forecast to be a $19B industry in 2018. Flexible hybrid electronics (FHE) is also experiencing significant product design and functionality growth with increasing gains in widespread adoption.

No longer isa single monolithic demand driver propelling the electronics manufacturing supply chain. The rapidly expanding digital economy continues to foster innovation with new demand from the IoT, virtual and augmented reality (VR/AR), automobile infotainment and driver assistance, artificial intelligence (AI) and Big Data, among others. With the explosion in data usage, memory demand is nearly insatiable, holding memory device ASPs high and prompting continued heavy investment in new capacity.

2018 is forecast to be another terrific year. IC revenues are expected to increase another 8 percent and semiconductor equipment will grow 11 percent. With diverse digital economy demand continuing, additional manufacturing capacity is being added in China as fab projects come on line to develop and increase the indigenous semiconductor supply chain.

So, why worry?

The cracks starting to show are in the areas of talent, data management, and Environment, Health, and Safety (EH&S).

Can the industry sustain this growth? The electronics manufacturing supply chain has demonstrated it can generally scale and expedite production to meet the massive new investment projects. The cracks starting to show are in the areas of talent, data management, and Environment, Health, and Safety (EH&S).

Talent has become a pinch point. In Silicon Valley alone, SEMI member companies have thousands of open positions. Globally, there are more than 10,000 open jobs. Attracting new candidates and developing a global workforce are critical to sustaining the pace of innovation and growth.
Data management and effective data sharing are keys to solving problems faster and making practical novel but immature processes at the leading edge. It is ironic that other industries are ahead of semiconductor manufac- turing in harnessing manufacturing data and leveraging AI across their supply chains. Without collaborative Smart Data approaches, there is jeopardy of decreasing the cadence of Moore’s Law below the 10 nm node.

EH&S is critical for an industry that now uses the majority of the elements of the periodic table to make chips – at rates of more than 50,000 wafer starts per month (wspm) for a single fab. The industry came together strongly in the 1990s to develop SEMI Safety Standards and compliance methodologies. Since then, the number of EH&S profes- sionals engaged in our industry has declined while the number of new materials has exploded, new processing techniques have been developed, and manufacturing is expanding across China in areas with no prior semicon- ductor manufacturing experience.

HTU has been a very effective program with over 218 sessions run to date, over 7,000 students engaged, and over 70 percent of respondents pursuing careers in the STEM field.

To ensure we don’t slow growth, the industry will need to work together in 2018 in these three key areas:

Talent development needs to rapidly accelerate by expanding currently working programs and adding additional means to fill the talent funnel. The SEMI Foundation’s High Tech University (HTU) works globally with member companies to increase the number of high school students selecting Science, Technology, Engineering, and Math (STEM) fields – and provides orientation to the semiconductor manufacturing industry. HTU has been a very effective program with over 218 sessions run to date, over 7,000 students engaged, and over 70 percent of respondents pursuing careers in the STEM field. SEMI will increase the number of HTU sessions in 2018.

Plans have already been approved by SEMI’s Board of Directors to work together with SEMI’s membership to leverage existing, and pioneer new, workforce development programs to attract and develop qualified candidates from across the age and experience spectrum (high school through university, diversity, etc.). Additionally, an industry awareness campaign will be developed and launched to make more potential candidates attracted to our member companies as a great career choice. I’ll be providing you with updates on this initiative – and asking for your involvement
– throughout 2018.

Data management is a broad term. Big Data, machine learning, AI are terms that today mean different things to different people in our supply chain. What is clear is that to act together and take advantage of the unimaginable amounts of data being generating to produce materials and make semiconductor devices with the diverse equipment sets across our fabs, we need a common understanding of the data and potential use of the data.

In 2018, SEMI will launch a Smart Data vertical application platform to engage stakeholders along the supply chain to produce a common language, develop Standards, and align expectations for sharing data for mutual benefit. Bench- marking of other industries and pre-competitive pilot programs are being proposed to learn and, here too, we need the support and engagement of thought leaders throughout SEMI’s membership.

EH&S activity must intensify to maintain safe operations and to eliminate business interruptions from supply chain disruptions. There is potential for disruptions from material bans such as the Stockholm Convention action on PFOA and arising from the much wider range of chemicals and materials being used in advanced manufacturing. Being able to reliably identify these in time to guide and coordinate industry action will take a reinvigorated SEMI EH&S stewardship and membership engagement.

As China rapidly develops new fabs in many provinces – some with only limited prior experience and infrastructure – SEMI EH&S Standards orientation and training will accelerate the safe and sustainable operation of fabs, enabling them to keep pace with the ambitious growth trajectory our industry is delivering. In 2018, we’ll be looking for a renewed commitment to EH&S and sustainability for the budding challenges of new materials, methods, and emerging regions.

Remarkable results from a remarkable membership

Thank you all for a terrific 2017 and let’s work together on the key initiatives to ensure that our industry’s growth and prosperity will continue in 2018 and beyond.

In a quick review of 2017, I would like to thank SEMI’s members for their incredible results and new revenue records. Foundational to that, SEMI’s members have worked together with SEMI to connect, collaborate, and innovate to increase growth and prosperity for the industry. These founda- tional contributions have been in expositions, programs, Standards, market data, messaging (communications), and workforce development (with HTU).

The infographic below captures these foundational accom- plishments altogether. SEMI strives to speed the time to better business results for its members across the global electronics manufacturing supply chain. To do so, SEMI is dependent upon, and grateful for, the support and volunteer efforts of its membership. Thank you for a terrific 2017 and let’s work together on the key initiatives to ensure that our industry’s growth and prosperity will continue in 2018 and beyond.

BY SYAHIRAH MD ZULKIFLI, BERNICE ZEE AND WEN QIU, Advanced Micro Devices, Singapore; ALLEN GU, ZEISS, Pleasanton, CA

3D integration and packaging has challenged failure analysis (FA) techniques and workflows due to the high complexity of multichip architectures, the large variety of materials, and small form factors in highly miniaturized devices [1]. The drive toward die stacking with High Bandwidth Memory (HBM) allows the ability to move higher bandwidth closer to the CPU and offers an oppor- tunity to significantly expand memory capacity and maximize local DRAM storage for high throughput in the data center. However, the integration of HBM results in more complex electrical communications, due to the emerging use of a physical layer (PHY) design to connect the chip and subsystems. FIGURE 1 shows the schematic of a 2.5D stacked die package designed so that some HBM μbumps are electrically connected to the main CPU through a PHY connection. In general, the HBM and CPU signal length needs to be minimized to reduce drive strength requirements and power consumption at the PHY.

Screen Shot 2018-03-01 at 11.46.34 AM

This requirement poses new challenges in FA fault isolation. A traditional FA workflow using electrical fault isolation (EFI) techniques to isolate the defect becomes less effective for chip-to-chip interconnects because there are no BGA balls for electrically probing the μbumps at the PHY. As a result, new defect localization techniques and FA flows must be investigated.

XRM theory

X-ray imaging is widely employed for non-destructive FA inspection because it can explore interior structures of chips and packages, such as solder balls, silver paste and lead frames. Thus, many morphological failures, such as solder-ball crack/burn-out and bumping failure inside IC packages, can be imaged and analyzed through X-ray tools. In 2D X-ray inspection, an X-ray irradiates samples and a 2D detector utilizes the projection shadow to construct 2D images. This technique, however, is not adequate for revealing true 3D structures since it projects 3D structures onto a 2D plane. As a result, important information, such as internal faulty regions of electronic packages, may remain hidden. This disadvantage can be overcome by using 3D X-ray microscopic technology, derived from the original computed tomography (CT) technique. In a 3D imaging system, a series of 2D X-ray images are captured at different angles while a sample rotates.

These 2D images are used to reconstruct 3D X-ray tomographic slices using mathematic models and algorithms. The spatial resolution of the imaging technique can be improved through the integration of an optical microscopy system. This improved technology is called 3D X-ray microscopy (XRM) [2]. FIGURE 2 shows an example 3D XRM image for a stacked die. The image clearly shows the internal structures – including the TSV, C4 bumps and μbump of the electronic components – without physically damaging or altering the sample. The high resolution and quality shown here are essential to inspect small structural defects inside electronic devices. With its non-destructive nature, 3D XRM has been useful for non-destructive FA for IC packaging devices.

Screen Shot 2018-03-01 at 11.46.42 AM

Failure analysis approach

The purpose of an FA workflow is to have a sequence of analytical techniques that can help to effectively and quickly isolate the failure and determine the root cause. Typical FA workflows for flip-chip devices consist of non-destructive techniques such as C-Mode scanning acoustic microscopy (C-SAM) and time domain reflectometry (TDR) to isolate the failure, followed by destructive physical failure analysis (PFA). However, there are limitations to each of these techniques when posed with the failure analysis of a more complex stacked die package.

C-SAM allows the inspection of abnormal bumps, delamination and any mechanical failure. A focused soundwave is directed from a transducer to a small point on a target object and is reflected when it encounters a defect, inhomogeneity or a boundary inside the material. The transducer transforms the reflected sound pulses into electromagnetic pulses, which are displayed as pixels with defined grey values thereby creating an image [3]. However, stacked die composed of a combination of multiple thin layers may complicate C-SAM analysis. This is because the thin layers have smaller spacing between the adjacent interface, and shorter delay times for ultrasound traveling from one interface to another. Therefore, failures between the die and die attach may not be easily detected, and false readings may even be expected.

TDR is an electrical fault isolation tool that enables failure localization through electrical signal data. The TDR signal carries the impedance load information of electrical circuitry; hence, the reflected signals show the discontinuity location that has caused the mismatch of impedance. In-depth theory on TDR is further discussed in Chin et al [4]. However, TDR can only estimate where the failure lies, whether it is in the substrate, die or interposer region. To pin point the exact location within the area of failure is difficult, due to limitations in separating the various small structures through the TDR signal. Additionally, some of the pulse power is reflected for every impedance change, posing challenges regarding unique defect isolation and signal complexity – especially for stacked die [5]. In cases where the failure pins reside in the HBM μbump region, no BGA ball out is available to probe and send an electrical pulse through.

Physical Failure Analysis (PFA) is a destructive method to find and image the failure once non-destructive fault isolation is complete. PFA can be done both mechanically and by focused ion beam (FIB). For stacked dies, FIB is predominantly used to image smaller interconnect structures such as TSVs and μbumps. However, the drawback is that the success of documenting the failure through PFA is largely dependent on how well the non-destructive FA techniques can isolate the failure region. Without good clear fault isolation direction, the failure region might be destroyed or missed during the PFA process, and thus no root cause can be derived.

The integration of XRM into the FA flow can help to overcome the limitations of the various analysis techniques to isolate the failure. It is a great advantage to image small structures and failures with the high spatial resolution and contrast provided by XRM and without destroying the sample. For failures in stacked die, XRM can be integrated into the FA flow for further fault isolation with high accuracy. The visualization of defects and failed material prior to destructive analysis increases FA success rates. However, the trade-off for imaging small defects at high resolution is time. For stacked die failures, C-SAM and TDR can first be performed to isolate the region of failure. With a known smaller region of interest to focus on, the time taken for XRM to visualize the area at high resolution is significantly reduced.

In cases where failures are identified in the HBM μbump, XRM is an effective technique to isolate the failure through 3D defect visualization. With the failure region isolated, XRM can then act as a guide to perform further PFA. Following are three case studies where XRM was used to image HBM packages with stacked dies.

Case studies

In the first case study, we explore the application of XRM as the primary means of defect visualization where other non-destructive testing and FA techniques are not possible. An open failure was reported for non-underfilled stacked die packages during a chip package interaction (CPI) study. The suspected open location was within the μbump joints at the HBM stack/ interposer interface. The initial approach exposed the bottom-most die of the HBM stack, followed by FIB cross-sectioning at the specified location. Performing the destructive approach to visualize the integrity of μbump joints in non-underfilled stack die packages was virtually impossible due to the fragility of silicon. The absence of underfill (UF) means that the HBM does not properly adhere to the interposer and is susceptible to peel off. In addition, there was no medium to release shear stresses experienced by the μbump joints upon bending stresses, which could not be absorbed by the package. As seen in FIGURE 3, parallel lapping of the HBM stack without UF caused die crack and peeling.

Screen Shot 2018-03-01 at 11.46.50 AM

Consequently, to avoid aggravating the damage on the sample, 3D XRM was performed to inspect and visualize the suspected location using a 0.7μm/voxel and 4X objective without any sample preparation. FIGURE 4 shows an example virtual slice where the micro-cracks throughout the row of μbump joints are visualized. The micro-cracks are measured a few microns wide. It is worth noting that the micro-cracks were visible with a short scan time of 1.5 hrs.

Screen Shot 2018-03-01 at 11.47.00 AM

With the critical defect information in 3D, PFA was performed on a sample that was underfilled to facilitate ease of sample preparation. SEM images in FIGURE 5 validated the existence of μbump micro-cracks observed by 3D XRM inspection.

In the second case study, the 3D XRM technique was applied to a stacked die package with a failure at a specific HBM/XPU physical interface (PHY) μbump connection. This μbump connection provides specific communication between the HBM stack and XPU die, and there is no package BGA ball out to enable electrical probing. Accordingly, it was not possible to verify if the failure type was an open or short. In addition, there was no means to determine if the failure was at the HBM or XPU die. Since defects from previous lots were open failures at the PHY μbump of the HBM, 3D XRM was performed at the suspected HBM open region using a 0.85μm/voxel and 4X objective.

As no defect was observed, XRM was then applied to the corresponding XPU PHY μbump. Contrary to the anticipated μbump open, a short was observed between two μbumps as shown in FIGURES 6a and 6b.

Screen Shot 2018-03-01 at 11.47.22 AM Screen Shot 2018-03-01 at 11.47.28 AM

 

The μbump short resulted from a solder extrusion bridging two adjacent μbumps. If 3D XRM had not been performed, a blind physical cross-section likely would have been performed on the initially suspected open region. As a result, the actual failure region may have been missed and/or destroyed.

In the final case study, an open failure was reported at a signal pin of a stack die package. As per the traditional FA flow, C-SAM and TDR techniques were applied to isolate the fault. C-SAM results showed an anomaly, and TDR suggested an open in the substrate as demonstrated in FIGURE 7a and 7b respectively.

Screen Shot 2018-03-01 at 11.47.10 AM Screen Shot 2018-03-01 at 11.47.16 AM

To verify the observations made by C-SAM and TDR non-destructive techniques, 3D XRM was performed using a 0.80μm/voxel and 4X objective at the region of

FIGURE 8 revealed a crack between the failure C4 bump and associated TSV. A physical cross-section was performed and the passivation cracks between the TSV and interposer backside redistribution layer (RDL) was observed as shown in FIGURE 9.

Screen Shot 2018-03-01 at 11.47.35 AM

In this case, 3D XRM provided 3D information for the FA engineer to focus on. Without the visual knowledge on the defect’s nature and location, the defect would have been missed during PFA.

Summary and conclusions

3D integration and packaging have brought about new challenges for effective defect localization, especially when traditional electrical fault isolation is not possible. 3D XRM enables 3D tomographic imaging of internal structures in chips, interconnects and packages, providing 3D structural information of failure areas without the need to destroy the sample. 3D XRM is a vital and powerful tool that helps failure analysis engineers to overcome FA challenges for novel 3D stacked-die packages.

Acknowledgement

This article is based on a paper that was presented at the 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2017).

References

  1. F. Altmann and M. Petzold, “Innovative Failure Analysis Techniques for 3-D Packaging Developments,” IEEE Design & Test, Vol. 33, No. 3, pp. 46-55, June 2016.
  2. C. Y. Liu, P. S. Kuo, C. H. Chu, A. Gu and J. Yoon, “High resolution 3D X-ray microscopy for streamlined failure analysis workflow,” 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2016, pp. 216-219.
  3. M. Yazdan Mehr et al., “An overview of scanning acoustic microscope, a reliable method for non-destructive failure analysis of microelectronic components,” 2015 16th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro- electronics and Microsystems, Budapest, 2015, pp.1-4.
  4. J. M. Chin et al., “Fault isolation in semiconductor product, process, physical and package failure analysis: Importance and overview,” Microelectronics Reliability, Vol. 51, Issue 9, pp. 1440-8, Nov. 2011.
  5. W. Yuan et al., “Packaging Failure Isolation with Time-Domain Reflectometry (TDR) for Advanced BGA Packages,” 2007 8th International Conference on Electronic Packaging Technology, Shanghai, 2007, pp. 1-5.

The top five semiconductor metrology/inspection equipment vendors grew 17.7% in 2017 according to the report “Metrology, Inspection, and Process Control in VLSI Manufacturing”, recently published by The Information Network, (www.theinformationnet.com) a New Tripoli, PA-based market research company.

The top three metrology/inspection suppliers were KLA-Tencor, Applied Materials Hitachi High Tech, Nanometrics, and Rudolph Technologies. These five companiesincreased their collective share of the overall global market to 87.0% in 2017, up from 82.4% in 2016.

metrology market

The report covers 27 different sectors and subsectors. With its large market share, KLA-Tencor led most of the sectors and subsectors. Applied Materials led the Defect Review Sector, Hitachi High Tech led the CD Inspection sector, Nanometrics held a large share of the Thin Film Metrology Sector, and Rudolph Technology led the Back-End Inspection market.

China and memory (DRAM and 3D NAND) are currently driving demand for the global wafer fab equipment market.

Orders for KLA-Tencor equipment from native Chinese customers nearly tripled in 2017 and this strong momentum is expected to continue into 2018.

China continues to be a strong focus for Rudolph Technologies. Revenue from China has more than doubled in the last two years. Rudolph’s revenue from advanced memory applications in both three DRAM and 3D NAND grew by 80% year-over-year as customers in Korea increased capacity to meet growing global demand for advanced memory used in cloud computing and mobile applications.

North America-based manufacturers of semiconductor equipment posted $2.36 billion in billings worldwide in January 2018 (three-month average basis), according to the January Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.  The billings figure is 1.4 percent lower than the final December 2017 level of $2.40 billion, and is 27.2 percent higher than the January 2017 billings level of $1.86 billion.

“The strong billings levels from late 2017 have carried over into the new year,” said Ajit Manocha, president and CEO of SEMI. “We maintain a positive outlook for the 2018 market, marking three years of growth for equipment spending.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)
Year-Over-Year
August 2017
$2,181.8
27.7%
September 2017
$2,054.8
37.6%
October 2017
$2,019.3
23.9%
November 2017
$2,052.3
27.2%
December 2017 (final)
$2,398.4
28.3%
January 2018 (prelim)
$2.364.8
27.2%

Source: SEMI (www.semi.org), February 2018
SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

Super Micro Computer, Inc. (NASDAQ: SMCI) today announced that it has expanded its Silicon Valley Headquarters to over two million square feet of facilities with the grand opening of its new Building 22.

The Corporate Headquarters includes engineering, manufacturing and customer service making Supermicro the only Tier 1 systems vendor to build its servers in Silicon Valley and worldwide.  Supermicro is ranked as the third largest server systems supplier in the world (Source: IDC).  In addition to the branded solution business used in the ranking, Supermicro also services large OEM and system integrator customers and shipped over 1.2 million units in 2017.

This latest building is the second of five facilities that the company plans to build on the 36-acre property formerly owned by the San Jose Mercury News. Additionally, the company continues to expand its other facilities worldwide.

“Having our design, engineering, manufacturing and service teams all here at our Silicon Valley campus gives Supermicro the agility to quickly respond to the newest technologies in the industry and to our customer’s needs and unique requirements, which is a major advantage that we have over the competition,” said Charles Liang, President and CEO of Supermicro.  “As our business continues to rapidly scale with over 1.2 million server and storage systems shipped globally last year, increasing our production capacity and capabilities is vital to keeping up with our rapid growth.  The opening of Building 22, along with the opening of two new facilities at our technology campus in Taiwan, provides the additional capacity and rack scale integration plug and play capabilities to ensure that we can provide the best possible service to our enterprise, datacenter, channel and cloud customers.”

“We’re thrilled to see an innovative, sustainable, and community-minded leader like Supermicro continuing to invest and grow in San Jose, and we look forward to their continued success now and for years to come!” said San Jose Mayor Sam Liccardo.

“The Corporation for Manufacturing Excellence – Manex would like to congratulate Supermicro for its continued growth through design and engineering excellence,” said Gene Russell, President and CEO of Manex.  “Its investments in workforce, physical plant and equipment are crucial to the Silicon Valley Ecosystem and to its global client base.  Manex, as a network member of the NIST Manufacturing Extension Partnership and the CMTC California network is a proud partner of Supermicro.”

Working closely with key partners like Intel, Supermicro leverages its strength in design and engineering to lead the way with first-to-market server and storage technology innovations. The company offers the industry’s broadest portfolio of advanced server and storage solutions including the popular BigTwin™ and SuperBlade® product lines and provides rack scale integration with rack plug and play capabilities.

Entering 2018 on solid ground


February 22, 2018

By Walt Custer, Custer Consulting Group

2017 finished on an upturn – both in the USA and globally.  Based on consolidated fourth-quarter actual and estimated revenues of 213 large, global electronic manufactures, sales rose in excess of 7 percent in 4Q’17 vs. 4Q’16 (Chart 1).  This was the highest global electronic equipment sales growth rate since the third quarter of 2011. Because some companies in our sample didn’t close their financial quarter until the end of January, final results will take a few more weeks – but all evidence points to a very strong fourth quarter of last year.

Custer1-Electronic-Equipment

 

Using regional (country specific) data (Chart 2), the normal, consumer electronics driven seasonal downturn began again in January.  However the recent year-over-year growth is still substantial.  On a total electronic equipment revenue basis, January 2018 was up almost 19.5 percent over January 2017.

Custer2-World-Electronic

Because this regional data in local currencies was converted to U.S. dollars at fluctuating exchange, the dollar denominated-growth was amplified by currency exchange effects.  At constant exchange the January growth was only 14 percent.   That is, when the stronger non-U.S. currencies were converted to weakening dollars, the dollar-denominated January 2018 fluctuating exchange growth was amplified by 5.5 percent.

Chart 3 shows 4Q’17/4Q’16 growth of the domestic electronic supply chain.  U.S. electronic equipment shipments were up 9.1 percent.  Only computer equipment and non-defense aircraft sales declined in the fourth quarter.  And of note, SEMI equipment shipments to North America rose almost 31 percent!

Custer3-US-Electronic-Supply

 

Chart 4 shows estimated fourth-quarter growth for the world electronic supply chain.  Only “Business & Office” equipment revenues declined in 4Q’17 vs. 4Q’16.

Custer4-Global-Electronic

Total global electronic equipment sales increased more than 7 percent in the fourth quarter and SEMI equipment revenues rose 32 percent.

2017 was a strong year and 2018 is off to a good start!  The 2017 lofty growth rates will temper, but this current expansion will likely continue.  Watch the monthly numbers!

Originally published on the SEMI blog.