Category Archives: Metrology

Fujitsu Semiconductor Limited and ON Semiconductor (Nasdaq: ON) today announced an agreement that ON Semiconductor will purchase a 30 percent incremental share of Fujitsu’s 8-inch wafer fab in Aizu-Wakamatsu, resulting in 40 percent ownership when the purchase is completed. The purchase is scheduled to be completed on April 1, 2018, subject to certain regulatory approvals and other closing conditions.

The two companies entered into an agreement in 2014, under which ON Semiconductor obtained a 10 percent ownership interest in Fujitsu’s Aizu 8-inch fab. Initial transfers began in 2014, and successful production and ramp-up of wafers began in June 2015. ON Semiconductor continues to increase demand at the Aizu 8-inch fab, and both companies determined that further strategic partnership will maximize the value both companies provide.

ON Semiconductor plans to increase ownership to 60 percent by the second half of 2018 and to 100 percent in the first half of 2020, allowing ON Semiconductor to add capacity to their global footprint. This additional capacity will allow ON Semiconductor to continue scaling its business based on demand and enable increased supply chain flexibility.

“We believe that transforming into a globally competitive company is the key for the continuous growth of the Aizu 8-inch fab. Furthering our strategic partnership with ON Semiconductor, who provides a broad product portfolio, will enable the Aizu 8-inch fab to secure future growth,” said Kagemasa Magaribuchi, president of Fujitsu Semiconductor Limited. “We believe that the growth of the Aizu 8-inch fab will contribute to maintaining and expanding a strong workforce and assist with the development of the regions.”

“We have had a strong and successful partnership with Fujitsu since announcing our investment in 2014,” said Keith Jackson, president and CEO of ON Semiconductor. “We believe furthering our partnership with Fujitsu Semiconductor will enable us to maintain our industry-leading manufacturing cost structure and also help us optimize our capital spending in coming years. This is a strategic investment for ON Semiconductor to secure additional manufacturing capacity, in support of our accelerated production needs and for revenue growth in coming years.”

Manufacturing is a core competency for ON Semiconductor, and approximately 75 percent of manufacturing operations are done internally through the company’s industry leading cost structure.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $35.0 billion for the month of August 2017, an increase of 23.9 percent compared to the August 2016 total of $28.2 billion and 4.0 percent more than the July 2017 total of $33.6 billion. All major regional markets posted both year-to-year and month-to-month increases in August, and the Americas market led the way with growth of 39.0 percent year-to-year and 8.8 percent month-to-month. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales were up significantly in August, increasing year-to-year for the thirteenth consecutive month and reaching $35 billion for the first time,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales in August increased across the board, with every major regional market and semiconductor product category posting gains on a month-to-month and year-to-year basis. Memory products continue be a major driver of overall market growth, but sales were up even without memory in August.”

Year-to-year sales increased in the Americas (39.0 percent), China (23.3 percent), Asia Pacific/All Other (19.5 percent), Europe (18.8 percent), and Japan (14.3 percent). Month-to-month sales increased in the Americas (8.8 percent), China (3.7 percent), Japan (2.8 percent), Asia Pacific/All Other (2.2 percent), and Europe (0.6 percent).

“With about half of global market share, the U.S. semiconductor industry is the worldwide leader, but U.S. companies face intense global competition,” said Neuffer. “To allow our industry to continue to grow and innovate here at home, policymakers in Washington should enact corporate tax reform that makes the U.S. tax system more competitive with other countries. The corporate tax reform framework released last week by leaders in Congress and the Trump Administration is an important step forward. We look forward to working with policymakers to enact corporate tax reform that strengthens our industry and the U.S. economy.”

Aug 2017

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

6.94

7.55

8.8%

Europe

3.20

3.22

0.6%

Japan

3.04

3.13

2.8%

China

10.68

11.08

3.7%

Asia Pacific/All Other

9.77

9.98

2.2%

Total

33.63

34.96

4.0%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

5.43

7.55

39.0%

Europe

2.71

3.22

18.8%

Japan

2.73

3.13

14.3%

China

8.99

11.08

23.3%

Asia Pacific/All Other

8.35

9.98

19.5%

Total

28.22

34.96

23.9%

Three-Month-Moving Average Sales

Market

Mar/Apr/May

Jun/Jul/Aug

% Change

Americas

6.27

7.55

20.5%

Europe

3.11

3.22

3.8%

Japan

2.95

3.13

6.0%

China

10.25

11.08

8.1%

Asia Pacific/All Other

9.43

9.98

5.9%

Total

31.99

34.96

9.3%

Today, SEMI announced the lineup of keynotes coming to SEMICON Japan’s “SuperTHEATER” ─ focusing on the future of the electronics manufacturing supply chain. SEMICON Japan 2017, the largest exhibition in Japan for electronics manufacturing, will take place at Tokyo Big Sight in Tokyo on December 13-15. Registration is now open for the exhibition and programs.

With the theme “Dreams Start Here,” SEMICON Japan 2017 will bring together the connections between people, technologies and businesses across the electronics manufacturing supply chain ─ extending to the internet of things (IoT) applications that inspire the dreams that shape the future.

Japan has the world’s third-largest 300mm wafer installed fab capacity and the world’s largest 200mm and smaller wafer fab capacity (including discrete devices production). Japan also supplies one third of the semiconductor equipment and more than half of the semiconductor materials that are purchased in the global market.

The SuperTHEATER offers nine keynote forums, all with simultaneous English-Japanese translation. On December 13, keynotes at SEMICON Japan’s SuperTHEATER include:

  • Opening Keynotes ─ Visions of the Game Changing Era
    • Soft Bank:  Ken Miyauchi, president and CEO, “The Information Revolution beyond the Singularity”
    • Qualcomm Technologies: Raj Talluri, senior VP of product management, “Qualcomm Viewpoint: Accelerating the Internet of Things”
       
  • Semiconductor Executive Forum ─ Growth Strategy in New Business Environment
    • TowerJazz Semiconductor: Russell Ellwanger, CEO, “Value Creation”
    • SMIC: Haijun Zhao, CEO, Considerations in Developing Manufacturable IC Technologies”
    • Micron Technology: Wayne Allan, senior VP of global manufacturing, “Enabling Smart Manufacturing in Today’s Industry 4.0”

The SEMI Market Forum, also on December 13, will offer presentations from IHS Markit and SEMI, with the theme “In the Light and Shadow of Awaking China”

Additional SEMICON Japan 2017 highlights include:

  • IT/AI Forum on U.S. companies’ artificial intelligence strategies
  • IoT Global Trends Forum on semiconductors for IoT
  • IoT Key Technology Forum on Smart Transportation
  • Manufacturing Innovation Forum n “Manufacturing Technology for the Diversified Future”
  • Electronics Trends
  • Mirai (the Future) Vision

 

For more information and to register for SEMICON Japan, visit www.semiconjapan.org/en/

COMET Group, a global provider of high-quality systems, components and services such as x-ray, ebeam and radio frequency technologies, today announced the opening of Lab One, its customer-centric technology and application center in San Jose, CA.

Scheduled to open October 4th, Lab One will bring Comet Group’s three core technologies under one roof for the first time:

  • RF power – Comet Plasma Control Technologies (PCT) designs and manufactures the technology used to make semiconductors and is used by leading chip manufacturers that power the industry’s most popular mobile devices (e.g. Apple, Samsung) and electronics (e.g. flat panel displays)
  • X-ray – Yxlon’s industrial X-ray and computed tomography – systems and services enable customers to improve the quality of their products and processes by non-destructive testing, measuring and decision support in industries such as electronics, automotive, aerospace, medtech, science and new technologies. They are based on highly compact Comet x-ray components and sources
  • ebeam – ebeam technology inactivates harmful pathogens that can cause food borne illnesses and provides safe, environmentally friendly packaging materials that reduce waste and improve food security

The working Lab and testing environment will act as an extension to many leading Silicon Valley businesses – providing access to a variety of testing and inspection services, as well as opportunities to collaborate with Comet Group’s industry experts, who will be available for consultation, brainstorming and problem solving.

“Our new Lab One facility can save local businesses time by providing local inspection services, save them money by finding costly flaws, and solve their logistic inspection services headaches with quick answers to their non-destructive test needs,” said Paul Smith, Sr. Vice President at Comet Technologies USA. “It’s a place where ideas are jointly transformed into solutions and solutions into business success.” 

With pioneering solutions for a wide range of industries, Comet Group will support its clients by bringing greater safety and security, mobility, sustainability and efficiency to numerous areas of life.

By James Amano, International Standards, SEMI

The SEMI International Standards Committee, at their SEMICON West 2017 meeting, approved the transformation of the existing 3D Stacked IC Committee and Assembly & Packaging Committee into a single, unified 3D Packaging and Integration Committee. Emerging technologies will be accommodated into the scope of the new committee, as North American TC Chapter Co-Chair Sesh Ramaswami (Applied Materials) explains: “Multi-die integration, horizontally and vertically, leveraging substrate, fan-out, interposer and TSV technology is our future. Hence, the new charter and scope will enable the committee to be of more value to the industry.”

Charter:

To explore, evaluate, discuss, and create consensus-based specifications, guidelines, test methods, and practices that, through voluntary compliance, will:

  • include the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration, either single- or multi-chip configurations. It relates to the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, flexible electronics technology
  • promote mutual understanding and improved communication between users and suppliers, equipment, automation systems, devices, and services
  • enhance the manufacturing efficiency, capability and shorten time-to-market and reduce manufacturing cost

Scope:

To develop standards for semiconductor devices, including processed wafers, chips, or multi-chip configurations to the next level of integration, either in single- or multi-chip configurations.

  • materials needed for 3D applications, including prime silicon and glass wafers, temporary and permanent bonding material, specifications needed for processed wafers and/or chips to enter an integration step, etc.
  • the materials related to the elements of, interconnection schemes, and unique packaging assemblies that provide for the communication link between device and packaging.
  • the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, and flexible electronics technology
  • metrologies to support these 3D integration and packaging technologies

Masahiro Tsuriya (iNEMI), Japan Co-Chair, further emphasizes “The new 3D Packaging & Integration Committee will be able to contribute to the advance of new, innovative semiconductor packaging technologies.”

The global committee currently has chapters active in Japan, North America, and Taiwan, which all meet throughout the year. To get involved, please join the SEMI International Standards Program at: www.semi.org/standardsmembership.

The Semiconductor Industry Association (SIA) released the following statement today from SIA president & CEO John Neuffer in support of the corporate tax reform framework released today by leaders in the Trump Administration and Congress. The proposal is expected to be considered by Congress in the coming weeks.

“Over the past three decades, the U.S. semiconductor industry has unleashed tremendous innovations that have transformed America’s economic, technological, and national security landscape. America’s corporate tax system, meanwhile, has remained largely unchanged, leaving U.S. businesses at a disadvantage to their overseas competitors.

“The tax reform framework is a step forward to make the U.S. corporate tax system more competitive and allow U.S. semiconductor companies to continue to grow and innovate here at home. The plan would advance the U.S. semiconductor industry’s core priorities for tax reform: a lower, globally competitive rate, a modern international tax system, and strong incentives for research and innovation.

“While there are many details of importance to our industry that need to be fleshed out, we support the plan as a framework for advancing corporate tax reform.  We look forward to working with Congress and the Administration to enact corporate tax reform that makes the United States more globally competitive and boosts U.S. leadership in semiconductor research, design, and manufacturing.”

A new system combines acoustic, optical and reflectometric techniques to enable measurement of metals, dielectrics, resists and critical dimensions on a single platform.

BY CHEOLKYU KIM, Director of Metrology Product Management, Rudolph Technologies, Inc.

Rapid growth in the mobile device market is generating demand for advanced packaging solutions with higher levels of system integration and increased I/Os and functionality. This demand is driving 2.5D/3D integration of IC devices, which in turn requires sophisticated packaging technologies. Among various approaches, fan-out is gaining traction as outsourced semiconductor assembly and test (OSAT) houses and wafer foundries roll out their own technologies. As illustrated in FIGURE 1, the adoption of fan-out technology accelerated significantly in 2016, and is projected to reach $2.5 billion by 2021, a more than 10X increase from 2015.

Screen Shot 2017-09-25 at 1.20.09 PM

First generation “core” fan-out was geared toward mobile applications and had RDL lines that were typically 10/10μm (line/space) and larger. Second generation HDFO processes, which were developed to integrate multiple chips in a single package, use more RDL lines at smaller width and tighter pitch, down to 2/2μm and smaller. Growth in HDFO accelerated with the entry of Apple and TSMC in 2016 and accounts for the bulk of the fan-out growth projected through 2021 [2-4].

As design rules for HDFO approach those of front-end processes, so too will requirements for process control and, in consequence, the need for more accurate and repeatable metrology. Until now, manufacturers have characterized metal films, such as RDL and under bump metallization (UBM), using semi-automated measurement tools, such as contact profilometers, which are easy to use and relatively inexpensive. However, these tools are not the best solution for measuring a variety of products with varying topographies in high volume production.

High Density Fan-Out process control

HDFO processes include one or more RDL, the number depending on the application. Like front-end processes, HDFO processes use additive and subtractive technol- ogies to create patterns of conductive metal lines isolated by dielectric materials. As RDL lines become smaller, controlling line resistance with appropriate dimensional control has become essential. For an RDL process, the most important parameters to monitor are dielectric thickness, Cu seed layer thickness, Cu thickness and line width (CD). In general, the process must operate inside a window that varies within 10% of the target value. This, in turn, requires measurement tools with a gauge capability (3σ repeatability + reproducibility) of 10% of the variability, or 1% of the target value. In addition to delivering accuracy and repeatability, the metrology system must be able to operate on product wafers and, therefore, 1) be able to measure test structures smaller than 50μm, 2) be non contact/non-destructive/ non-contaminating, 3) be fast enough to support high volume production and 4) be able to handle the significant surface topography and substrate/wafer warpage that are induced by the HDFO process.

As shown schematically in FIGURE 2, the metrology system described here (MetaPULSE® AP, Rudolph Technologies), combines picosecond ultrasonic laser sonar (PULSETM), automated optical microscopy and reflectometry to meet all the requirements for RDL process control in a single system. The acoustic technique, well proven and widely accepted for metal film metrology in front-end applications, is a first principle technology that provides accurate measurements of metal film thickness for UBM and RDL.

Screen Shot 2017-09-25 at 1.20.16 PM

Measurements of RDL thickness with this technique on dense line arrays, pads and bumps have shown excellent correlation to cross sectional scanning electron microscope (X-SEM) results. The precision and gage capability of the technology have been validated down to 2μm and meet OSAT and foundry RDL roadmap requirements.

The integration of a high-resolution reflectometer provides accurate measurements of dielectric and resist thickness, ranging from a few 1000Å to 60μm, on product wafers. The incorporation of an automated optical microscope/high-resolution camera provides gage-capable CD measurements. CD measurements can be made simultaneously with thickness measurements. The addition of optical CD measurements and reflectometer-based transparent film thickness measurements to the acoustic platform provides an efficient and comprehensive in-line RDL metrology solution that eliminates the need to route wafers to multiple measurement tools.

PULSE acoustic thickness measurements on opaque films

FIGURE 3 illustrates the principles of the PULSE acoustic measurement technology. An extremely short laser pulse is focused onto a small spot on the sample surface where the energy of the laser pulse is absorbed by the film surface. This causes a sudden increase of surface temperature, and rapid thermal expansion launches a sound wave on the surface that travels into the film. When the sound wave reaches an interface with an underlying film, it is partially reflected back to the surface as an echo. Upon arrival at the surface, the echo causes a change in optical reflectivity, which is detected to measure the round-trip travel time of the sound wave. Film thickness can be calculated from the travel time of the sound wave and the speed of sound in the material. Some of the energy from the original sound wave is transmitted through the interface. In a multi-layered stack, the progressing sound wave returns a distinct echo from each interface. An analysis of the round-trip travel time for each successive echo permits the calculation of the thickness of each layer. Typical data acquisition times vary from 1s to 4s per site. Repeatability is < 0.1% of target thickness, meeting the 10% GR&R requirement. FIGURE 4 shows the correlation between X-SEM and PULSE measurements for RDL in the 1.25μm-1.5μm thickness range. The excellent correlation clearly demonstrates the accuracy of PULSE thickness measurements.

Screen Shot 2017-09-25 at 1.20.23 PM Screen Shot 2017-09-25 at 1.20.30 PM Screen Shot 2017-09-25 at 1.20.36 PM

Reflectometer thickness measurements on transparent films

FIGURE 5 (left) demonstrates the strong correspondence between a measured reflectometer signal and a model fitted curve for 5μm polyimide on Si. The figure also shows the correlation between reflectometer measurements and a fab reference metrology tool. The excellent correlation with the reference tool confirms the accuracy of reflectometer measurements. Data collection time for reflectometer measurements is typically less than 1s. The reflectometer has excellent sensitivity with Å level resolution and gage-capable R&R.

Screen Shot 2017-09-25 at 1.20.44 PM Screen Shot 2017-09-25 at 1.20.49 PM

Automated optical CD measurements

Using the optical microscope/ high resolution camera system, users can define multiple regions of interest (ROI) for CD measurements, including single line and multi-line arrays. The built-in measurement algorithms can report individual or average values. Extension of the CD technique to also measure overlay has shown promising results and additional work is in progress to fully characterize the capability. FIGURE 6 shows images and signals from CD measurements on lines and arrays. The strong correlation between optical CD and X-SEM measurements (FIGURE 7) validates the accuracy of the technique. CD measurement with the optical microscope is limited by the micro- scope’s resolution, typically 1μm or larger. Since SEM resolution is typically on the scale of nanometers, the correlation requires proper calibration. The results shown in Fig. 7 are after calibration.

Screen Shot 2017-09-25 at 1.21.01 PM Screen Shot 2017-09-25 at 1.21.06 PM Screen Shot 2017-09-25 at 1.21.13 PM

Multi-layered stacks

Most of RDL plating requires prior deposition of a Cu seed layer, the thickness of which must also be tightly controlled. FIGURE 8 (left) shows examples of the acoustic signals acquired from three Cu/ Ti stacks of varying thickness. The first positive peak of each signal gives the round-trip travel time of the sound wave in the Cu film, while the spacing between first and second positive peaks gives the round-trip travel time through the Ti layer. The echo positions are used to calculate the thickness of Cu and Ti layers simultaneously. Figure 8 (right) shows the signal of an Au/Ni/Cu/Al stack measured on UBM. The echo from each layer is distinct. Knowing the arrival times of the echoes and the speed of sound in the materials, the system calculates the thickness of all four layers simultaneously, with 3σ repeatability less than 1% for each of the layers.

Screen Shot 2017-09-25 at 1.21.21 PM Screen Shot 2017-09-25 at 1.21.28 PM

Warped wafer handling

The thin wafers/substrates used in HDFO processes can be warped significantly at several different steps in the process, most significantly by the mismatch between thermal expansion coefficients of the molding compound and the die. Warpage of 2mm or more poses a major challenge to handling and measurement systems. A specially designed vacuum chuck has three concentric vacuum zones. Applying vacuum to the zones sequentially, starting with the innermost zone and working out, the chuck pulls and holds warped wafers flat against itself to allow accurate measurements.

Conclusions

High density fan-out packaging is essential for advancing growth in mobile and networking applica- tions. The integration of multi-chip modules in fan-out processes requires complex processing using tools and materials that are significantly more expensive than traditional packaging lines. We have described an automated metrology solution that combines acoustic measurements with high resolution reflectometry and optical microscopy to provide comprehensive, gage- capable measurements for characterizing critical process steps in high volume production applications. Simultaneous measurement of multiple parameters on a single platform eliminates the need to route product through several different tools, improving the speed and efficiency, and reducing the overall cost-of-ownership, of the metrology process.

References

1. “Fan-out technnologies and MarketTrends 2016 Report”,Yole Devel- oppement, July 2016
2. “What is driving advanced packaging platforms development?”, T. Buisson and S. Kumar, Chip Scale Review, pp. 32-36,May-June 2016 3. “Recent advances and trends in advanced packaging”, J. Lau, Chip
Scale Review, pp. 46-54, May-June 2017.
4. “Status of Advanced Packaging Report,” Yole Developpement, June 2017.

North America-based manufacturers of semiconductor equipment posted $2.18 billion in billings worldwide in August 2017 (three-month average basis), according to the August Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in August 2017 was $2.18 billion.The billings figure is 3.9 percent lower than the final July 2017 level of $2.27 billion, and is 27.7 percent higher than the August 2016 billings level of $1.71 billion.

“Equipment billings in August declined relative to July, signaling a pause in this year’s extraordinary growth,” said Ajit Manocha, president and CEO of SEMI. “Nonetheless monthly billings remain well above last year’s monthly levels.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)
Year-Over-Year
March 2017
$2,079.7
73.7%
April 2017
$2,136.4
46.3%
May 2017
$2,270.5
41.8%
June 2017
$2,300.3
34.1%
July 2017 (final)
$2,269.7
32.9%
August 2017 (prelim)
$2,181.8
27.7%

Source: SEMI (www.semi.org), September 2017

IC Insights has just released its September Update to The McClean Report.  This 32-page Update includes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends.  Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.

In 2017, the 7% increase in the total pure-play foundry market is forecast to be almost entirely due to an 18% jump in <40nm feature size device sales (Figure 1).

Figure 1

Figure 1

Although expected to represent 60% of total pure-play foundry sales in 2017, the ≥40nm pure-play IC foundry market is forecast to be up only $0.2 billion this year.  In contrast, the 2017 leading-edge <40nm pure-play foundry market is expected to surge by a hefty $3.3 billion.  Moreover, not only is almost all of the pure-play foundry growth forecast to come from leading-edge production in 2017, most of the profits that are expected to be realized in the foundry market also forecast to come from the finer feature sizes as well.

TSMC is by far the technology leader among the major pure-play foundries.  In 2017, 58% of TSMC’s revenue is expected to come from <40nm processing, more than double percentage at GlobalFoundries and more than triple the share at UMC.  In total, TSMC is forecast to hold an 86% share of the total <40nm pure-play foundry market this year.

Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have almost 7x the dollar volume sales at <40nm as compared to GlobalFoundries, UMC, and SMIC combined this year ($18.5 billion for TSMC and $2.7 billion for combined total of GlobalFoundries, UMC, and SMIC).  In fact, 10% of TSMC’s total sales this year are forecast to be for its 10nm process technology.

In contrast to TSMC, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.  In fact, only 7% of SMIC’s 2017 sales are expected to be from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so much less compared to TSMC.

Semiconductor Research Corporation (SRC), today announced that Samsung Electronics Company Ltd. (Samsung), one of the world’s largest chipmakers, has signed an agreement to join SRC’s research consortium. Samsung will participate in two SRC platforms – the New Science Team (NST) project and the Global Research Collaboration (GRC) program.

The NST project, a 5-year, $300M+ initiative commences in January 2018. NST consists of two complementary research programs: JUMP (Joint University Microelectronics Program) and nCORE (nanoelectronics Computing Research), supporting long-term research focused on high- performance, energy-efficient microelectronics for communications, computing and storage needs. Within the GRC program, comprised of nine design and process technology research disciplines, Samsung will participate in the Packaging and Logic & Memory Devices programs.

“It is an exciting time at SRC with the addition of Samsung to our premier group of semiconductor design, manufacturing, and advanced technology companies. SRC welcomes Samsung as we continue to bring together the world’s most brilliant minds to turn theories into reality,” said Ken Hansen, President and CEO of Semiconductor Research Corporation. “We now have the most innovative semiconductor companies collaborating to advance research for next-generation technology and to continue the promise of Moore’s Law economics, bringing increased performance and new product features to the consumer.”

“Collaborative research has been a key element of Samsung’s global strategy,” said Dr. HK Kang, Executive Vice President of Semiconductor Research and Development Center, Samsung Electronics. “The roadmap to future discoveries in technology is deeply rooted in the research coming from industry-sponsored university programs such as NST and GRC. We look forward to working with the SRC team to spark meaningful advancements in semiconductor technology as we explore future innovation.”

With the addition of Samsung, 7 of the top 10 global semiconductor companies are now members of SRC. Samsung represents the fifth non-U.S. headquartered company to join SRC within the last 18+ months.