Category Archives: Metrology

By Paula Doe, SEMI

As the rate of traditional scaling slows, the chip sector looks increasingly to materials and design to move forward on multiple paths for multiple applications. Figuring out more effective ways to collaborate across silos will be crucial.

Source: IBM [IBM slide 6 in Strategic Materials Conference deck]

Source: IBM [IBM slide 6 in Strategic Materials Conference deck]

  1. Paradigm shift requires co-optimization

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“Scaling has hit a wall, and there is no longer any single path forward,” noted Larry Clevenger, BEOL Architect and Technology Definition, IBM Research, at the SEMI Strategic Materials Conference 2016 (September 20-21). “The materials set we use in the middle and back end of line is running out of steam. We need new materials and design co-optimization.”  He noted EUV would much improve the critical tight pitch areas for the memory and BEOL for 7nm-5nm logic. But reducing the parasitics in the metal interconnect in middle of the line and BEOL will also be critical, with good results demonstrated from new materials like Si:P and Ge:Ga meta-stable alloys, cobalt instead of tungsten, self-forming encapsulation of copper by cobalt, and airgaps, all of which would require optimization of an ecosystem of appropriate cleaning, deposition and wet process technologies for integration. Changing the design to route the critical paths directly up to higher wiring levels where the wires are larger would also help reduce resistance.

“It’s a paradigm shift that what was once a process deviation is now an excursion,” said Archita Sengupta, Intel senior technologist, noting the need for new specialized tools to measure, monitor and control the process to detect ever tinier defects sooner. “We need more proactive cooperation across the supply chain for bottom up control of quality from suppliers.”

Showing impressive examples of imaging and computation enabling doctors to reduce errors in breast cancer detection by 85 percent, and even to operate on a beating heart, using Nvidia GPUs and artificial intelligence, Nvidia’s director of Advanced Technology John Hu noted, “We are at a real inflection point for demand for more compute power, and we can’t get there by just process scaling any more. We are going to have to rely on new architectures to rescue us from the increasingly imperfect reality of materials and processes.”

While almost every speaker stressed the increasing need for the different segments of the supply chain from materials to design to work more closely together to move technology forward along many new paths, the materials suppliers in the audience felt that progress could be better to make this happen. Some audience members talked among themselves of now being invited more often into the fabs to discuss material development, but still not being told much detail about the key target parameters. Material suppliers in the audience raised the issues of the time and expense needed to qualify their second sources for raw materials and precursors, to get the needed environmental certifications, and to find access to the expensive exotic multi-technology metrology tools capable of finding contaminates too small to see with conventional methods, before they could even bring in any potential material to be evaluated for use several years in the future.

Although speakers kept referring to the past Golden Age of Moore’s Law of regular two-year dimensional scaling, before the proliferation of alternatives, Tim Hendry, retiring Intel VP, Fab Materials, pointed out that it hadn’t really seemed like a Golden Age at the time. “As I remember, we thought it was pretty hard back then too.”

  1. Look to self-aligned and selective processes as scaling boosters

As lithography scaling slows down, new approaches will make creative use of deposition and etch to keep improving pattern resolution. “14nm is a real sweet spot technically for lithography that will be with us for a long time,” noted Anton DeVilliers, Tokyo Electron America director of Patterning Technology, suggesting a toolkit of assorted self-alignment and selective deposition and etch processes likely to see increasing use as resolution boosters as an alternative to pushing the lithography, such as collars at key points to protect the pattern, or self aligned patterning by selective etching.

Adding a protective ALD collar holds a key region open during etch to widen the process window and prevent shorts from process variation in tight pattern areas.

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ALD snap collar holds the critical part of M1 pattern open to widen window in LELELE process…

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So that overlay variation that would typically create a short…

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Instead creates the desired pattern. Source: TEL

Using materials with different etch selectivity for different parts of a pattern, such as for alternate lines, enables the creation of a self aligned pattern at higher resolution than the lithography.  Different etch selectivity in alternate metal tracks could also reduce the number of exposure passes and improve overlay tolerance. “For 5nm nanowires, we’ll have to use selective ALD and ALE, controlled by self assembling monolayers,” noted DeVilliers. “We’ve done each of these steps on a tool, but now the challenge is to put them all together.”

  1. Progress on 3D alternatives

“To maintain the pace of progress we’ll have to change everything—we can’t do it with Moore’s Law,” said Bill Bottoms, chairman and CEO, Third Millennium Test Solutions, updating on the international effort to create a Heterogeneous Integration Roadmap. “Future progress will come from bringing active elements closer together through integration at the system level, with interconnect with photonics and plasmonics.” The aim is to map future needs to better enable precompetitive collaboration. The first edition of the roadmap is now slated to come out in March.

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CEA-Leti researchers meanwhile are reporting good progress on lowering the temperatures of the various processes needed to build a second chip directly on top of a first, for monolithic 3D CMOS-on-CMOS integration.  Performance of the bottom chip degrades if the process temperatures for the top chip are >500°C, mainly because the NiPt silicide deteriorates, but replacing the NiPt with a more stable NiCo and adding an Si cap looks promising to increase stability. The 8nm active active layer for the top device is bonded atop the bottom device at room temperature and annealed 300C. Nanosecond laser thermal annealing and low temperature solid phase epitaxy regrowth help bring down temperatures for dopant activation. Cycles of deposition and etch replace selective epitaxy for the source and drain, while different precursors reduce process temperatures to 500-550C. “Later this year at IEDM we’ll demonstrate top CMOS made at 500°C with these developments,” said Philippe Rodriguez, CEA-Leti research engineer.

  1. Get used to the slow growth world 

The semiconductor industry will see silicon demand (MSI) pick up from this year’s 0.6 percent increase to  ~3.8 percent growth in 2017, and ~6.3 percent in 2018, as some uncertainty about interest rates and government policy in major countries resolves, according to the econometric semiconductor forecast from Hilltop Economics and LINX Consulting. “We got comfortable with 3 percent GDP growth in the world that we sell chips into, but since the 2009 recession we are only seeing about 2.4 percent growth,” said Duncan Meldrum, chief economist, Hilltop Economics. He noted that economists keep saying the world will get back to its regular 3 percent growth next quarter or year, but it hasn’t happened, probably because high government debt levels in most major economies tends to reduce growth by about reduces it. Silicon demand grows a little faster than GDP, but its trends generally track that global growth number more than in the past as the electronics industry matures.

  1. Wafer level fan out will shake up package materials sector

Now that it appears the 40 to 50 percent improvement in performance in the newest Apple A10 processor is largely from its wafer-level fan out packaging from TSMC, demand for the packaging approach is ramping fast. “This is one of the fastest ramps we’ve seem for a package in a long time,” said TechSearch International president Jan Vardaman. “It’s a very disruptive technology that will have a big impact on the industry.” The thinner, lower-cost packaging approach is also showing up in RF and audio codec chips in mobile phones, with  ~2 billion units just in Samsung and Apple phones, potentially bringing big changes to the packaging materials market. Laminate substrate suppliers will see demand plunge, copper post suppliers will see little change, and makers of wafer-level dielectrics could potentially see 3X growth in volume. “But don’t think you’ll see that in revenue, since customers will really beat the prices down.”

And in a final note, the gathered materials sector paused in a moment of silence for Dan Rose, who passed away on September 19.  Dan was a well-known market researcher and founder of Rose Associates with a focus on materials market data.

Originally published on the SEMI blog.

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry business. An excerpt from the September Update, describing foundry sales by feature size, is shown below.

Figure 1

Figure 1

TSMC has long been the technology leader among the major pure-play foundries. As shown in Figure 1, 54% of TSMC’s 2016 revenue is expected to come from <40nm processing. GlobalFoundries, which has dedicated a large portion of its capacity to making advanced processors over the past few years, also generates a large portion of its sales based on leading-edge process technology and feature sizes. In 2016, 52% of GlobalFoundries’ sales are forecast to come from <40nm production.

Although GlobalFoundries and TSMC are forecast to have a similar share of their sales dedicated to <40nm technology this year, TSMC is expected to have almost 6x the sales volume at <40nm as compared to GlobalFoundries in 2016 ($15.6 billion for TSMC and $2.6 billion for GlobalFoundries). In contrast, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.

Because TSMC has a very large percentage of its sales targeting <40nm production, its revenue per wafer is forecast to increase at a CAGR of 3% from 2011 through 2016 as compared to a -1% CAGR expected for the total revenue per wafer average of GlobalFoundries, UMC, and SMIC over this same timeperiod. Only 2% of SMIC’s 2016 sales are expected to come from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so low as compared to TSMC and GlobalFoundries.

It is interesting to note that the increase in pure-play foundry sales this year is forecast to be almost entirely due to <40nm feature size device sales (Figure 2). Although it is expected to represent 60% of total pure-play foundry sales in 2016, the ≥40nm pure-play IC foundry market is forecast to be flat this year. In contrast, the leading-edge <40nm pure-play foundry market in 2016 is expected to surge by 23%, increasing by a hefty $3.6 billion.

Figure 2

Figure 2

North America-based manufacturers of semiconductor equipment posted $1.75 billion in orders worldwide in August 2016 (three-month average basis) and a book-to-bill ratio of 1.03, according to the August Equipment Market Data Subscription (EMDS) Book-to-Bill Report published by SEMI.  A book-to-bill of 1.03 means that $103 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in August 2016 was $1.75 billion. The bookings figure is 2.3 percent lower than the final July 2016 level of $1.80 billion, and is 5.0 percent higher than the August 2015 order level of $1.67 billion.

The three-month average of worldwide billings in August 2016 was $1.71 billion. The billings figure is approximately the same as the final July 2016 level of $1.71 billion, and is 8.4 percent higher than the August 2015 billings level of $1.58 billion.

“The book-to-bill ratio has been at or above parity since December of last year with current monthly bookings and billings levels at $1.7 billion,” said Denny McGuirk, president and CEO of SEMI.  “Given the current data trends, North American equipment suppliers are clearly benefiting from strong investments by device manufacturers in the second half of the year.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

  Billings
(3-mo. avg)		 Bookings
(3-mo. avg)		 Book-to-Bill
March 2016  $1,197.6 $1,379.2 1.15
April 2016  $1,460.2 $1,595.4 1.09
May 2016  $1,601.5 $1,750.5 1.09
June 2016  $1,715.2 $1,714.3 1.00
July 2016 (final) $1,707.9 $1,795.4 1.05
August 2016 (prelim) $1,708.1 $1,753.9 1.03

Source: SEMI (www.semi.org), September 2016

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the SEMI Equipment Market Data Subscription (EMDS).

Analogix Semiconductor, Inc. and Beijing Shanhai Capital Management Co, Ltd. (Shanhai Capital), today jointly announced that they have entered into a definitive merger agreement under which a consortium led by Shanhai Capital will acquire all of the outstanding shares of Analogix for over $500 million. China Integrated Circuit Industry Investment Fund Co., Ltd. (China IC Fund) also joined Shanhai Capital’s fund as one of the limited partners. The transaction is subject to regulatory approvals and is expected to close in late 2016.

Analogix’s high-speed, mixed-signal semiconductor integrated circuits (ICs) for high-performance display applications are used in mobile devices, virtual/augmented reality (VR/AR), and other high-performance electronic products from leading electronics brands including Apple, Samsung, LG, Microsoft, Google, Lenovo, Dell, HP, Asus, and HTC. The company is headquartered in Santa Clara, California, and the majority of its engineering operations are located in Beijing, China. Current investors include leading venture capital firms: DCM Ventures, Globespan Capital Partners, Keytone Ventures, and the Woodside Fund.

“We are very happy to have reached this agreement, which provides significant value to our shareholders,” said Dr. Kewei Yang, Analogix Semiconductor’s chairman and CEO. “The financial support of Shanhai Capital propels our growth while maintaining the direction, organization, and determination to serve our customers. I am especially excited that we all share the same vision of building Analogix into a much broader and more capable global semiconductor leader.”

“We are pleased to establish our relationship with Analogix, a company whose technology leadership is recognized by the world’s leading OEMs, and we look forward to facilitating Analogix’s continued growth,” said Mr. Xianfeng Zhao, Chairman of Beijing Shanhai Capital Management Co, Ltd. “With the added investment, we can leverage the strength of the company’s core technology and business expertise, extend our business into adjacent high-growth markets, and build a world-leading semiconductor company. We expect an IPO in China in the near future.”

The Semiconductor Industry Association (SIA), in consultation with Semiconductor Research Corporation (SRC), today presented its University Research Award to professors from the University of Chicago and the University of Michigan in recognition of their outstanding contributions to semiconductor research.

Dr. Paul Nealey, professor of molecular engineering at the University of Chicago, received the honor for excellence in technology research, while Dr. David T. Blaauw, professor of electrical engineering and computer science at the University of Michigan, was recognized for excellence in design research.

“Research brings to life the tremendous innovations that underpin the U.S. semiconductor industry, the broader tech sector, and our economy,” said John Neuffer, president and CEO of the Semiconductor Industry Association, which represents U.S. leadership in semiconductor manufacturing, design, and research.

“Professors Nealey and Blaauw have led research efforts that have advanced semiconductor technology and strengthened America’s global technology leadership. It is an honor to recognize Dr. Nealey and Dr. Blaauw for their landmark accomplishments.”

“SRC’s mission is to drive focused industry research to both advance state-of-the-art technology and continue to create a pipeline of qualified professionals who will serve as next-generation leaders for the industry,” said Ken Hansen, SRC President and CEO. “Dr. Nealey and Dr. Blaauw exemplify that spirit of innovation, and we’re pleased to honor them for their achievements.”

Dr. Nealey is a pioneer of directed self-assembly, which is becoming very important in microelectronics processing to create patterns for integrated circuits. He is one of the world’s leading experts on patterning organic materials. This entails creating physical patterns of structure and composition in organic materials at the nanometer length scale, where the patterns affect the function of the materials. Dr. Nealey holds 14 patents and is the author of more than 180 publications.

Dr. Blaauw worked for Motorola, Inc. from 1993-2001, where he was the manager of the High Performance Design Technology group. Since August 2001, he has been on the faculty at the University of Michigan where he is currently a full professor. His work has focused on VLSI design with particular emphasis on adaptive and low-power design. Dr. Blaauw received his B.S. from Duke University in 1986 and his Ph.D. from the University of Illinois, Urbana, in 1991.

The University Research Award was established in 1995 to recognize lifetime research contributions to the U.S. semiconductor industry by university faculty.

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry industry and a look at the current state of the merger and acquisition surge in the semiconductor industry. An excerpt from the M&A portion of this Update is shown below.

After an historic surge in semiconductor merger and acquisition agreements in 2015, the torrid pace of transactions has eased (until recently), but 2016 is already the second-largest year ever for chip industry M&A announcements, thanks to three major deals struck in 3Q16 that have a combined total value of $51.0 billion. As of the middle of September, announced semiconductor acquisition agreements this year have a combined value of $55.3 billion compared to the all-time high of $103.8 billion reached in all of 2015 (Figure 1). Through the first three quarters of 2015, semiconductor acquisition pacts had a combined value of about $79.1 billion, which is 43% higher than the total of the purchasing agreements reached in the same period of 2016, based on M&A data compiled by IC Insights.

In many ways, 2016 has become a sequel to the M&A mania that erupted in 2015, when semiconductor acquisitions accelerated because a growing number of suppliers turned to purchase agreements to offset slower growth in major existing end-use equipment applications (such as smartphones, PCs, and tablets) and to broaden their businesses to serve huge new market potentials, including the Internet of Things (IoT), wearable electronics, and strong segments in embedded electronics, like highly-automated automotive systems. China’s goal of boosting its domestic IC industry is also driving M&A. In the first half of 2016, it appeared the enormous wave of semiconductor acquisitions in 2015 had subsided substantially, with the value of transactions announced between January and June being just $4.3 billion compared to $72.6 billion in the same six-month period in 1H15. However, three large acquisition agreements announced in 3Q16, including SoftBank’s purchase of ARM, Analog Devices’ intended purchase of Linear Technology, and Renesas’ potential acquisition of Intersil) have insured that 2016 will be second only to 2015 in terms of the total value of announced semiconductor M&A transactions.

Figure 1

Figure 1

A major difference between the huge wave of semiconductor acquisitions in 2015 and the nearly 20 deals being struck in 2016 is that a significant number of transactions this year are for parts of businesses, divisions, product lines, technologies, or certain assets of companies.  This year has seen a surge in the agreements in which semiconductor companies are divesting or filling out product lines and technologies for newly honed strategies in the second half of this decade.

Solid State Technology announced today that its premier semiconductor manufacturing conference and networking event, The ConFab, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017. A 30% increase in attendance in 2016 with a similar uplift expected in 2017, makes the venue an ideal meeting location as The ConFab continues to expand.

    

For more than 12 years, The ConFab, an invitation-only executive conference, has been the destination for key industry influencers and decision-makers to connect and collaborate on critical issues.

“The semiconductor industry is maturing, yet opportunities abound,” said Pete Singer, Editor-in-Chief of Solid State Technology and Conference Chair of The ConFab. “The Internet of Things (IoT) is exploding, which will result in a demand for “things” such as sensors and actuators, as well as cloud computing. 5G is also coming and will be the key technology for access to the cloud.”

The ConFab is the best place to seek a deeper understanding on these and other important issues, offering a unique blend of market insights, technology forecasts and strategic assessments of the challenges and opportunities facing semiconductor manufacturers. “In changing times, it’s critical for people to get together in a relaxed setting, learn what’s new, connect with old friends, make new acquaintances and find new business opportunities,” Singer added.

Dave Mount

David Mount

Solid State Technology is also pleased to announce the addition of David J. Mount to The ConFab team as marketing and business development manager. Mount has a rich history in the semiconductor manufacturing equipment business and will be instrumental in guiding continued growth, and expanding into new high growth areas.

Mainstream semiconductor technology will remain the central focus of The ConFab, and the conference will be expanded with additional speakers, panelists, and VIP attendees that will participate from other fast growing and emerging areas. These include biomedical, automotive, IoT, MEMS, LEDs, displays, thin film batteries, photonics and advanced packaging. From both the device maker and the equipment supplier perspective, The ConFab 2017 is a must-attend networking conference for business leaders.

The ConFab conference program is guided by a stellar Advisory Board, with high level representatives from GLOBALFOUNDRIES, Texas Instruments, TSMC, Cisco, Samsung, Intel, Lam Research, KLA-Tencor, ASE, NVIDIA, the Fab Owners Association and elsewhere.

Details on the invitation-only conference are at: www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For details on attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

By Ted Shafer, Business Manager, Mature Product Sales, ASML

Ted Shafer of ASML reports on the highlights from the ≤200mm manufacturing session during SEMICON West, organized by the SEMI Secondary Equipment and Applications Special Interest Group. Your next opportunity to catch up on latest trends on ≤200mm manufacturing trends and its impact on the secondary equipment and applications market is SEMICON Europa 2016 and the Secondary Equipment Tech Arena session. 

Wednesday July 13th at SEMICON West a seminar and panel discussion were held to discuss the longevity and growth of the 200mm equipment market, and responses from IDMs, OEMs and 3rd parties to the challenges this growth presents.

Tim Tobin of Entrepix was the first speaker.  Entrepix is a premier 3rd party refurbisher of CMP and other process equipment.  Tim was the first to remark on a phenomenon that the other speakers and panelists also noted: a huge portion of the die in the devices we use daily do not require state of the art 300mm manufacturing.  For example, 60% – 80% of the chips in your smartphone or tablet are manufactured on 200mm – or smaller – wafers.  These wafers are created using mature equipment, which is frequently purchased from the secondary market, often from refurbishers such as Entrepix.

SEMI’s Christian Dieseldorff next provided a great overview of 200mm market trends, titled “200mm Fab: Trends, Status, and Forecast”.  Driven by the growth of IoT (Internet of Things), new 200mm fabs are being built and additional capacity is being added at existing fabs.  Key take-away is that after peaking in 2006, then declining for several years, 200mm wafer starts per month are now forecasted to exceed 2006’s level of 5.4M by 2019.  The question on everyone’s mind is, once that level is exceeded, where will the tools come from to manufacture those wafers?

200mm-image1

Pierric Gueguen of Yole spoke of the increased adoption of exotic substrates like GaN, Sapphire and Silicon Carbide.  These substrates provide many performance advantages, such as lower power consumption, faster switching speed, and high temperature resistance.  Yet the substrates cannot scale to 12”, and sometimes not to 8”.  So the increased adoption of these substrates is driving additional demand for 150mm/200mm tools.

As a counter-point to the 200mm discussions, Karen Erz of Texas Instruments gave a very well-received presentation on TI’s pivot to 300mm for analog, which has traditionally been manufactured on 200mm wafers.  A key to TI’s success is to embrace without fear buying opportunities for used equipment when they present themselves.  TI does not compete at the leading edge – their minimum feature size is 130nm – and thus mature, pre-owned, cost-effective equipment is always their first choice.  In fact, surplus 300mm is often more available, and less expensive, than comparable 200mm tools.  TI capitalized on the bankruptcies of the 300mm fabs of Qimonda Dresden, Qimonda Richmond, and PROMOS, also surplus tools at Powerchip, to scoop up large batches of inexpensive 300mm tools.  They continue to buy surplus 300mm tools when they come on the market, even in advance of actually requiring the tools.  As a result, 92% of RFAB’s analog production is done with pre-owned 300mm equipment.

Emerald Greig of Surplus Global, in addition to organizing the seminar, also provided a well-researched presentation on surplus equipment trends, titled “The Indispensable Secondary Market”.  Surplus Global is one of the largest surplus equipment traders, and they track the used equipment market very closely.  Emerald discussed how the supply of tools per year is trending dramatically downwards.  In 2009 they saw 6,000 tools come on the market, and that run-rate has steadily decreased to the point where by last year it was under 1,000/year.  This year we are at just 600.

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AMAT’s John Cummings provided the first OEM perspective on the 200mm market.  John showed how over 70% of the chips in the segments of automotive, wearables and mobile are produced on <=200mm wafers.  These segments are growing – for example a BMW i3 contains an astonishing 545 total die, and 484 of them are manufactured on <=200mm wafers.   AMAT reports that there are not enough used 200mm tools on the market to support the demand, and thus AMAT supplies their customers with new 200mm tools to augment the upgrades and refurbs they perform on pre-owned tools.  AMAT also provides new functionality for their mature 200mm products, increasing their usefulness and extending their lifetime.

Finally there was the OEM panel discussion, consisting of Kevin Chasey of TEL, David Sachse of LAM, Hans Peters from Ebara, and Ted Shafer of ASML.  Emerald Greig of Surplus Global provided some initial questions and solicited additional ones from the audience.   The OEMs echoed one common theme of the presentations, that 200mm demand is robust, and core tools are increasingly hard to find.  TEL additionally noted that China is a growing player in this market, and that OEMs must now support their 200mm product lines much longer than initially planned.  LAM said that 200mm core supply is so tight that the prices are rising above even comparable 300mm cores.  In response, LAM augments the supply of used tools by creating new 200mm tools.  Ebara added that the core tools coming on the market are often undesirable first-generation tools or tools in very bad condition.  On the other hand, this creates a role for the OEM, who has the expertise to make these tools production-worthy.  ASML noted that many of their larger 200mm customers are considering a migration from the PAS 5500 platform to ASML’s TWINSCAN platform for 200mm production.  Although developed for 300mm, and in general larger and more expensive than the 200mm 5500 series, ASML has spent the last 15 years making TWINSCANs increasingly productive and reliable, to the point where they often offer superior cost of ownership at 200mm than ASML’s 5500 platform.  Furthermore, customers buying TWINSCAN for 200mm production have an easy upgrade to 300mm when/if their plans call for it.

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In summary, the seminar showcased a robust exchange of ideas, where the presenters and panelists examined the resurgent 200mm market, and described many solutions to the common challenge of limited and expensive 200mm cores.

Attend SEMICON Europa and the Secondary Equipment & Applications session on October 26 to find out the latest trends and discuss in what areas OEMs, IDMs and secondary  market operators can cooperate more closely to improve sustainable access to legacy manufacturing equipment.

Find out more about SEMI’s Secondary Equipment and Applications Special Interest Group and the Secondary Equipment Legacy Management Program that is currently under development. For more information and to get involved, contact [email protected] (Ms. Rania Georgoutsakou, Director Public Policy for Europe, SEMI).

By Zvi Or-Bach, President & CEO, MonolithIC 3D Inc.

As we have predicted two and a half years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.

Our March 2014 blog Moore’s Law has stopped at 28nm has recently been re-confirmed. At the time we wrote: “From this point on we will still be able to double the amount of transistors in a single device but not at lower cost. And, for most applications, the cost will actually go up.” This reconfirmation can be found in the following IBS cost analysis table slide, presented at the early Sept FD-SOI event in Shanghai.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

As reported by EE Times – Chip Process War Heats Up, and quoting Handel Jones of IBS “28nm node is likely to be the biggest process of all through 2025”.

IBS prediction was seconded by “Samsung executive showed a foil saying it believes 28nm will have the lowest cost per transistor of any node.” The following chart was presented by Samsung at the recent SEMICON West (2016).

Zvi 2

And even Intel has given up on its “every two years” but still claims it can keep reducing transistor cost. Yet Intel’s underwhelming successes as a foundry suggests otherwise. We have discussed it in a blog titled Intel — The Litmus Test, and it was essentially repeated by SemiWiki’s Apple will NEVER use Intel Custom Foundry!

This discussion seems academic now, as the actual engineering costs of devices in advanced nodes have shown themselves to be too expensive for much of the industry. Consequently, and as predicted, the industry is bifurcating, with a few products pursuing scaling to 7nm while the majority of designs use 28nm or older nodes.

The following chart derived from TSMC quarterly earnings reports was published last week by Ed Sperling in the blog Stepping Back From Scaling:

Zvi 3

Yes, the 50-year march of Moore’s Law has ended, and the industry is now facing a new reality.

This is good news for innovation, as a diversity of choices helps support new ideas and new technologies such as 3D NAND, FDSOI, MEMS and others. These technologies will enable new markets and products such as the emerging market of IoT.

A good opportunity to learn more about these new scaling technologies is the IEEE S3S ’16, to be held in the Hyatt Regency San Francisco Airport, October 10th thru 13th, 2016. It starts with 3D and FDSOI tutorials, the emerging technologies for the IC future. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D, and three leading researchers from an imec, MIT, and Korea university collaboration will present their work on advanced monolithic 3D integration technologies. Many other authors will discuss their work on monolithic 3DIC and its ecosystem, in addition to tracks focused on SOI, sub-VT and dedicated sessions on IoT.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, announced worldwide sales of semiconductors reached $27.1 billion for the month of July 2016, an increase of 2.6 percent compared to the previous month’s total of $26.4 billion. July marked the global market’s largest month-to-month sales increase since September 2013, though sales were down 2.8 percent compared to the July 2015 total of $27.9 billion. Underscoring the welcome uptick, month-to-month sales increased in all regional markets for the first time since October 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The modest increase in global semiconductor sales in July was the global market’s largest month-to-month growth in nearly three years, an encouraging sign of potentially stronger sales during the remainder of 2016 and beyond,” said John Neuffer, president and CEO, Semiconductor Industry Association. “After months of lagging sales, the Americas region was a bright spot in July, posting 3.3 percent growth to lead all regional markets. Meanwhile, most major semiconductor product categories saw increased sales in July compared to the previous month, with DRAM leading the way with 7.1 percent growth.”

In addition to the month-to-month growth in the Americas, sales also increased in China (3.2 percent), Japan (3.1 percent), Asia Pacific/All Other (1.8 percent), and Europe (0.7 percent). Year-to-year sales increased in China (4.7 percent), but dropped in Japan (-1.1 percent), Europe (-4.9 percent), Asia Pacific/All Other (-6.8 percent), and the Americas (-7.5 percent).

“As Congress returns to Washington this week, we urge policymakers to work together to advance initiatives that promote growth and innovation in the semiconductor industry and throughout the U.S. economy,” Neuffer said. “One such measure is the Trans-Pacific Partnership (TPP), a landmark agreement that would tear down barriers to trade with Pacific-Rim countries. Congress should do what’s right for U.S. businesses, consumers, and our economy and approve the TPP.”

To find out how to purchase the WSTS Subscription Package, which includes comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, please visit http://www.semiconductors.org/industry_statistics/wsts_subscription_package/.

July 2016 GSR table and graph