Category Archives: Metrology

Rudolph Technologies, Inc. (NYSE: RTEC) announced today that it has received orders for 12 of its Dragonfly™ G2 system, just months after releasing the product. Several systems were delivered in the fourth quarter to the largest OSAT where the Dragonfly G2 systems displaced incumbent 3D technology and retained the Company’s market leadership in 2D macro inspection. The remaining systems will ship in the first half of 2019 to OSAT, IDM, and Foundry customers who are adopting the Dragonfly G2 platform for its high productivity in two-dimensional (2D) inspection, and its accuracy and repeatability in three-dimensional (3D) inspection of the smallest copper pillars. The Company expects additional adoptions of the Dragonfly G2 system across multiple key market segments in the first half of 2019, which validates Rudolph’s collaborative R&D approach with its key customers.

The new Dragonfly G2 platform delivers up to 150% improvement in productivity over legacy systems as well as exceeds competitive system throughputs. Its modular architecture provides a flexible platform with plug-and-play configurability to combine 2D with 3D Truebump™ Technology for accurate copper pillar/bump height measurements. Clearfind™ Technology detects non-visual residue defects and advanced sensor technology measures 3D features and CD metrology. Additionally, the Dragonfly G2 platform has been specifically architected to allow the measurement, data collection, and analysis of bump interconnects nearing 100 million bumps per wafer using Rudolph’s Discover® software and advanced computing architecture.

“We are pleased that our leading-edge customers across multiple market segments are quickly recognizing the value of the Dragonfly G2 system,” said Michael Plisinski, chief executive officer at Rudolph. “Today’s interconnects for advanced memory are now at or below five microns, which require higher accuracy and repeatability versus standard copper pillar bumps. With approximately 65 wafer-level packages in today’s high-end smartphones, a single weak interconnect or reliability failure can result in a high cost of return, driving our customers’ need for the enhanced process control performance. Defect sensitivity, resolution, and productivity are combined in the Dragonfly G2 system to deliver a capability and cost of ownership that is unparalleled in the competitive space.”

By Paul Trio

SCIS is a SEMI Technology Community that tackles critical component defectivity for the semiconductor manufacturing industry. The organization develops test methods for measuring defects in these critical components. Originally, this SEMI community was looking at challenges surrounding sub-10nm process nodes, but our constituents – Integrated Device Manufacturers (IDMs), capital equipment OEMs, and (sub)component suppliers – felt that the immediate need was for standards that would apply to process nodes that are already being used for volume semiconductor device manufacturing.

IDMs need ways to tell their supply chain how defects attributable to these critical components factor into the overall process-node defect budgets and wafer-contamination limits. Chipmakers and IDMs needed to start with a baseline: How problematic are existing critical components in the overall fab systems and how do these contaminants contribute to defects and how do they affect overall process yields?

These questions must be answered for every component in the fab’s process line including the drums that hold the fab chemistries, fluid delivery systems, and components used in the wafer-processing chamber. All of these critical fab-line components come into contact with each manufactured wafer, in one way or another, and each is a suspect with respect to contamination, defects, and yield problems. SCIS develops test methods for these fab-line critical components testing that are used to identify the defects caused by these components and for establishing baselines.

SCIS has seven working groups dealing with various critical components. Each is developing various test methods for many critical fab-line components. There are many facets with respect to testing each of these critical components.

Take something as simple as a seal, such as an FFKM (perfluoroelastomer, made from polymers) seal. These seals are ubiquitous in fab lines. In harsher environments, such as inside of a processing chamber, these seals are exposed to high temperatures and harsh chemistries. Different FFKM seals will have different characteristics such as thermal resistivity and chemical resistance, depending on customer specifications, and can also vary from one manufacturer to another. In addition, these characteristics can change depending on environmental conditions – or just the passage of time.

SCIS looks at defect traits from the perspective of each component in the fab line and decides which of the components’ parameters contribute most to process defects. Initially, the SCIS Seals & Valves Group collected a list of seal-related issues or parameters. The working group then cross-checked these parameters against different manufacturing processes used in the fab including ALD (atomic layer deposition) and CVD (chemical vapor deposition). Some processes are harder on seals than others. Then the working group prioritized these various parameters according to their contribution to the overall process defect budget. IDMs provided important input during these steps because they work with these seals on a daily basis. At this point, the SCIS working group had a prioritized list of parameters, vetted by various stakeholders in the semiconductor manufacturing industry. The group then set to develop standardized measurement methods for these critical parameters.

Based on this work, the SCIS Seals & Valves Group has already published two documents. The first is a standard that specifies methods for testing seal-induced impurities such as ashing (analysis of metals content of the ash) and TOC (total organic content).

The second document published by the Seals & Valves Group is a guide that documents BKMs (best known methods) for handling seals – from the moment they’re cured in an oven to packaging, shipping, handling in a fab, and installation – a to reduce contamination problems during use. For example, some seals are sensitive to light. Some polymer seals degrade when they come into contact with IPA (isopropyl alcohol), which is often used for prepping. A degraded seal can emit contamination particles during processing, which will cause yields to fall. (This latter bit of information came directly from a major IDM, which demonstrates the invaluable role that users of these components can play in the development of testing standards.)

The Seals & Valves Group’s current work focuses on developing a standard for measuring seal leak rates. This standard will define test methods for evaluating a seal’s ability to maintain pressure under vacuum. Although there are well-established standard for testing seal CSR (compressive stress relaxation) in the aerospace industry, there’s no such standard for the semiconductor industry. So originally, the Seals & Valves Group tried to tackle that challenge by developing a similar standard for SEMI’s constituents. However, a more practical and immediate parametric challenge turned out to be seal leakage rates.

Installed seals are exposed to high temperatures and harsh chemistries in the semiconductor fabrication process. The Seals & Valves Group decided to develop a test method that would determine how well seals perform over time with respect to leakage rates as the seals are exposed to cyclic harsh conditions. The goal is to simulate the working conditions for these seals, as closely as possible and in a repeatable manner.

There are, of course, some challenges associated with this work. For example, IDMs and equipment OEMs don’t want to reveal their exact process conditions as they are proprietary. So the Seals & Valves Group took a step back and focused on developing a test method based solely on exposure to elevated temperatures.

Development of this thermal test requires the design of a standardized test jig to help ensure consistent, repeatable tests, shown in Figure 1.

Figure 1: Elastomer seal test jig developed by the SCIS Seals & Valves Group.

The seal under test, shown in red in Figure 1, sits at the center of the jig. A second seal, shown in green, is used to seal the actual test environment. Two thermocouples in the jig’s top and bottom monitor of the temperature inside of the jig. There are gas and purge lines for controlling the ambient pressures on either side of the seal under test.

Figure 2 illustrates how the jig is connected to the gas sources.

Figure 2: The Seals Test Jig is connected to helium and nitrogen gas sources and to a calibrated leak (vacuum) line.

The seals leak test is based on a helium leak test. Helium is one of the smallest atoms so it will leak through just about any small gap and, with time, permeate through the material as well. In addition, helium is inert, and testing for helium using a mass spectrometer is a well-established technique for leak testing. Helium leak testing can be one thousand to one million times more sensitive than using mechanical, pressure-decay test techniques. The jig’s nitrogen lines serve to purge the test chambers of helium between leak tests.

Developing just a test jig is not sufficient. The Seals & Valves Group also developed a test sequence for using the jig. There were no existing standard, so the group needed to use its knowledge of the seals’ composition and operating conditions to develop certain test parameters. For example, the group elected to use 200°C as the maximum temperature for the high-temperature portion of the test because FFKM seals start to degrade at 250°C.

At this point, the Seals & Valves Group has gone through several iterations of a proposed test sequence. There was some initial reluctance to provide detailed inputs, but after a few iterations of the proposed method (and an understanding that this would become an industry standard to hold suppliers accountable), inputs have become more forthcoming.

This is an excellent example that demonstrates why it’s so important for SCIS working groups to get chipmakers, IDMs, component vendors, and even feedstock materials vendors to participate in these standardization efforts. Standards are far more useful if they’re based on real-world conditions.

Currently, the SCIS Seals & Valves Group is working towards finalizing the seals-leak test sequence. The jig has been designed in AutoCAD and a prototype will soon be manufactured. Although the test and jig have been developed with significant industry participation, the validity of the test has yet to be determined. The validity will be verified though Alpha testing before the jig design and test method are incorporated into a standard.

However, SEMI is not a test house. It’s a facilitator. The testing will therefore be performed by a neutral third party capable of carrying out the test under fab-like conditions. SEMI’s role is to work with different testing entities such as SUNY Polytechnic Institute in Utica, New York or IMEC in Belgium.

SEMI will solicit bids for this work through its SCIS Executive Advisory Committee, which consists of C-level executives from device makers, semiconductor capital equipment OEMs, and major critical component suppliers. This project has leveraged many of the relationships that SEMI has developed over the years and has broken new ground in standards making for SCIS and for SEMI.

For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].

By Lynnette Reese, Editor-in-Chief, Embedded Intel® Solutions

According to SEMI (semi.org), the global semiconductor revenue forecast for the second half of 2018 was doubled from 7.5 to 15 percent, a substantial growth. The semiconductor industry has seen cycles of growth and stagnation before, as innovative new products peak and decline before new technologies come out to drive growth from another direction. The wide adoption of personal computers marked great growth in semiconductors; a market that has been dominated by Intel for decades. When the PC market began to mature, a period of stagnation was followed by the mobile computing era. Companies like Qualcomm and MediaTek emerged as key players in the mobile industry. However, both computer and mobile sectors are now sustainable, but not growing appreciably.

Figure 1: Entegris works with automakers and mainstream fabs to investigate reducing contaminants and particles that don’t affect yield yet cause critical problems in long-term reliability. (Image courtesy of Entegris, ©2018).

Recently, multiple growth engines have kicked in for semiconductors, driving a new era of growth. Growth drivers include data centers, a growing “economy of data,” artificial intelligence, virtual reality, autonomous vehicles, and increasing automation in industrial applications, particularly in the Internet of Things (IoT) and robotics. The concurrent emergence of several new markets and applications has prompted a high demand; from leading edge chips on down to some of the legacy nodes. In turn, growth in semiconductors is driving the need for materials and better technologies for Integrated Chips (ICs).

Companies feeding the boom with materials and chemicals for making ICs are seeing growth that shows no signs of abating. One materials company, Entegris (ENTG), has recently expanded its Kulim manufacturing capacity and capabilities, adding new tooling, molding machines, and numerous updates to the assembly area so that Entegris can meet the demand for wafer handling products. Entegris is a 52-year-old company that, for context, was founded two years before Intel Corporation. Entegris provides materials and material solutions to semiconductor companies (semis). Currently, the company has about 4,000 employees with sales revenue of approximately $1.5 billion. Entegris has been expanding rapidly in recent years, achieving growth by about two to three percent above the market. The company is now viewed by most investors as a growth company than as an industrial, “cyclical business” type of company. Entegris is assisting the semiconductor industry in two ways: by helping the semis realize more advanced technologies and by providing materials for making chips.

Figure 2: Robotic handling equipment in a clean room. (Image courtesy of Entegris, ©2018)

Entegris has three divisions that address three different elements of semiconductor manufacturing. The first division provides advanced materials such as specialty chemicals, specialty gas mixtures, cleaning chemicals, deposition chemicals, specialty coatings, graphite, silicon carbide (SiC), and many other materials that fabrication plants (fabs) use to make chips. The second group at Entegris is involved in benefiting materials handling with carriers for handling wafers and photomasks, wafer and reticle handling, fluid management, sensing, control, and supply and delivery of chemicals to fabs. It is chip growth that primarily drives the growth of all Entegris’ divisions, with some growth influenced by advances in technology. The third division focuses on microcontamination control and primarily handles leading edge filtration and purification (at levels measured in parts per trillion). Microcontamination control is presently the fastest growing division at Entegris. Anything that touches the semiconductor wafer must go through a filter and purifier, whether gas, liquid, photo-resist, slurries, or other chemicals.

Figure 3: Entegris provides solutions to eliminate some of the random inferences impacting reliability. (Image courtesy of Entegris, © 2018)

Why is microcontamination control important?

Technologies continue to improve such that the industry is now producing Systems-on-chip (SoCs) at the 7 nm node and is headed to 5 nm. At such a scale, any particle or contaminants can make a chip fail. Enterprises like Entegris’ microcontamination control group are the last line of defense against contaminants for all chipmakers. Entegris works with automakers and mainstream fabs to investigate reducing some of the contaminants and particles that are not affecting yield yet are causing critical problems in long-term chip reliability.

According to Wenge Yang, Vice President of Marketing Strategy at Entegris, “Many existing and mainstream fabs are yielding high 90 percent range. However, we recently found that particles that are small enough to not cause a reduction in chip yield – can still cause reliability issues down the road. This has triggered Entegris to become an industry advocate on a new effort to reduce contaminants even further than has been practiced up to now.”

A Hot Topic

Entegris spotted a trend emerging about a year or two ago as semis began rooting out causes affecting long-term chip reliability that included microcontamination that did not affect yield but could affect a chips’ long-term reliability. There’s no greater concern for reliability than in autonomous cars; it’s become a hot topic.

The Society of Automotive Engineers (SAE) International issued a standard (J3016) that defines six levels of automation for self-driving cars. Level zero has no automation whatsoever. Adaptive cruise control is a Level one feature. Level two specifies partial automation. Level three defines conditional automation, such as Tesla’s Autopilot. Level four demonstrates a high level of automation where the car can operate without human oversight under certain conditions. Level five is full automation with no human involvement.

“One of the most interesting things we have seen is that with the growth of some specific sectors, the design and manufacturing challenge is changing,” Wenge affirms. “One example is in the automotive industry. If an automobile used only two or 300 chips total, the failure rate is not causing that much of a headache as it does if you have 10,000 chips in one car.”

Level Five autonomous cars may have as many as 10 LiDAR systems around the car, gathering data and processing signals and images in real-time, with low latencies. A fully autonomous car might have 10,000 ICs with 50 percent of the cost of the car sunk into the electronics. With that many chips in one autonomous vehicle, automakers begin to parallel NASA-level care in design and manufacturing, but without the added safety of redundant systems due to cost and size constraints. Add to this pressurized scenario the harsh automotive environment with extreme temperatures and constant, heavy vibration.

Figure 4: Autonomous Waymo Chrysler Pacifica Hybrid minivan undergoing testing in Los Altos, California, November 2017. Credit: Dllu, CC BY-SA 4.0.

“With these many chips in each car, if you have a failure rate of one chip out of one million, then several hundred cars might fail on the roads every single day,” states Wenge. The resulting repairs, medical bills, and lawsuits would be costlier than fixing the reliability issue at the outset. “For Entegris, the intrinsic need for increased reliability is an excellent opportunity.”

The military, aerospace, and avionics industries commonly employ redundant systems. However, the automotive industry cannot afford redundant systems, which means that we must improve the single systems’ reliability. The Level Five autonomous car sends processed data feeds into a central computer that decides whether the car should brake, slow down, accelerate, and so forth. If any component in any autonomous automotive systems fails, the car may not collect crucial data.  If the car has made a decision, it may be unable to execute on it. The possibility for failure is multiplied as automakers load thousands of ICs in a single car.

As Wenge points out, “Autonomous car makers start to realize, ‘If I put that many chips into the car, I run the risk of reliability everywhere.’ Of greater concern are chips that have passed on down the line as ‘good’ in a 100 percent yield batch…but can still fail in the field. This is how the topic of detailed reliability gets triggered.”  The design process for automotive applications must be accompanied by very high awareness of the reliability consequences. States Wenge, “Entegris is providing solutions to eliminate some of the random inferences impacting reliability.

Wenge Yang, Ph.D. Vice President, Market Strategy Dr. Yang joined Entegris in 2012 to serve as the Vice President of Market Strategy. In his role, he is responsible for Entegris product and market strategy, market research and market trend analysis, strategic marketing, and the company’s strategic technology roadmap. Before joining Entegris, Dr. Yang was an equity research analyst at Citigroup covering the semiconductor equipment and materials sector. He also served in various executive roles at Advanced Micro Devices, Tokyo Electron, and two start-up companies. Dr. Yang received a Ph.D. in Materials Science and Engineering and an MBA from Rensselaer Polytechnic Institute. Master of Science degree in Mechanical Engineering from the New Jersey Institute of Technology, and a Bachelor of Science degree in Materials Science and Engineering from Shanghai Jiao Tong University.

By Junko Collins

The SEMI International Standards program is operated in all major electronics manufacturing regions including the Americas, Europe, Japan, Korea, Taiwan and China to increase the manufacturing efficiency and interoperability. More than 5,000 volunteers representing over 2,000 companies work in 20 global technical committees and over 200 task forces to find solutions to common technology challenges.

At SEMICON Japan 2019 – December 12-14 at Tokyo Big Sight, Tokyo – SEMI recognized two industry veterans active in the Japan chapter for their longtime contributions to the SEMI International Standards program. The award ceremony took place on December 13 with 56 Standards committee members and SEMI executives including Ajit Manocha, president and CEO of SEMI, and Jim Hamajima, president of SEMI Japan, in attendance.

Hiromichi Enami of Hitachi High-Technologies Corporation and Isao Suzuki of MKS Japan Receive SEMI Japan Honor Award. Left to right: Jim Hamajima (SEMI), Ajit Manocha (SEMI), Hiromichi Enami (Hitachi High-Technologies), Isao Suzuki, James Amano (SEMI) and Mike Ciesinski (SEMI)

Contributing to SEMI Standards for more than 20 years, Mr. Hiromichi Enami of Hitachi High-Technologies Corporation has been dedicated to committee management by acting as co-chair of the Gases Technical Committee and the Facilities Technical Committee. In addition, as chairman of the division, he has strived for harmonization with other committees and regions. (The current SEMI International Standards program has no division structure).

Mr. Isao Suzuki, formerly of MKS Japan, is also a long-time contributor to the SEMI standards activities, having demonstrated his commitment to the management of the Gases Technical Committee and as a co-chair of the Facilities Technical Committee. He has also made significant efforts towards cooperation with Information & Control Committee activities related to sensor bus activities.

The SEMI Japan Honor Award is given to members who has contributed to the SEMI International Standards program as a member of Japan Regional Standards Committee or as a Global Technical Committee Japan Chapter co-chair for more than four years.

By Junko Collins, director of Standards and EHS, SEMI Japan

In microelectronic devices, the bandgap is a major factor determining the electrical conductivity of the underlying materials. Substances with large bandgaps are generally insulators that do not conduct electricity well, and those with smaller bandgaps are semiconductors. A more recent class of semiconductors with ultrawide bandgaps (UWB) are capable of operating at much higher temperatures and powers than conventional small-bandgap silicon-based chips made with mature bandgap materials like silicon carbide (SiC) and gallium nitride (GaN).

In the Journal of Applied Physics, from AIP Publishing, researchers at the University of Florida, the U.S. Naval Research Laboratory and Korea University provide a detailed perspective on the properties, capabilities, current limitations and future developments for one of the most promising UWB compounds, gallium oxide (Ga2O3).

Gallium oxide possesses an extremely wide bandgap of 4.8 electron volts (eV) that dwarfs silicon’s 1.1 eV and exceeds the 3.3 eV exhibited by SiC and GaN. The difference gives Ga2O3 the ability to withstand a larger electric field than silicon, SiC and GaN can without breaking down. Furthermore, Ga2O3 handles the same amount of voltage over a shorter distance. This makes it invaluable for producing smaller, more efficient high-power transistors.

“Gallium oxide offers semiconductor manufacturers a highly applicable substrate for microelectronic devices,” said Stephen Pearton, professor of materials science and engineering at the University of Florida and an author on the paper. “The compound appears ideal for use in power distribution systems that charge electric cars or converters that move electricity into the power grid from alternative energy sources such as wind turbines.”

Pearton and his colleagues also looked at the potential for Ga2O3 as a base for metal-oxide-semiconductor field-effect transistors, better known as MOSFETs. “Traditionally, these tiny electronic switches are made from silicon for use in laptops, smart phones and other electronics,” Pearton said. “For systems like electric car charging stations, we need MOSFETs that can operate at higher power levels than silicon-based devices and that’s where gallium oxide might be the solution.”

To achieve these advanced MOSFETs, the authors determined that improved gate dielectrics are needed, along with thermal management approaches that will more effectively extract heat from the devices. Pearton concluded that Ga2O3 will not replace SiC and GaN as the as the next primary semiconductor materials after silicon, but more likely will play a role in extending the range of powers and voltages accessible to ultrawide bandgap systems.

“The most promising application might be as high-voltage rectifiers in power conditioning and distribution systems such as electric cars and photovoltaic solar systems,” he said.

Advances in the technology of material growth allow fabricating sandwiches of materials with atomic precision. The interface between the two materials can sometimes exhibit physical phenomena which do not exist in both parent materials. For example, a magnetic interface found between two non-magnetic materials. A new discovery, published today in Nature Physics, shows a new way of controlling this emergent magnetism which may be the basis for new types of magnetic electronic devices.

Sensitive magnetic imaging detects strain tunable magnetism. Credit: Kalisky Lab

Using very sensitive magnetic probes, an international team of researchers led by Prof. Beena Kalisky, of Bar-Ilan University’s Department of Physics and Institute of Nanotechnology and Advanced Materials (BINA), has found surprising evidence that magnetism which emerges at the interfaces between non-magnetic oxide thin layers can be easily tuned by exerting tiny mechanical forces. The team also includes Prof. Lior Klein, of Bar-Ilan’s Department of Physics and BINA, and researchers from DTU (Denmark) and Stanford University (USA).

Magnetism already plays a central role in storing the increasing amount of data produced by humanity. Much of our data storage today is based on tiny magnets crammed into our memory drive. One of the promising means in the race to improve memory, in terms of quantity and speed, is the use of smaller magnets. Until today the size of memory cells can be as small as a few tens of nanometers — almost a millionth of the width of a strand of hair! Further reduction in size is challenging in three main respects: the stability of the magnetic cell, the ability to read it, and the ability to write into it without affecting its neighboring cells. This recent discovery provides a new and unexpected handle to control magnetism, thus enabling denser magnetic memory.

These oxide interfaces combine a number of interesting physical phenomena, such as two-dimensional conductance and superconductivity. “Coexistence of physical phenomena is fascinating because they do not always go hand in hand. Magnetism and superconductivity, for example, are not expected to coexist,” says Kalisky. “The magnetism we saw did not extend throughout the material but appeared in well-defined areas dominated by the structure of the materials. Surprisingly, we discovered that the strength of magnetism can be controlled by applying pressure to the material”.

Coexistence between magnetism and conductivity has great technological potential. For example, magnetic fields can affect the current flow in certain materials and, by manipulating magnetism, we can control the electrical behavior of electronic devices. An entire field called Spintronics is dedicated to this subject. The discovery that tiny mechanical pressures can effectively tune the emerging magnetism at the studied interfaces opens new and unexpected routes for developing novel oxide-based spintronic devices.

Total fab equipment spending in 2019 is projected to drop 8 percent, a sharp reversal from the previously forecast increase of 7 percent as fab investment growth has been revised downward for 2018 to 10 percent from the 14 percent predicted in August, according to the latest edition of the World Fab Forecast Report published by SEMI.

Entering 2018, the semiconductor industry was expected to show a rare fourth consecutive year of equipment investment growth in 2019. But the SEMI World Fab Forecast Report, tracking more than 400 fabs and lines with major investment projects, forecast in August a slowdown in the second half of 2018 and into the first half of 2019. Now, with recent industry developments, a steeper downturn in fab equipment is expected (Figure 1).

Figure 1

The report shows overall spending down 13 percent in the second half of 2018 and 16 percent in the first half of 2019 with a strong increase in fab equipment spending expected in the second half of 2019.

Plunging memory prices and a sudden shift in companies’ strategies in response to trade tensions are driving rapid drops in capital expenditures, especially among leading-edge memory manufacturers, some fabs in China, and some projects for mature nodes such as 28nm. Industry sectors expecting record-breaking growth in 2019, such as memory and China, are now leading the decline.

Following a sharp fall in NAND flash pricing earlier this year, DRAM prices in the fourth quarter of 2018 began to soften, seemingly ending the two-year DRAM boom. Inventory corrections and CPU shortages continue, prompting predictions of even steeper price declines.

Memory makers have quickly responded to changing market conditions by adjusting capital expenditures (capex), and tool orders have been put on hold. DRAM spending may see an even deeper correction in 2019 while NAND flash-related investment could also suffer a double-digit decline next year.

A review of spending by industry sector reveals that, while memory capital expenditures were expected to grow by 3 percent in 2019, they are now forecast to drop by 19 percent year-over-year (YOY). DRAM is hit the hardest with a fall of 23 percent, while 3D NAND will contract 13 percent in 2019.

China and Korea are suffering the largest drops in spending since the August report.

China fab spending falls

Projections for equipment spending in China in 2019 have been revised from US$17 billion in August to US$12 billion, with multiple factors at play including a slowing memory market, trade tensions, and delays in some project timelines.

SK Hynix is expected to slow DRAM expansion in 2019. GLOBALFOUNDRIES reconsidered its plan for the Chengdu fab, delaying the ramp. SMIC and UMC are slowing spending. The Fujian Jinhua DRAM project has been put on hold.

Korea fab spending down

In August, SEMI forecast that Korea fab equipment spending would decline by 8 percent, to US$17 billion, in 2019 – a projection that has now been slashed to US$12 billion, a drop of 35 percent YoY. Samsung began to reduce equipment investments in the fourth quarter of 2018, and the spending cuts are expected to continue into the first half of 2019. Samsung’s largest projects to be hit are P1 (slowdown) and the ramp of P2 Phase 1 (delayed). Adjustments to the S3 schedule are also expected.

Not all memory makers cut capital expenditures

While SEMI’s detailed, fab-level data show that some memory makers will scale back capital expenditures for 2019, one company stands out. Micron will increase capex for FY19 to US$10.5 billion, up about 28 percent, or $8.2 billion, from FY18. Micron plans to expand and upgrade facilities, invest less in NAND in FY19 than in FY18, and anticipates no new wafer starts.

Outlook still upbeat for mature technologies

In other sectors, especially for non-leading-edge and specialty technologies, some fabs are still increasing investments (Figure 2).

Figure 2

Opto – especially CMOS image sensors – shows strong growth, surging 33 percent to US$3.8 billion in 2019. Micro (MPU, MCU and DSP) is expected to grow more than 40 percent in 2019 to US$4.8 billion. Analog and mixed signal investments also show strong growth – 19 percent – in 2019, bringing spending to US$660 million. The foundry sector, the second largest product segment in total investments at US$13 billion, shows a 10 percent rise in 2019.

The recent three-year boom in the semiconductor market was chiefly driven by the memory sector (e.g. DRAM and 3D NAND flash). One company, Samsung, invested at unprecedented levels, lifting the entire industry. Other memory makers rode the wave of the boom cycle by boosting investments. And China’s profile rose with its huge investments. The industry was poised for four consecutive years of revenue growth – a streak not seen since the 1990s.

Now the industry faces well-known threats of inventory correction and the trade war. Both phenomena could slow growth significantly and if both unfold in full force in tandem, the impact could be serious. The data in SEMI’s latest publication of the World Fab Forecast show that the four-year growth streak will not materialize.

Since its August 2018 publication, more than 260 updates have been made to the World Fab Forecast. The report now includes more than 1,280 records of current and 115 future front-end semiconductor facilities from high-volume production to research and development. The report covers data and predictions through 2019, including milestones, detailed investments by quarter, product types, technology nodes and capacities down to fab and project level.

The SEMI World Fab Forecast examines capital expenditure plans of individual front-end device manufacturers, while the SEMI bi-annual Semiconductor Equipment Sales Forecast is based on year-to-date data collected from equipment manufacturers and modeled off of announced capital expenditure plans of both front-end and back-end equipment manufacturers.

IC Insights is in the process of revising its forecast and analysis of the IC industry and will present its new findings in The McClean Report 2019, which will be published in January 2019.  Among the revisions is a complete update of forecast growth rates of the 33 main product categories classified by the World Semiconductor Trade Statistics organization (WSTS) through the year 2023.

Topping the chart of fastest-growing products for 2018 is DRAM, which comes as no surprise given the strong rise of average selling prices in this segment over the past two years (Figure 1).  The 2018 DRAM market is expected to show an increase of 39%, a solid follow-up to the 77% growth in 2017. The number-one position is not unfamiliar territory for the DRAM market.  It was also the fastest-growing IC segment in 2013 and 2014.

Figure 1

Remarkably, DRAM has been at the top and near the bottom of this list over the past six years, demonstrating its very volatile and cyclical nature.  IC Insights forecasts that DRAM will rank nearly last in terms of market growth in 2019, with a 1% decrease in total sales.  After two strong years of growth, Samsung, SK Hynix, and Micron—the world’s three primary DRAM suppliers—have expanded their manufacturing capacity and are beginning to ramp up production, bringing some much needed relief to strained supplies, especially for high-performance DRAM devices. At the same time, shipments of large-scale datacenter servers, which were a primary catalyst for much of the recent DRAM market surge, have begun to ease as uncertain economic and trade conditions factor into decisions about continuing with the strong build out.

NAND flash joins DRAM as another memory segment that has enjoyed very strong growth over the past two years (Figure 2).  Solid-state computing, particularly, has been a key driver for high-density, high-performance NAND flash even as mobile applications continue to be a significant driver. Meanwhile, automotive and computing special purpose logic devices have also been strong performers the past two years.  The top five IC markets listed for 2018 are the only product categories that are expected to surpasses the 17% growth rate of the total IC market this year.

Figure 2

The full list of IC product rankings and forecasts for the 2019-2023 timeperiod is included in The McClean Report 2019, which will be released in January 2019.

By Walt Custer

Global growth by electronic sector

Now that most companies in our sector analyses have reported their calendar third quarter 2018 financial results, we have final or 3Q’18/2Q’17 growth estimates for the world electronic supply chain (Chart 1). We estimate electronic equipment grew 6.7% on a U.S. dollar-denominated basis.

Source: Custer Consulting Group based on consolidated financial reports of public companies

Electronic equipment growth has peaked for this current business cycle (Chart 2), dropping from +11.1% in the second quarter to 6.7% in the third quarter. Most of the supply chain is responding to this slowing.

Semiconductors, SEMI equipment an Taiwan chip foundries

While the most recent growth rates in Charts 1 & 2 are for the third quarter, October and November growth is included in Chart 3.  Foundry growth was +4.6% in November, world semiconductor shipments eased to +12.7% in October and SEMI capital equipment slipped to +10% also in October. The days of the +30% growth rates are behind us for this current business cycle!

Sources: SIA; SEMI; financial reports of Taiwan listed foundry companies

Global semiconductor growth outlook for 2019

The World Semiconductor Trade Statistics Organization in conjunction with the SIA just updated the chip shipment forecasts for 2018 and 2019 (Chart 4). World semiconductor shipments were estimated to have climbed 15.9% (in U.S. dollars) in 2018 but are predicted to slow to a +2.6% rate in 2019.

Source: www.wsts.org, www.semiconductors.org

Looking forward

The Global Manufacturing PMI (Chart 5) leveled out in November but remained well below its December 2017 high.  This translates to a slower but still positive world expansion in the short term. By region (Chart 6), U.S. growth remains robust, Japan picked up, Europe continues to decelerate, China is near zero growth and Taiwan and South Korea are contracting.

Source: www.markiteconomics.com

ll eyes are on the global economy, Brexit, trade wars and bizarre political wrangling. 2019 could be a very volatile year!

Walt Custer of Custer Consulting Group is an analyst focused on the global electronics industry.

Releasing its Year-End Total Equipment Forecast at the annual SEMICON Japan exposition, SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase 9.7 percent to $62.1 billion in 2018, exceeding the historic high of $56.6 billion set last year. The equipment market is expected to contract 4.0 percent in 2019 but grow 20.7 percent to reach $71.9 billion, an all-time high.

The SEMI Year-end Forecast predicts wafer processing equipment will rise 10.2 percent in 2018 to $50.2 billion. The other front-end segment – consisting of fab facilities equipment, wafer manufacturing, and mask/reticle equipment – is expected to increase 0.9 percent to $2.5 billion this year. The assembly and packaging equipment segment is projected to grow 1.9 percent to $4.0 billion in 2018, while semiconductor test equipment is forecast to increase 15.6 percent to $5.4 billion this year.

In 2018, South Korea will remain the largest equipment market for the second year in a row. China will rise in the rankings to claim the second spot for the first time, dislodging Taiwan, which will fall to the third position. All regions tracked except Taiwan, North America, and Korea will experience growth. China will lead in growth with 55.7 percent, followed by Japan at 32.5 percent, Rest of World (primarily Southeast Asia) at 23.7 percent, and Europe at 14.2 percent.

For 2019, SEMI forecasts that South Korea, China, and Taiwan will remain the top three markets, with all three regions maintaining their relative rankings. Equipment sales in South Korea is forecast to reach $13.2 billion, in China $12.5 billion, and in Taiwan $11.81 billion. Japan, Taiwan and North America are the only regions expected to experience growth next year. The growth picture is much more optimistic in 2020, with all regional markets expected to increase in 2020, with the market increasing the most in Korea, followed by China, and Rest of World.

The following results are in terms of market size in billions of U.S. dollars:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports:

  • Monthly SEMI Billings Report, an early perspective of the trends in the equipment market
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  • SEMI Mid-Year Forecast, an outlook for the semiconductor equipment market