Category Archives: Metrology

IC Insights will release its new 2016 McClean Report late next month.  The 2016 McClean Report will include a ranking of the top-50 semiconductor suppliers’ for 2015 as well as the top-50 fabless semiconductor suppliers.  The forecasted “post-merger” top-10 2015 IDM and fabless semiconductor suppliers are covered in this research bulletin.

Unlike the relatively close annual market growth relationship between fabless semiconductor suppliers and foundries, fabless semiconductor company sales growth versus IDM (integrated device manufacturers) semiconductor supplier growth has typically been very different (Figure 1).  In 2010, for the first and only time on record thus far, IDM semiconductor sales growth (35%) outpaced fabless semiconductor company sales growth (29%).  Since very few fabless semiconductor suppliers participate in the memory market, the fabless suppliers did not receive much of a boost from the surging DRAM and NAND flash memory markets in 2010, which grew 75% and 44%, respectively.

As shown in Figure 2, only three of the top-10 IDM semiconductor suppliers are forecast to register growth in 2015 and, in total, the top-10 IDMs are expected to display flat growth this year.  Although flat growth by the top-10 IDMs would typically be considered poor performance, it is still forecast to be a much better result than is expected from the top-10 fabless semiconductor suppliers (Figure 3).  In order to make direct comparisons for year-over-year growth, IC Insights combined the merged, or soon to be merged, companies’ 2014 and 2015 semiconductor sales regardless of when the merger occurred.

As shown, the top-10 fabless semiconductor suppliers are forecast to register a 5% decline in sales this year, five points worse than the top-10 IDMs.  It should be noted that essentially all of the decline expected for the top-10 fabless suppliers in 2015 could be attributed to the forecasted decline in Qualcomm/CSR’s sales this year.  Much of the sharp decline in Qualcomm/CSR’s sales this year is being driven by Samsung’s increasing use of its internally developed Exynos application processor in its smartphones instead of the application processors it had previously sourced from Qualcomm.

Fig 1

Fig 1

Fig 2

Fig 2

Fig 3

Fig 3

Application processor sales to fabless/system house Apple from pure-play foundry TSMC are included in the fabless company sales ranking under the “Apple/TSMC” moniker.  Application processor sales supplied to Apple from IDM-foundry Samsung are included as part of Samsung’s logic IC sales.

As mentioned in the title of this Research Bulletin, 2015 could end up being only the second year ever, after 2010, in which the IDM semiconductor suppliers outpace the fabless semiconductor suppliers with regard to year-over-year growth.  Whether this actually takes place will be revealed from IC Insights’ extended compilation of the IDM and fabless semiconductor company rankings for the 2016 McClean Report.

Physicists at the Technical University of Munich, the Los Alamos National Laboratory and Stanford University (USA) have tracked down semiconductor nanostructure mechanisms that can result in the loss of stored information – and halted the amnesia using an external magnetic field. The new nanostructures comprise common semiconductor materials compatible with standard manufacturing processes.

Quantum bits, qubits for short, are the basic logical elements of quantum information processing (QIP) that may represent the future of computer technology. Since they process problems in a quantum-mechanical manner, such quantum computers might one day solve complex problems much more quickly than currently possible, so the hope of researchers.

In principle, there are various possibilities of implementing qubits: photons are an option equally as viable as confined ions or atoms whose states can be altered in a targeted manner using lasers. The key questions regarding their potential use as memory units are how long information can be stored in the system and which mechanisms might lead to a loss of information.

A team of physicists headed by Alexander Bechtold and Professor Jonathan Finley at the Walter Schottky Institute of the Technical University of Munich and the Cluster of Excellence Nanosystems Initiative Munich (NIM) have now presented a system comprising a single electron trapped in a semiconductor nanostructure. Here, the electron’s spin serves as the information carrier.

By evaporating indium gallium arsenide onto a gallium arsenide substrate TUM physicists created nanometer-scale hills, so-called quantum dots. An electron trapped in one of these quantum dots can be used to store information. Hitherto unknown memory loss mechanisms could be switched off by applying a magnetic field. Credit:  Fabian Flassig / TUM

By evaporating indium gallium arsenide onto a gallium arsenide substrate TUM physicists created nanometer-scale hills, so-called quantum dots. An electron trapped in one of these quantum dots can be used to store information. Hitherto unknown memory loss mechanisms could be switched off by applying a magnetic field. Credit:
Fabian Flassig / TUM

The researchers were able to precisely demonstrate the existence of different data loss mechanisms and also showed that stored information can nonetheless be retained using an external magnetic field.

Electrons trapped in a quantum dot

The TUM physicists evaporated indium gallium arsenide onto a gallium arsenide substrate to form their nanostructure. As a result of the different lattice spacing of the two semiconductor materials strain is produced at the interface between the crystal grids. The system thus forms nanometer-scale “hills” – so-called quantum dots.

When the quantum dots are cooled down to liquid helium temperatures and optically excited, a singe electron can be trapped in each of the quantum dots. The spin states of the electrons can then be used as information stores. Laser pulses can read and alter the states optically from outside. This makes the system ideal as a building block for future quantum computers.

Spin up or spin down correspond to the standard logical information units 0 and 1. But, on top of this come additional intermediate states of quantum mechanical up and down superpositions.

Hitherto unknown memory loss mechanisms

However, there is one problem: “We found out that the strain in the semiconductor material leads to a new and until recently unknown mechanism that results in the loss of quantum information,” says Alexander Bechtold. The strain creates tiny electric fields in the semiconductor that influence the nuclear spin orientation of the atomic nuclei.

“It’s a kind of piezoelectric effect,” says Bechthold. “It results in uncontrolled fluctuations in the nuclear spins.” These can, in turn, modify the spin of the electrons, i.e. the stored information. The information is lost within a few hundred nanoseconds.

In addition, Alexander Bechthold’s team was able to provide concrete evidence for further information loss mechanisms, for example that electron spins are generally influenced by the spins of the surrounding 100,000 atomic nuclei.

Preventing quantum mechanical amnesia

“However, both loss channels can be switched off when a magnetic field of around 1.5 tesla is applied,” says Bechtold. “This corresponds to the magnetic field strength of a strong permanent magnet. It stabilizes the nuclear spins and the encoded information remains intact.”

“Overall, the system is extremely promising,” according to Jonathan Finley, head of the research group. “The semiconductor quantum dots have the advantage that they harmonize perfectly with existing computer technology since they are made of similar semiconductor material.” They could even be equipped with electrical contacts, allowing them to be controlled not only optically using a laser, but also using voltage pulses.

Technavio has added a new market research report on the global discrete semiconductors market, to its semiconductors portfolio. The global discrete semiconductors market is expected to grow at a CAGR of around 5% between 2015 and 2019. APAC dominates the global market, accounting for around 62% of the overall market revenue. The main reason for the high revenue contribution from this region is the high concentration of OEMs and ODMs in the region.

The new industry research report from Technavio discusses in detail the key drivers and trends responsible for the growth of this market and its sub-segments.

“The market vendors are offering various discrete power devices with diverse applications especially to reduce energy wastage. Vendors are increasing the power density, aiming towards energy conservation. More is the power density of discrete semiconductors, netter is the efficiency of these devices which help end-users in saving energy. Moreover, the depletion and rising cost of fossil fuels have made energy conservation a requirement, resulting in the augmented adoption of discrete power semiconductors over the next few years,” said Navin Rajendra, Lead Analyst, Hardware & Semiconductor, Technavio Research.

Automotive segment is the fastest growing segment of the overall discrete semiconductors market. To reduce the dependence on fossil fuels and to reduce environmental hazards, the automotive sector is shifting to hybrid vehicles. Also, these vehicles have more semiconductor content compared to traditional automobiles. This change has raised the demand and requirement for power efficiency fulfilled by the discrete power semiconductors.

The key vendors in the global discrete semiconductors market include Fairchild, Infineon, and NXP. The market is expected to witness a significant push for investments in R&D by the leading market vendors during the forecast period. The main area of vendor focus in the market is toward energy conservation. Many vendors are engrossed in increasing power density, and it is expected to positively impact the implementation of discrete power in newer application areas.

A more detailed analysis is available in the Technavio report, Global Discrete Semiconductors Market 2015-2019.

The European Commission has approved under the EU Merger Regulation the acquisition of Broadcom Corporation by Avago Technologies Limited. Both companies are global manufacturers of semiconductors. The Commission concluded that the merged entity would continue to face effective competition in Europe.

Commissioner Margrethe Vestager, in charge of competition policy, said: “Thanks to very good cooperation with the companies the Commission has been able to approve this multi-billion dollar takeover within a very short space of time while preserving effective competition in this crucial high-technology sector.”

The Commission’s investigation showed that the portfolios of the companies are mainly complementary since Broadcom makes “off-the-shelf” chips for the broadband and connectivity market segments, while Avago makes custom-built chips for special applications in the analog wireless integrated circuits, enterprise, storage and industrial segments.

Nevertheless, the Commission had some concerns about the vertical relationship created by the transaction, since Avago supplies certain intellectual property (technology for allowing fast data transmission between chips) to some of Broadcom’s competitors. The Commission’s concern was that after the takeover Avago could have had an incentive to withhold this intellectual property in order to extend the merged entity’s leading market position in the so-called “switch chips” market.

However, already during the Commission’s assessment of the case, Avago addressed these concerns by entering into commercial agreements with other “switch chip” manufacturers. These agreements will ensure that other “switch chip” manufacturers will continue to have access to the necessary intellectual property on reasonable terms. Thanks to this up-front solution, the Commission has been able to unconditionally clear the proposed transaction, which was notified on October 2, 2015.

Related news: 

Avago Technologies acquisition of Broadcom creates a new semiconductor powerhouse

Historic era of consolidation for chipmakers

North America-based manufacturers of semiconductor equipment posted $1.33 billion in orders worldwide in October 2015 (three-month average basis) and a book-to-bill ratio of 0.98, according to the October EMDS Book-to-Bill Report published today by SEMI. A book-to-bill of 0.98 means that $98 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in October 2015 was $1.33 billion. The bookings figure is 14.7 percent lower than the final September 2015 level of $1.55 billion, and is 20.3 percent higher than the October 2014 order level of $1.10 billion.

The three-month average of worldwide billings in October 2015 was $1.36 billion. The billings figure is 9.1 percent lower than the final September 2015 level of $1.50 billion, and is 14.7 percent higher than the October 2014 billings level of $1.18 billion.

“Both bookings and billings weakened for the second consecutive month; however, year-to-date bookings and billings levels remain above last year’s levels,” said Denny McGuirk, president and CEO of SEMI. “SEMI will update its 2016 equipment outlook during SEMICON Japan next month.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

  Billings
(3-mo. avg)
Bookings
(3-mo. avg)
Book-to-Bill
May 2015 $1,557.3 $1,546.2 0.99
June 2015 $1,554.9 $1,517.4 0.98
July 2015 $1,556.2 $1,587.3 1.02
August 2015 $1,575.9 $1,670.1 1.06
September 2015 (final) $1,495.0 $1,554.9 1.04
October 2015 (prelim) $1,358.4 $1,325.8 0.98

Source: SEMI (www.semi.org), November 2015

Inotera appoints new president


November 19, 2015

Inotera’s board of directors announced this week that they have approved the appointment of Mr. Rod Morgan as president, succeeding Dr. Scott Meikle. The change is effective January 1, 2016.

Mr. Morgan is currently Special Assistant of Inotera. Prior to joining Inotera, he was vice president of Procurement at Micron Technology, Inc. Before that, he served as co-executive officer of IM Flash Technologies, LLC. Mr. Morgan joined Micron in 1984 and held numerous leadership roles in manufacturing operations, including Fab Manager, Manufacturing Integration Manager, Key Equipment Group Director, and Site Director.

The board of directors announced that Dr. Pei-Ing Lee, currently serving as president of Nanya Technology Corporation, was elected to be the new chairman of the company. The election is effective November 10, 2015.

Inotera is a DRAM manufacturing venture between US memory giant Micron Technology Inc. and DRAM chipmaker Nanya Technology.

Inotera plans to fully convert all its production to 20nm chips by the end of the second quarter next year. At end of this year, the chipmaker plans to convert 80 percent of its 30nm chips into 20nm.

ON Semiconductor Corporation and Fairchild Semiconductor International Inc. today announced plans for ON Semiconductor to acquire Fairchild for $20.00 per share in an all cash transaction valued at approximately $2.4 billion. The acquisition creates a leader in the power semiconductor market with combined revenue of approximately $5 billion, diversified across multiple markets with a strategic focus on automotive, industrial and smartphone end markets.

“The combination of ON Semiconductor and Fairchild creates a power semiconductor leader with strong capabilities in a rapidly consolidating semiconductor industry. Our plan is to bring together two companies with complementary product lines to offer customers the full spectrum of high, medium and low voltage products,” said Keith Jackson, president and chief executive officer of ON Semiconductor. “The immediate EPS accretion and potential to significantly augment ON Semiconductor’s free cash flow, make the Fairchild acquisition an excellent opportunity for ON Semiconductor stockholders.”

“As part of ON Semiconductor, Fairchild will continue to pioneer technology and design innovation in efficient energy consumption to help our customers achieve success and drive value for our partners and employees around the world,” stated Mark Thompson, chairman and chief executive officer of Fairchild. “We look forward to working closely with the ON Semiconductor team to ensure a smooth transition.”

Following consummation, the transaction is expected to be immediately accretive to ON Semiconductor’s non-GAAP earnings per share and free cash flow, excluding any non-recurring acquisition related charges, the fair value step-up inventory amortization, and amortization of acquired intangibles. ON Semiconductor anticipates achieving annual cost savings of $150 million within 18 months after closing the transaction.

The transaction is not subject to a financing condition. ON Semiconductor intends to fund the transaction with cash from the combined companies balance sheet and $2.4 billion of new debt. The debt financing commitment also includes provisions for a $300 million revolving credit facility which will be undrawn at close. ON Semiconductor remains committed to its share repurchase program, and the agreed upon financing provides flexibility to continue share repurchases going forward.

Follow other industry acquisition news here.

CEA-Leti and its partners in the European FP7 project PLAT4M today announced they have built three silicon photonics platforms. The four-year project, which launched in 2013, aims at building a European-based supply chain in silicon photonics and speeding industrialization of the technology. PLAT4M, which is funded by a European Commission grant of 10.2 million euros, includes 15 leading European R&D institutes and CMOS companies, key industrial and research organizations in design and packaging, as well as end users in different application fields, to build the complete supply chain.

Midway through the project, the consortium has developed advanced technologies and tools by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration, and developing a packaging toolkit. The supply chain is based on technology platforms of Leti, imec and STMicroelectronics, supported by a unified design environment. The high level of maturity of the technology offered by these platforms makes them readily accessible to a broad circle of users in a fabless model.

Imec’s silicon photonics platform, based on 200mm substrates, has matured thanks to the PLAT4M project. The platform is based on SOI substrates with 220nm crystalline silicon on a 2,000nm buried oxide. During this project the existing fabrication processes and integration flow have been fine tuned to have stable and repeatable performance for all photonics building blocks (couplers, waveguides, phase shifters, photodetectors). This feeds the process design kit’s robust performance specifications and guarantees quality and first-time-right designs for the platform’s fabless users for high data-rate telecom and non-telecom applications. PLAT4M partners Thales, Polytec and TNO already are using the technology.

Beyond the 200mm platform, imec has pushed the limits of silicon photonics, exploiting advanced optical lithography with its 193nm immersion lithography scanner. It also has demonstrated very low propagation loss (~0.6dB/cm) for fully etched waveguides with excellent within-wafer linewidth control (standard deviation

Using the imec platform, Thales demonstrated a coherent combination of laser beams (CBC). Ultimately, this application aims at producing high-power, high-energy laser sources for sensing, industry or fundamental physics. The CBC rationale is to push the limits of single laser emitters (typically fiber amplifiers) by using a large number of amplifiers and coherently adding the output beams. The coherent addition requires locking the phase of all the amplifying channels. With the number of channels, potentially very large (from tens to thousands), an integrated technology is a major concern in terms of possible industrial products. The first generation CBC demonstrator of PLAT4M, which was packaged by Tyndall UCC, included a one-to-16 channel splitter tree, plus 16 independent thermal phase modulators. The CBC experiment showed the successful coherent addition of 16 laser beams at 1.55µm.

cea-leti supply chain

Leti has developed a new photonic platform based on 200mm SOI wafers. This process offers multilevel silicon patterning that allows the design of various passive and active devices (e.g. modulator and photodiode) with thermal tuning capability. Two AlCu levels are available for routing. A process design kit (PDK) is available for circuit design and an MPW service will be proposed in 2016. State-of-the-art performances have been demonstrated: insertion losses are below 2dB/cm for monomode waveguide and below 0.2dB/cm for multimode devices. Germanium photodiode responsivity is > 0.75A/W for a bandwidth >30GHz. Mach-Zehnder modulator VpLp is in the 2V.cm range for 2V operation with an E/O bandwidth > 25GHz. Moreover, Leti and III-V Lab have developed integrated hybrid III-V lasers and electro-absorption modulators (EAM) on silicon using a wafer-bonding technique. The hybrid lasers operate in the single-mode regime and the EAMs exhibit an extinction ratio higher than 20 dB with a drive voltage lower than 2V. Clear eye diagram has been achieved at a bit-rate of 25 Gb/s, confirming strong potential for telecom applications.

During the project, ST developed an additional silicon-photonic platform in 300mm technology to be used as an R&D tool for proof-of-concept purposes. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is designed for evaluating new devices and subsystems for demonstration. DAPHNE is a flexible platform that perfectly fits R&D needs. While developing it, ST demonstrated wavelength-division-multiplexing solutions using arrayed waveguide gratings, echelle gratings, cascaded Mach-Zehnder interferometers and side-coupled integrated spaced sequence of resonators. Some of the configurations are designed for the 100GBase-LR4 standard, and the experimental characterization results show insertion losses below 0.5dB and channel cross-talks above 25dB for a band flatness of 2nm. Furthermore, proper operation of receiver-and-transmitter blocks to be interfaced to optical devices above them has been demonstrated at 28Gbps, making use of 65nm-node technologies.

The PLAT4M WP2 work has led to a qualitative leap of the design flow for silicon photonics, allowing the photonics community to design more complex and more robust circuits. The electronics OpenAccess standard for data sharing between design-automation tools includes an extension for silicon photonics in a beta phase today. Simulation capabilities were leveraged thanks to an extensive characterization effort from the three partner fabs and thanks to the statistical data gathered for variability prediction. Paris-Sud University has studied theoretically the behavior of different phase shifters and photodetectors for a time-efficient and precise modeling. Mentor Graphics and PhoeniX Software partners have improved phase-aware routing and tool interoperability. Verification and manufacturability have reached industry-requirement standards thanks to the development of new techniques based upon the Mentor Graphics Calibre platform that delivers layout-versus-schematic comparison (Calibre nmLVS), photonic rule checks (PRC) and curvilinear-aware design-rule checks (Calibre nmDRC). Mask preparation is also improving with better pattern-density control and mask correction.

Due to their exciting properties, 2D crystals like graphene and transition metal dichalcogenides promise to become the material of the future.

BY STEFAN DE GENDT, CEDRIC HUYGHEBAERT, IULIANA RADU and AARON THEAN, imec, Leuven, Belgium.

As we enter into the era of functional scaling where the cross-roads of More-Moore and More-Than-Moore meet, the search for new devices and their enabling material comes to the forefront of technology research. 2D crystals provide very interesting form-factors with respect to traditional 3D crystals (bulk, Si, and III-V semiconductors). In this elegant 2D form, electronic structure, mechanical flexibility, defect formation, and electronic and optical sensitivity become dramatically different. Aaron Thean: “As researchers at imec explore the physics and applications of such material, it is now becoming important to find a wafer-scale path towards technology implementation and integration of these novel materials.” Working closely with research teams across universities and industry partners, the first important step for imec is to enable the flake-to-wafer transition, while concurrently exploring the material, and device-to-circuit applications. The work will build new infrastructure (e.g. epitaxy, metrology, patterning, and electrical characterizations, etc.) around it.

Graphene and beyond

A 2D material is basically formed as a regular network in two dimensions, not extending in the third dimension. It is a monolayer-type of material, where monolayer should be understood as ‘up to a few monolayers’. The most known 2D material is graphene, a crystalline monolayer of carbon atoms arranged in a hexagonal honeycomb lattice structure. Recently, the exploration of 2D materials has moved beyond graphene. Stefan De Gendt: “2D materials cover all classes of materials, from semiconductors to insulators to metals. Graphene is a prominent example of a (semi-)metal. Transition metal dichalcogenides (or MX2 with M a transition metal and X a chalcogen such as sulfur or selenium) and hexagonal boron nitrides are well known examples of 2D semiconductors and insulators, respectively.”

2D materials: the new silicon?

Many of these materials exhibit remarkable properties that can be exploited in a range of applications. Cedric Huyghebaert: “Graphene, for example, is a fantastic electronic and thermal conductor. It has a record thermal conductivity, a very high intrinsic mobility, a high current density and long mean free path of electrons. Its surface is chemically inert, it has a low surface energy and no out-of-plane dangling bonds. MX2 have versatile properties that complement those of graphene. For example, they have a wide range of bandgaps as opposed to graphene, where the bandgap is absent. In case of graphene, we have to open the bandgap by using e.g. graphene nanoribbons or bilayer graphene.”

2D materials represent interesting alternatives to Si-based transistors. Iuliana Radu: “When scaling the gate length of a traditional Si-based MOSFET, overlapping junctions lead to short channel effects which degrade transistor performance. By introducing 2D materials in the channel of the MOSFET, they could show superior immunity to short channel effects. 2D materials could therefore extend traditional CMOS scaling beyond its current limits. They are also being considered for tunnel-FET (or TFET) applications, where carrier transport happens through band-to-band tunneling. In principle, 2D materials have no dangling bonds at the interfaces. These dangling bonds are one of the main limiters for TFETs with conventional semiconductors and limit strongly their performance.”

2D materials hold promises in other domains as well. Cedric Huyghebaert: “Many applications become possible by integrating these exciting materials in a monolithic way on top of CMOS. In (bio)sensing applications, for example, owing to their ability to adsorb and desorb various atoms and molecules. Or in optoelectronics, where the combination of a low absorption and high carrier mobility turns out very beneficial. Researchers are also assessing the potential of 2D materials to replace copper wires in back-end-of-line interconnects. Finally, 2D materials have been considered for appli- cation in domains such as plasmonics, photovoltaics and energy storage, and as transparent electrodes. In the latter applications, the requirements for graphene are less stringent than in aggressive transistor scaling. Therefore, the first graphene-based commercial products will most likely be introduced in one of these domains.”

The hamburger experience

Stefan De Gendt: “Ultimately, they potentially enable the engineering of new nano-based stacks: sandwich structures that are composed of various 2D materials, including semiconductors, metals and insulators. This view was nicely described at the 2013 IEDM conference, by the plenary speaker Andrea Ferrari. If you take a hamburger, it’s a layered combination of various ingredients, each with a specific flavor. But it’s the combination of all these layers that makes the hamburger a unique experience. The same will potentially hold for stacks made up of different 2D materials.”

From flakes to large-area synthesis

Applications based on graphene and other 2D materials have become very popular. Many of the above concepts have been successfully demonstrated and have been comprehensively described in scientific journals. However, so far, most of the demonstrations are limited to the lab, using 2D materials in the form of small exfoliated flakes. Iuliana Radu: “The real challenge today is maturing these concepts from flake-based devices towards real products that can be mass produced; only then, can they revolutionize multiple industries. And this has become a key goal at imec. Our goal is to demonstrate the manufacturability of these devices in a 300mm CMOS environment. And we house the expertise to run process flows on these materials (FIGURE 1). At imec, we work on all the unit process steps and on the sequence of steps towards an end application (e.g. TFETs, optical I/O, interconnects), and combine this with modeling and device benchmarking. We also take part in the Graphene Flagship, Europe’s 1 billion euro program that covers the whole value chain from materials production to components and systems.”

Materials 1

The road towards manufacturability

Due to the nature of the 2D materials, almost every unit process step such as contacting, doping, gate engineering, patterning and etch, etc, is a challenge. These steps, combined with the ability to integrate them into a cleanroom compatible process flow, are however essential to progress towards applications.

Cedric Huyghebaert: “A first challenge is related to the growth of these materials on large area templates, and their subsequent transfer to the final substrate. Graphene, for example, is typically grown on a metal template at high temperatures, up to 1000°C. The template is crucial, since the quality of graphene is very much dependent on the quality of the underlying template. Usually, the better the quality of graphene, the more difficult the transfer process becomes. At imec, we are actively working on the growth and defect-free transfer of graphene (FIGURES 2 and 3). In collaboration with AIXTRON, we focus on the synthesis of large area graphene using AIXTRON BM technology, compatible with 200 and 300mm processes. For the transfer, we rely on our knowledge on 3D Si integration processes. We also work on growth of MX2 materials by a direct sulfurization process or by atomic layer deposition in the 200 and 300mm imec fabs.”

Materials 2&3

Another hurdle is doping of the 2D semiconducting materials, which is needed to tune their energy levels and control their properties. Cedric Huyghebaert: “In the classical way, doping a semiconductor material means replacing an atom in the 3D structure. If you replace an atom in a 2D structure, you have a defect. So we have to consider different ways of doping these materials. At imec, we do this in collaboration with universities. We explore the possibility of achieving for example a semi-permanent doping by interaction with chemical molecules. Besides doping, contacting is also a challenge. The contribution of the electrodes to the total resistance of the device needs to be as low as possible. We therefore look into materials and architectures that allow for the lowest possible contact resistance.”

Several applications require a dielectric to be grown on top of the active semiconducting material. Stefan De Gendt: “In case of 2D materials, you have an almost perfectly passivated material, with no anchoring sites for the dielectric to nucleate. Consequently, the more perfect the 2D material, the more defective the dielectric on top may be.” Aaron Thean: “This is completely unlike 3D semiconductor processing, where a large part of material functionalization is achieved by surface and bulk material bond breaking and forming reactions, like dopant activation, oxidation, etc. This potential almost dangling-bond free weakly-interacting Van-Der-Waals nano-sheet system gives rise to new process challenges, as well as new opportunities like surface molecular doping and multi-layer channel stacking. One such approach is to transfer a 2D dielectric material to the 2D semiconducting material – like the hamburger experience described before.” Imec is working on understanding how to passivate, dope and grow dielectrics on various 2D materials. And there is patterning and etch, litho, and finally, characterization. Iuliana Radu:

“We are used to work with 3D bulk materials. But when you need to characterize only one or a few monolayers, there is hardly any material that can take part in the measurement. Therefore, the signals obtained with any classical characterization technique are extremely weak. And this requires new characterization strategies. At imec, we have established procedures that rely in a first phase on the physical characterization of the initial material properties. As the quality of the materials improve, we will cross-correlate physical characterization and electrical behavior of the layers.”

Demonstrating the potential

At IEDM 2014, imec and its associated lab at Ghent University have demonstrated an integrated graphene optical modulator on silicon. Cedric Huyghebaert:

“Integrated optical modulators with high modulation speed, small footprint and broadband a-thermal operation are highly desired for future chip-level optical interconnects. Due to its fast tunable absorption over a wide spectral range, graphene is well suited to achieve this. We could demonstrate a hybrid graphene-silicon modulator at bit rates up to 10Gb/s. This shows that it is possible to introduce CVD-grown graphene in a high quality Si platform and obtain a performance that can compete with traditional SiGe-based modulators. Moreover, if CVD graphene quality becomes more mature and can be brought into production, we will most probably end up with a device that is far less expensive than today’s optical components.”

Worldwide silicon wafer area shipments decreased during the third quarter 2015 when compared to second quarter area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,591 million square inches during the most recent quarter, a 4.1 percent decrease from the record amount of 2,702 million square inches shipped during the previous quarter. New quarterly total area shipments were flat when compared to third quarter 2014 shipments.

“After two consecutive record breaking quarters, quarterly silicon shipment growth slightly declined,” said Ginji Yada, chairman of SEMI SMG and general manager, International Sales & Marketing Department of SUMCO Corporation. “Quarterly shipments for the most recent quarter are on par with the same quarter as last year, with total silicon shipment volumes for 2015 through the end of the third quarter higher relative to the same period last year.”

Quarterly Silicon* Area Shipment Trends

Million Square Inches

Q3-2014

Q2-2015

Q3-2015

9M-2014

9M-2015

Total

2,597

2,702

2,591

7,548

7,930

* Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.