Category Archives: Metrology

The SEMI Strategic Materials Conference (SMC), taking place September 22–-23 in Mountain View, Calif., will uncover the drivers for new materials and how material suppliers are impacted by the value chain they serve. The SMC theme is “”Materials Enabling a Smart and Interconnected World”” – focusing on the emerging trends in the semiconductor industry arising from the increasing pervasiveness of the Internet across industries and the potential impact on our daily lives. SMC is the only conference devoted to the technology and business drivers of materials in the microelectronics industry. It is also a planning, forecasting, and business development necessity for the “advanced materials” microelectronics industry.

Gary Patton, Ph.D., CTO and Head of Worldwide R&D at GLOBALFOUNDRIES kicks off with the conference’s keynote. Other companies presenting include: Air Liquide Electronics, Air Products and Chemicals, Applied Materials, Cabot Microelectronics, Consumer Electronics Association, EMD Performance Materials, Environmental and Occupational Risk Management, Freescale Semiconductor, Honeywell, Imec, Imprint Energy, Inpria, Intel Corporation, Lam Research, Medtronic, Micron Technology, ON Semiconductor, SEMI, Susquehanna International Group, Techcet, and Texas Instruments.

Day One focuses on economic and material trends, including market forces for semiconductor process materials, both from chip fabricators and also end-use applications. Market trends in materials and semiconductor equipment growth, semiconductor production demand, and end-user applications will be covered, as well as a “Street perspective.”

SMC will continue with “Material Enabling Silicon Everywhere” bring new life for mature technologies and new capabilities from materials science. Many Internet of Things (IoT) devices will build off well-known technologies, but “More than Moore” integration may also be necessary to fulfil the vision.

Day Two of SMC focuses on “New Emerging Materials Technology and Opportunities at the Edge.” The “Great Untethering” of data from wired infrastructure led to an explosion in lightweight, high-powered, energy-efficient portable computing. This session delves into how this ubiquitous connectivity will enable new modes of work and leisure, healthcare and entertainment, production, distribution and consumption of the staples and ornaments of life. This session will highlight the new-to-the-world capabilities over the next 20 years, and some likely areas where materials science and technology will be essential parts of tomorrow’s digital ecosystems.

For the “advanced materials”-enabled microelectronics industry, the Strategic Materials Conference is a planning, forecasting, and business development necessity. Organized by the Chemical and Gas Manufacturers Group (CGMG), a SEMI Special Interest Group comprised of leading manufacturers, producers, packagers and distributors of chemicals and gases used in the microelectronics industry, SMC has provided valuable information and networking opportunities to materials and electronics industry professionals since 1995.

For the complete agenda, additional information and to register, visit the Strategic Materials Conference webpage at www.semi.org/smc.

The growth rate for vehicle shipments in China is slowing, but more and better performing semiconductors will still be required in automotive applications in the coming years. Total automotive semiconductor revenue in China reached $5.6 billion in 2014, and revenues are expected to grow nearly 11 percent year over year in 2015 to reach $6.2 billion. Semiconductors used in automotive powertrains, infotainment and body-convenience electronic systems are the primary drivers of revenue growth, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight.

“There is increasing auto industry focus on power efficiency and green energy, as well as the pursuit of greater safety and a better overall driving experience,” said Alex Liu, semiconductors and components analyst for IHS. “For that reason, more and higher performance semiconductors will be required in automotive applications, like direct injection systems in power engines, advanced driver assistance systems and safety applications.”

According to the latest IHS Automotive Semiconductor Report — China, the leading automotive semiconductor company in 2014 was Freescale, based on bill-to China sales, with 15.5 percent of the market. Freescale is strong in the microcontroller and processor market, with products that are widely used in automotive powertrains, automotive bodies, and safety and infotainment systems. Freescale was followed by STMicroelectronics, with 14 percent of the 2014 market in China, and NXP Semiconductors, with 12 percent of the market.

Local automotive design market revenue in China was estimated to reach $1.5 billion in 2014, led by the automotive infotainment category, which includes car radios and navigation systems. IHS expects that the total local design market in China will grow at a 13 percent compound rate from 2014 to 2019.

“Local Chinese companies are strong in the automotive aftermarket, because they have a price advantage, require less time to market and have more flexible design processes than their non-local competitors,” Liu said. “With the accumulation of technical knowledge, and close ties to original equipment manufacturers, some local players have also gradually entered the applications market. They provide semiconductors for low-end auto-body electronic applications where quality and reliability are less critical, such as parking assistance in advanced driver assistance systems and automotive infotainment.”

ReportsnReports.com added 2015 semiconductor market research reports that forecast a 2.9 percent CAGR to 2020 for semiconductor industry and a 6.7 percent rise from 2014 in the semiconductor equipment market size during 2015 across the world.

The Global Semiconductor Market 2015 – 2020 research report forecasts revenues for key services across key geographies. The global semiconductor market is forecast to reach $332bn across 2015, representing a 3.4 percent growth in comparison to $316bn in 2014. This research forecasts that the market will grow at a 5-yr CAGR of 2.9 percent over 2015 to 2020, with the majority of growth being driven by mobile, automotive and industrial application markets. The consumer electronics and data processing application markets are expected to remain at the end of the growth spectrum with limited expectations for any innovative development to lead market demand.

Key product and service applications for semiconductor technology include innovations in smart devices and hyper-connected communications networks, as well as medical devices and efficient infrastructure across the energy sector. There is still capacity in the semiconductor market for innovative semiconductor production methods that drive expenditure reduction, productivity, and efficiency as the demand for performance increases.

This semiconductor market research facilitates analysis of the state of the global semiconductor market in 2015 and a market forecast for the period 2015-2020. It helps identify how the market operates and which companies are operating in the market, their current products and pipeline candidates. Discover how the semiconductor market is evolving across the forecast period of 2015-2020 through the examination of global and regional benefits and challenges, particularly relating to political, economic, social, and technological factors and read interviews with 2 key global authorities in the semiconductor market.

Top 20 global semiconductor industry players, by revenue, 2014 listed in this research include Intel, Samsung, Qualcomm, Micron, SK Hynix, Texas Instruments, Toshiba, Broadcom, TSMC, STM, MediaTek, Renesas, SanDisk, Infineon, NXP, Avago, AMD, Freescale, Sony and NVIDIA.

The second research titled “Global and China Semiconductor Equipment Industry Report, 2014-2015″ says in 2014, the global semiconductor equipment market size totaled USD38 billion, up 10.4 percent from 2013. It is predicted that in 2015 this figure will climb to USD40.5 billion, a rise of 6.7 percent from a year ago, and that the market size in 2016 will slump by 5.6 percent as compared to 2015. However, the possible shrinkage in 2016 might come from the following factors:

Firstly, following a peak in 2014, main electronic products such as smartphones and tablet and laptop PCs have stagnated or declined. This is particularly true of tablet PCs, which has presented a significant decline. On the other hand, equipment market delays being sluggish but will without doubt decline in 2016.

Secondly, due to the global deflation, prices for bulk commodity led by oil and iron ore plunged and would cause knock-on effect, which would in turn result in a fall in semiconductor equipment prices.

Thirdly, global economic recovery will probably come to a halt, with the US GDP dropping by 0.7 percent in 2015Q1. Moreover, China’s GDP growth slowed obviously. The both countries constituted the major driving force of the global economy. The stimulatory effect of US QE began to fade away, and therefore the economy might go down.

In 2014, semiconductor equipment vendors made remarkable performance, with a substantial rise in operating profit, though their revenue did not increased. The merger of Applied Material and Tokyo Electron was rejected by the US Department of Commerce. In future, more of M&A plans may well be intervened by the government, after all semiconductor equipment market is a highly concentrated market.

In 2015, the Chinese semiconductor companies and institutions showed their strength, launching a series of mergers and acquisitions. The Chinese enterprises are adept in and fond of capital operation rather than industrial production. The semiconductor equipment market size in China will reach USD4.4 billion in 2015, of which the domestic companies, mostly engaged in low-end equipment, will account for just 14 percent.

Major semiconductor equipment market vendors mentioned in this report include Applied Materials, ASML, Tokyo Electron, KLA-Tencor, Lam Research, DAINIPPON SCREEN, Nikon Precision, Advantest, Hitachi High-Technologies, ASM International N.V., Teradyne, ASM PACIFIC, Kulicke & Soffa, AMEC and Sevenstar Electronics.

North America-based manufacturers of semiconductor equipment posted $1.51 billion in orders worldwide in June 2015 (three-month average basis) and a book-to-bill ratio of 0.98, according to the June EMDS Book-to-Bill Report published today by SEMI.  A book-to-bill of 0.98 means that $98 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in June 2015 was $1.51 billion. The bookings figure is 2.6 percent lower than the final May 2015 level of $1.55 billion, and is 3.5 percent higher than the June 2014 order level of $1.46 billion.

The three-month average of worldwide billings in June 2015 was $1.54 billion. The billings figure is 1.0 percent lower than the final May 2015 level of $1.56 billion, and is 16.2 percent higher than the June 2014 billings level of $1.33 billion.

“The June book-to-bill saw slight declines in the three-month averages for both booking and billings compared to May,” said Denny McGuirk, president and CEO of SEMI.  “Both figures, however, are above the trends reported one year ago and the first half of the year has been one of positive growth.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
January 2015 

$1,279.1

$1,325.6

1.04
February 2015 

$1,280.1

$1,313.7

1.03
March 2015 

$1,265.6

$1,392.7

1.10
April 2015 

$1,515.3

$1,573.7

1.04
May 2015 (final)

$1,557.3

$1,546.2

0.99
June 2015 (prelim)

$1,542.1

$1,506.1

0.98

Source: SEMI (www.semi.org), July 2015

Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, today announced that Analog Devices, Inc. has joined SRC’s hardware cybersecurity research program called Trustworthy and Secure Semiconductors and Systems (T3S).

T3S is a new SRC targeted research effort aimed at developing cost-effective strategies and tools to design and manufacture chips and systems that are reliable, trustworthy, secure and resistant to attack, tampering or counterfeiting. With the emergence of the Internet of Things, the increasing reliance on connected mobile and embedded devices, and the lengthy and global supply chain, the ability to provide assurance that hardware systems do what they are intended to and nothing else is more important than ever.

“Semiconductors are key enablers to the innovation and economic growth potential embodied in the next wave of information and communications technology where all manner of physical phenomena and digital devices are sensor-equipped and connected. The magnitude of this wave will depend in large part on the semiconductor industry’s ability to offer the assurances of security and reliability to customers. We see the SRC T3S program as an excellent, research, university-based program that will develop tools and design methods to secure the distributed sensor networks of the future,” said Samuel H. Fuller, Vice President of R&D at Analog Devices.

“We are pleased to have Analog Devices participating in the T3S program as we work to develop techniques and tools that provide assurance to customers across the entire supply chain,” said Celia Merzbacher, SRC Vice President for Innovative Partnerships.

T3S is collaborating with the National Science Foundation (NSF) to jointly fund university research on Secure, Trustworthy, Assured and Resilient Semiconductors and Systems (STARSS).

This collaboration substantially increases the impact of the T3S investment and enhances the value of the federal program by utilizing funding and connecting industry and academia. Last year STARSS announced a first set of projects at 10 universities totaling approximately $4 million and is in the process of selecting a second round of proposals to begin in late 2015.

BY JIN YOU ZAO, STATS ChipPAC, Singapore, and JOHN THORNELL, Rudolph Technologies, Inc. Bloomington, MN, USA

The demand for 4-mask layer Cu-plated wafer-level chip scale packaging (WLCSP) is increasing rapidly, and the current capability for in-line Cu height measurements is not suitable for high volume manufacturing (HVM). Thus, metrology constrains production capacity and limits volume ramp. Furthermore, the bottleneck created by a backlog of Cu step height measurements risks the timely detection of process drift and control. For a 4-mask layer Cu-plated WLCSP, accurate Cu step height measurement is required for both the Redistribution Layer (RDL) and Under Bump Metal (UBM) to ensure consistent delivery of good electrical performance and package reliability. This is especially important as WLCSP is moving towards finer feature size and pitch to meet increasing demand for smaller form factor.

In this article, the current measurement methodology is reviewed and an alternative measurement solution is derived. Full automation capability is delivered, yet the solution is reliable and versatile enough for high-mix production volumes. For quick-turn and high-mix volume manufacturing, accurate and fast in-line monitoring is crucial for timely process drift detection and control.

WLCSP in-line process measurement challenges

Contact-based profilometers are commonly used in wafer bumping for measurement of metal feature (RDL, UBM) thicknesses due to their ease of use and their low cost of ownership. However, the method of measurement is largely semi-automatic, and the identification of exact features and measurement locations is challenging.

This becomes more acute in a high product-mix HVM environment, where measurement needs to be highly adaptive to different features on different products. As such, contact-based profilometers are limited to sampling measurements, and cannot perform 100% die inspection for process characterization.

It is thus desirable to have an automated feature measurement system capable of measuring features at precise locations on different topology on wafers in both sampling and full inspection modes.

Specifically, feature measurement for wafer bumping comprises the following configurations (FIGURE 1):

HVM Fig 1

a) Cu RDL feature height measurement after Cu electro-plating, where the sputtered metal seed layer to enable Cu plating remains on the first layer polyimide surface

b) Final Cu RDL feature thickness measurement on first layer polyimide surface (PI-1) after the Cu seed layer is etched away. Accurate final Cu RDL thickness measurement would require a good gauging of the PI-1 thickness underneath, especially if the topology is not flat.

c) Cu UBM feature height measurement after Cu electroplating

d) Final Cu UBM feature thickness measurement on second layer polyimide surface (PI-2)

The development for automated feature measurement proceeded in two phases: (Phase-1) Cu step height highlight measurement on reflective metal surfaces, and (Phase-2) Cu thickness and polyimide thickness measurement on non-reflective surfaces.

Phase-1: Auto Cu height measurement

In this phase, the 3D inspection (3DI) system commonly used for solder bump height (typically greater than 20μm) measurement is explored for auto Cu feature height measurement. Typical 3DI system such as Rudolph’s WaferScanner, is equipped with the 3D triangulation laser sensor (FIGURE 2). Laser triangulation, where a laser is directed at the wafer surface at an angle of 45° and focused to a spot size of 8μm, provides fast, precise measurements of bump height and coplanarity. Through a combination of laser-scanning and wafer movement, the beam scans the entire wafer surface. A lens collects the reflected/scattered laser light and focuses it on a position sensitive detector.

HVM Fig 2

To enable Cu feature height measurement (typically in the range of 2- 20μm), the Triangular laser sensor was redesigned with a spot size of 5μm, providing accuracy down to +/-0.2 μm. The laser scanning algorithm was also improved from an array to a stagger method to improve the repeatability of scanning signals. As Cu feature height measurement is influenced by the surrounding topology, the ability to select any datum for measurement is critical. This was achieved through the integration of camera-based 2D inspection to the improved triangular laser sensor system using the developed datum selection program. An automated height measurement report can be conveniently generated for further analysis through the program (FIGURE 3).

FIGURE 3. Selectable datum for Cu feature height measurement through camera-sensor integration.

FIGURE 3. Selectable datum for Cu feature height measurement through camera-sensor integration.

To verify the consistency of measurement performance, both the improved 3D triangulation laser sensor system and contact profilometer were used to measure feature Cu height on correlation device wafers. It confirmed that the automated 3D triangulation laser sensor system registers statistically similar Cu feature height mean compared to the manual contact profilometer, but required only one-fifth of the measurement time taken by the profilometer. Wafer bumping facilities which already have an existing pool of 3DI inspection tools can be modified to extend measurement application to Cu feature height without the need for excessive new investment.

Phase-2: Auto Cu/ PI thickness measurement

While a strong signal can be derived using the 3D triangular laser signal for Cu feature height measurement after electroplating (Fig. 1, a and c), it is more difficult to establish a stable signal for Cu feature height measurement after the reflective metal seed layer is etched away, and a reference datum needs to be established on the remaining transparent polyimide surface (Fig. 1, b and c). Several conventional methods exist for non-contact measurement of step heights, such as various confocal sensors, triangulation sensors, and scanning white light interferometry. These sensors typically have difficulty differentiating between reflections from the top and bottom surfaces of a layer, that is, layer thickness. This limitation comes from the depth of focus of the objective, which in turn depends on its numerical aperture (NA). Thus, for all these techniques, sensor performance is highly dependent on objective lens.

To overcome this technical constraint, it was necessary to develop a metrology system that can measure concurrently the transparent layer thickness as well as the metal feature step height above the surface of the transparent layer. This can be achieved through the integration of reflectometry and visible light interferometry principles [3]. In this method, the direct reflection from the transparent layer provides direct thickness measurement of the transparent material, while the interferometry captures topography (distance from the sensor), allowing the system to measure the thickness of the opaque metals by scanning over the edge of the feature. This technique is called the visible thickness and shape sensor (VT-SS) system.

In the following sections we provides further description of how the VT-SS system can be adapted for feature height/thickness measurement on varying topology and opaque materials. For this work, we used the Rudolph Technologies NSX System configured with the VT-SS sensor.

VT-SS system MSA study

Measurement system analysis (MSA) seeks to qualify a measurement system for use by quantifying its accuracy, precision and stability. VLSI standard wafers with 8μm, 24μm, and 48μm step heights were used to assess gauge repeatability and reproducibility (GR&R) and accuracy of the VT-SS system, as well as system correlation on two different NSX Systems (tool matching) that were retrofitted with the VT-SS system.

A. Gauge repeatability and reproducibility
For the GR&R study, a total of ten parts on VLSI wafers (4 parts from 8μm, 3 parts from 24μm and 48μm respectively) were measured three times each, including wafer loading and unloading. FIGURE 4 shows gauge R&R for VT-SS is 1.35% of tolerance and fully meeting AIAG standard of <10%.

HVM Fig 4

B. Accuracy
Step height measurement accuracy was evaluated by means of bias and linearity analysis using the VLSI step height wafers. For this study, one location on each standard wafer was measured ten times and compared to the VLSI specification for the wafer.

Based on the studies in FIGURE 5, measurement with VT-SS system shows an average bias of 0.95%, and linearity error of 0.0059%, meeting the AIAG standard of <5%.

FIGURE 5. Accuracy study on VT-SS with VLSI standard.

FIGURE 5. Accuracy study on VT-SS with VLSI standard.

C. Correlation of Multiple Systems
Having established VT-SS capability, the next evaluation is system correlation on multiple tools of the same configuration. The same VLSI wafers described above were measured on a second system with the same hardware and software configuration.

HVM Table 1

A summary of results are shown in TABLE 1, and a detailed example of the 24μm step height is shown in FIGURE 6. For each wafer, the two systems produce similar results, with an offset that ranges from approximately 10nm to 30nm. Considering that the measurement uncertainty is on the order of 5nm (1-), the small system offset is within expectations.

HVM Fig 6

VT-SS system application assessment

VT-SS system allows capturing of both the transparent polyimide thickness and opaque Cu feature height with a single scan from polyimide layer to Cu feature. From the part of the scan covering the polyimide, signals representing the direct measure of the polyimide thickness, the distance to the first surface of the polyimide, and the distance to a metal surface under the passivation stack are measured. The direct measure of the polyimide thickness is the measurement a standard spectroscopic reflectometer would produce. In that part of the scan where the sensor spot illuminates the Cu step height, the direct thickness peak and one of the distance peaks disappear. Only a distance peak to the surface of the Cu feature is present since the copper is opaque. The Cu step height above the first polyimide layer is then determined from the appro- priate distance measures from each part of the scan. Thus, all the desired thickness and Cu thickness measurements are reported.

To aid interpretation of measured signal peaks, a visualization program was developed for automated generation of feature thickness. FIGURE 7 shows an illustration of the program interface for visualization of measured thickness. Raw data can also be exported for further analysis.

HVM Fig 7

A. VT-SS Cu RDL Layer thickness measurement
To assess VT-SS system’s measurement performance on an actual device feature, it was used to measure the Cu feature RDL thickness layer above the first polyimide (PI) layer (refer to Fig. 1, for a pictorial illustration) on a correlation device wafer. The measured RDL thickness was then cross verified with the actual measured Cu feature step height from a contact profilometer and WaferScanner

B. VT-SS Polyimide cum RDL layer Thickness
Further evaluation of the VT-SS system accuracy was achieved through comparison with cross sectional scanning electron microscopy (X-SEM) measurements. X-SEM allows evaluation of both RDL step height and PI thickness (Fig. 1, b). As discussed above the measurement sensor has the unique capability to simultaneously measure step height, i.e. a distance measurement, and film thickness. Both types of measurements must be independently evaluated for accuracy.

Conclusion

We have reported the development of VT-SS-based system on a fully automated platform for in-line process measurement of wafer bumping processes. This new metrology integrates both reflectometry and visible light interferometry principles. Based on MSA studies, VT-SS on a fully automated platform is a precise, accurate and fast metrology system. Engineering validations have shown VT-SS is highly capable in measuring critical dimensions such as RDL/UBM metal thickness, transparent polyimide/ passivation thickness, and feature sizes in one single step. It relieves the current constraints imposed by existing measurement tools on in-line process control, especially in a high mix, high volume production environment. This allows WLCSP production to move to new milestones of quality, yield, cycle time and productivity.

Acknowledgment

The authors would like to thank Harry Kam of STATSChipPAC Singapore (SCS) for his sponsorship in this project, and other team members from SCS and Rudolph Technologies, Inc. for supporting the development work.

References
1. Yole Development, WLCSP Market & Industrial Trends: 2012, Jan2012
2. Robert F. Kunesh, “Wafer Level Chip-Scale Packaging: Evolving to Meet a Growing Application Space”, Adv. Microelectronics, Jan/Feb 2013, Vol. No.1, pp14-16.
3. J. Schwider and Liang Zhou, “Dispersive Interferometric Profilometer,” Opt. Lett., Vol. 19, p. 995, 1994.

JIN YOU ZAO is with STATS ChipPAC in Singapore, and JOHN THORNELL is with Rudolph Technologies, Inc., in Bloomington, MN.

Genmark Automation, a developer of tool and factory automation solutions for the semiconductor and related industries, today announced the launch of its new CODEX Stocker. The CODEX Stocker integrates stocking, sorting and metrology functions in a single tool that stores and delivers various substrates on demand, of defined quality and in defined numbers. Consolidating the functions of these traditionally nonrevenue-generating tools frees up fab floor space for production equipment, enabling a facility to maximize its productivity and yield.

“There is a clear market opportunity for a high-quality, highly reliable tool that can enable the functions of sort, stocking and metrology simultaneously,” said Carl McMahon, President & EVP of Global Customer Operations at Genmark Automation. “Given the continual pressure to improve yield and productivity, the benefits of storing, measuring and tracking all media in one location, using less cleanroom floor space, quickly becomes evident.”

Key differentiators of the CODEX Stocker include:

  • Reduced overall tool footprint. Novel rotary “carousel” module, which increases the volume of substrates stored compared with existing rack systems, and allows the robot to access the wafers from a single side.
  • First library retrieval system for semiconductor manufacturing. Integrated stocker and metrology systems enable real-time measurement and data tracking. Storing all substrates in a single location allows for more effective tracking of the substrate life cycle.
  • Gantry robot to provide extended range and larger working envelope for wafer delivery.

“Beyond the traditional Si wafer market, the glass wafer for bond/debond, reticle and reticle box storage are important targets for this type of integrated system,” said McMahon. “Taking the glass wafers used in bond/debond as an example, concentricity, uniformity and thickness are very important. By stocking all media in one location with onboard metrology, you can easily make decisions on when the usable lifetime of a wafer is up and when to change it out, to consistently maximize productivity.”

The CODEX’s modular design is easily configurable to customers’ specific needs, whether integrated device manufacturers or original equipment manufacturers. A high-capacity system, it is performance-optimized for high throughput, has a configurable architecture and is readily expandable. For example, using 300mm wafers, each carousel can hold up to 1,700 wafers, depending on thickness. The tool supports 200mm, 300mm and 450mm wafers as well as reticles.

codex

IBM Research today announced that working with alliance partners at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE) it has produced the semiconductor industry’s first 7nm (nanometer) node test chips with functional transistors. The breakthrough underscores IBM’s continued leadership and long-term commitment to semiconductor technology research.

The accomplishment, made possible through IBM’s unique public-private partnership with New York State and joint development alliance with GLOBALFOUNDRIES, Samsung and equipment suppliers, is driven by the company’s $3 billion, five-year investment in chip R&D announced in 2014. Under that program, IBM researchers based at SUNY Poly’s NanoTech Complex in Albany are pushing the limits of chip technology to 7nm node and beyond to meet the demands of cloud computing and Big Data systems, cognitive computing and mobile products.

Developing a viable 7nm node technology has been one of the grand challenges of the semiconductor industry. Pursuing such small dimensions through conventional processes has degraded chip performance and negated the expected benefits of scaling — higher performance, less cost and lower power requirements. Microprocessors utilizing 22nm and 14nm technology power today’s servers, cloud data centers and mobile devices, and 10nm technology is well on the way to becoming a mature technology, but 7nm node has remained out of reach due to a number of fundamental technology barriers. In fact, many have questioned whether the traditional benefits of such small chip dimensions could ever be achieved.

The IBM 7nm node test chip with functioning transistors was achieved using new semiconductor processes and techniques pioneered by IBM Research. Developing it required a number of first-in-the-industry innovations, most notably silicon germanium (SiGe) channel transistors and extreme ultraviolet (EUV) lithography integration at multiple levels.

By introducing SiGe channel material for transistor performance enhancement at 7nm node geometries, process innovations to stack them below 30nm pitch and full integration of EUV lithography at multiple levels, IBM was able to achieve close to 50 percent area scaling improvements over today’s most advanced 10nm technology. These efforts could result in at least a 50 percent power/performance improvement for the next generation of systems that will power the Big Data, cloud and mobile era.

The 7nm node milestone continues IBM’s legacy of historic contributions to silicon and semiconductor innovation. They include the invention or first implementation of the single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed SiGe, High-k gate dielectrics, embedded DRAM, 3D chip stacking and Air gap insulators.

IBM and SUNY Poly have built a highly successful, globally recognized partnership at the multi-billion dollar Albany NanoTech Complex, highlighted by the institution’s Center for Semiconductor Research (CSR), a $500 million program that also includes the world’s leading nanoelectronics companies. The CSR is a long-term, multi-phase, joint R&D cooperative program on future computer chip technology. It continues to provide student scholarships and fellowships at the university to help prepare the next generation of nanotechnology scientists, researchers and engineers.

Related news: 

IBM announces $3B research initiative

GLOBALFOUNDRIES completes acquisition of IBM Microelectronics business

By Christian Dieseldorff and Lara Chamness, SEMI

We, in the semiconductor supply chain, are constantly immersed in detailed numbers. It’s important to pull back and look at the major trends that have profoundly changed and are reshaping our industry.

Data from SEMI World Fab Forecast reports

1997

2002

2007

2012

2017
Global Volume Fab Count
Number of Fabs WW 

682

802

849

861

864
Number of Fabs WW (excluding discrete and LED)

472

508

499

440

440
Global Volume Fabs by Wafer Size
Number of volume 200mm fabs (excluding discrete and LED)

111

170

173

152

149
Number of volume 300mm fabs (excluding discrete and LED)

0

13

62

81

109
Global Fab Capacity by Device Type
Fab Capacity (200mm equiv. thousand wafer starts per month)

5,655 

7,519 

15,441 

18,068 

20,609 

Memory

20%

19%

36%

29%

27%

Foundry

13%

19%

18%

27%

30%

MPU&Logic

35%

31%

22%

17%

16%

Analog, Discretes, MEMS & Other

32%

31%

24%

27%

26%
Largest Regional Fab Capacities
Fab Capacity Regional Trends (excluding discrete and LED)

Largest installed capacity

Japan

Japan

Japan

Japan

Taiwan

Second largest installed capacity

Americas

Americas

Taiwan

S. Korea

S. Korea

Third largest installed capacity

Europe

Europe

S. Korea

Taiwan

Japan
Source: SEMI (www.semi.org) 

The table shows that the largest increase of new fabs occurred in the time frame from 1997 to 2002 with 18 percent growth rate. The growth rate drops to 6 percent from 2002 to 2007, 1 percent from 2007 to 2012 and flat from 2012 to 2017. This drop in change rate does not mean that there are no new fabs being built but is explained by fabs closing. There are still new fabs being built ─ especially for 300mm ─ but the rate of fabs closing is overshadowing this fact. From 2007 to 2012 alone over 150 facilities closed with majority from 2008 to 2010.

With the rise of 300mm at begin of the millennium we see a rapid increase of 300mm fabs from 2002 to 2007 with 380 percent and at the same time a decrease of new 200m fabs from 50 percent to 2 percent. From 2007 to 2012 more 200mm fabs were closed but this trend is slowing. With emerging IOT demand, 200mm fabs will be part of the capacity mix for the foreseeable future.

Fueled by the fabless or “fab lite” movement, we see that the foundry era has a strong and steady growth since begin of its era in the 90s. By 2017, foundry capacity will have surpassed memory with 30 percent of the total capacity.

Both foundry and memory mainly use 300mm wafers which contribute to the large increase in capacity. The other sector MPU & Logic uses mainly 300mm but there are still fabs with wafer sizes of 200mm or less. While the Logic sector is increasing in capacity with System LSI applications, we see a decline for MPU which contributed to the decline in share.  Although we see an increase of capacity for sensors and analog/mixed signal, the sector combined as “Analog, Discretes, MEMS & Others” shows modest growth mainly because the wafer sizes used are 200mm and below which contributes to the less share of capacity.

For decades Japan was the leader in installed capacity which will have changed by 2017 when Taiwan will have taken over the highest capacity spot.  Japan is restructuring business models and approaching a more fab-lite to fabless model.  Korea is mainly driven by Samsung and is benefitting from the mobile business using memory and System LSI chips.

For more information on market data, visit www.semi.org/en/MarketInfo and attend an upcoming SEMICON: SEMICON West 2015 (July 14-16) in San Francisco, Calif; SEMICON Taiwan 2015 (September 2-4) in Taipei, Taiwan; SEMICON Europa 2015 (October 6-8) in Dresden, Germany; SEMICON Japan 2015 (December 16-18) in Tokyo, Japan.

By David W. Price and Douglas G. Sutherland

Author’s Note: This is the eighth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications.

Moving to the next design rule can be stressful for the inspection and metrology engineer. Like everything else in the fab, process control generally doesn’t get any easier as design rules shrink and new processes are introduced.

The eighth fundamental truth of process control for the semiconductor IC industry is:

Process Control Requirements Increase with Each Design Rule

This statement has proven to be historically accurate, as evidenced by the increase in process control spending as a percentage of wafer front-end (WFE) total costs. This article, however, will focus on a few of the forward-looking observations that we believe will further accelerate the adoption of process control.

The historical increase in process control with shrinking design rules has been driven largely by the introduction of key technical inflections. Recent examples for logic/foundry include immersion lithography, high-k metal gates, gate-last integration, and FinFET transistor structures. These high profile process changes required enormous engineering focus and led to the implementation of new inspection and metrology steps to characterize the associated defectivity and drive yield learning.

While the industry will continue to face significant technical challenges (next-generation lithography being the most obvious example), there is another factor emerging which will play an equally large role in setting the inspection and metrology strategy for the 16/14nm design node and beyond.

Figure 1 shows the number of process steps as a function of design rule for a generic logic/foundry process. Up to the 20nm node, there has been a very modest increase in process steps with design rule shrinks due to, for example, more metal levels and the addition of hard mask steps. But starting at 16/14nm, there will be an unprecedented increase in the number of process steps. This jump in process steps will be driven by:

  • The shift from 2D to 3D transistor structures in both logic and memory
  • More complicated integration in both the front end and back end
  • The push-out of EUV lithography, leading to massive numbers of multi-patterning steps

Figure 1. The number of process steps will increase dramatically, starting at 16/14nm. [source: IC Knowledge Strategic Cost Model, KLA-Tencor internal data]

Figure 1. The number of process steps will increase dramatically, starting at 16/14nm. [source: IC Knowledge Strategic Cost Model, KLA-Tencor internal data]

Process Tool Defectivity

Because of this increase in process steps—and the accumulative nature of yield loss—fabs must reduce the defectivity at each individual step in order to achieve the same final yield. Figure 2 shows the total yield as a function of the number of process steps where the average per-step yield is held constant. Prior to 16/14nm, this effect was scarcely noticeable since the total increase in process steps was minimal.

Moving forward, fab defect reduction teams must continue to resolve the challenging new technical inflections. But they must also place more focus on driving down defectivity at all process steps:

  1. Line Yield: To maintain the same line yield (wafers out / wafers in), there must be fewer excursions and less scrap at each step
  2. Die Yield: Every operation in the fab must be held to a tighter specification for defect density (D0) and variation (Cpk)

To make matters worse, defect inspection and metrology operations will continue to become more difficult. The defect count must go down even as the number of yield-relevant defects increases and the detection task becomes harder. Similarly, the variability in metrology measurements must be reduced even as those measurements become more difficult to make.

Figure 2. The Cumulative (Final) Yield is the product of the per-step yield for each unit operation in the process flow. This chart shows that, for a given average per-step yield, the final yield will decrease as the number of process steps increases.

Figure 2. The Cumulative (Final) Yield is the product of the per-step yield for each unit operation in the process flow. This chart shows that, for a given average per-step yield, the final yield will decrease as the number of process steps increases.

Impact on Cycle Time

The increase in process steps has another downside: increased cycle time. If cycle time increases in proportion to the number of process steps then it follows from Figure 1 that the cycle time will roughly double from the 20nm to the 10nm node. One publication has even suggested that the cycle time may double from 20nm to an advanced 16nm process [2].

The fab’s ability to do yield learning via feedback from electrical test and physical failure analysis (PFA) is directly tied to the “hot lot” cycle time. Longer hot-lot cycle times mean fewer opportunities for these long-loop learning cycles as device manufacturers try to ramp yield and deliver products to market. More emphasis must therefore be placed on in-line yield learning methodologies.

Sampling Pressure

Finally, more process steps will increase the manufacturing cost per wafer. In the second article in this series, Sampling Matters, we showed that the ideal sampling rate (that which provides the lowest total cost to the fab) goes with the square root of the device manufacturing cost. In other words, if the manufacturing cost increases by 30 percent then the corresponding process control sampling rate needs to increase by 14 percent (everything else being constant) to stay at the lowest total cost. This sampling increase will put further pressure on the fab’s inspection and metrology teams.

Summary

In summary, each new design rule will introduce:

  • Technical inflections that require engineering focus and innovation, as well as the implementation of new process control methodologies
  • More process steps that must be directly monitored
  • Tighter controls and lower defect density at each individual step due to the compounding nature of yield loss
  • Longer cycle times, resulting in more reliance on in-line (vs. end-of-line) techniques for yield learning
  • Higher stakes (greater economic impact to the fab) in the event of an excursion due to the higher wafer manufacturing costs, which will put pressure on the fab to increase inspection and metrology sampling

The cascade of challenges that flows from the increase in process steps is sometimes referred to as the “Tyranny of Numbers.” For further exploration of how fabs are adapting their process control strategy for new design rules, please contact the authors of this article.

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

  1. Lipsky, “TSMC Outlines 16nm, 10nm Plans.” EE Times, 4/8/2015.
  2. Jones, Strategic Cost Model, IC Knowledge, LLC. http://www.icknowledge.com/

Read more Process Watch: 

Time is the enemy of profitability

Know your enemy

The most expensive defect

Process Watch: Fab managers don’t like surprises

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”