Category Archives: Metrology

GLOBALFOUNDRIES today announced that it has completed its acquisition of IBM’s Microelectronics business.

With the acquisition, GLOBALFOUNDRIES gains differentiated technologies to enhance its product offerings in key growth markets, from mobility and Internet of Things (IoT) to Big Data and high-performance computing. The deal strengthens the company’s workforce, adding decades of experience and expertise in semiconductor development, device expertise, design, and manufacturing. And the addition of more than 16,000 patents and applications makes GLOBALFOUNDRIES the holder of one of the largest semiconductor patent portfolios in the world.

“Today we have significantly enhanced our technology development capabilities and reinforce our long-term commitment to investing in R&D for technology leadership,” said Sanjay Jha, chief executive officer of GLOBALFOUNDRIES. “We have added world-class technologists and differentiated technologies, such as RF and ASIC, to meet our customers’ needs and accelerate our progress toward becoming a foundry powerhouse.”

Through the addition of some of the brightest and most innovative scientists and engineers in the semiconductor industry, GLOBALFOUNDRIES solidifies its path to advanced process technologies at 10nm, 7nm, and beyond.

In RF, GLOBALFOUNDRIES now has technology leadership in wireless front-end module solutions. IBM has developed world-class capabilities in both RF silicon-on-insulator (RFSOI) and high-performance silicon-germanium (SiGe) technologies, which are highly complementary to GLOBALFOUNDRIES’ existing mainstream technology offerings. The company will continue to invest to deliver the next generation of its RFSOI roadmap and looks to capture opportunities in the automotive and home markets.

In ASICs, GLOBALFOUNDRIES now has technology leadership in wired communications. This enables the company to provide the design capabilities and IP necessary to develop these high-performance customized products and solutions. With increased investments, the company plans to develop additional ASIC solutions in areas of storage, printers and networking. The most recent ASIC family, announced in January and built on GLOBALFOUNDRIES’ 14nm-LPP technology, has been well accepted in the marketplace with several design wins.

GLOBALFOUNDRIES increases its manufacturing scale with fabs in East Fishkill, NY and Essex Junction, VT. These facilities will operate as part of the company’s growing global operations, adding capacity and top-notch engineers to better meet the needs of its existing and new customers.

Moreover, the transaction builds on significant investments in the burgeoning Northeast Technology Corridor, which includes GLOBALFOUNDRIES’ leading-edge Fab 8 facility in Saratoga County, NY and joint R&D activities at SUNY Polytechnic Institute’s College of Nanoscale Science and Engineering in Albany, NY. The company’s presence in the northeast now exceeds 8,000 direct employees.

The acquisition includes an exclusive commitment to supply IBM with advanced semiconductor processor solutions for the next 10 years. GLOBALFOUNDRIES also gets direct access to IBM’s continued investment in semiconductor research, solidifying its path to advanced process geometries at 10nm and beyond.

Related news: 

IBM announces $3B research initiative

Research led by Michigan State University could someday lead to the development of new and improved semiconductors.

In a paper published in the journal Science Advances, the scientists detailed how they developed a method to change the electronic properties of materials in a way that will more easily allow an electrical current to pass through.

The electrical properties of semiconductors depend on the nature of trace impurities, known as dopants, which when added appropriately to the material will allow for the designing of more efficient solid-state electronics.

The MSU researchers found that by shooting an ultrafast laser pulse into the material, its properties would change as if it had been chemically “doped.” This process is known as “photo-doping.”

“The material we studied is an unconventional semiconductor made of alternating atomically thin layers of metals and insulators,” said Chong-Yu Ruan, an associate professor of physics and astronomy who led the research effort at MSU. “This combination allows many unusual properties, including highly resistive and also superconducting behaviors to emerge, especially when ‘doped.'”

An ultrafast electron-based imaging technique developed by Ruan and his team at MSU allowed the group to observe the changes in the materials. By varying the wavelengths and intensities of the laser pulses, the researchers were able to observe phases with different properties that are captured on the femtosecond timescale. A femtosecond is 1 quadrillionth, or 1 millionth of 1 billionth, of a second.

“The laser pulses act like dopants that temporarily weaken the glue that binds charges and ions together in the materials at a speed that is ultrafast and allow new electronic phases to spontaneously form to engineer new properties,” Ruan said. “Capturing these processes in the act allows us to understand the physical nature of transformations at the most fundamental level.”

Philip Duxbury, a team member and chairperson of the department of physics and astronomy, said ultrafast photo-doping “has potential applications that could lead to the development of next-generation electronic materials and possibly optically controlled switching devices employing undoped semiconductor materials.”

A semiconductor is a substance that conducts electricity under some conditions but not others, making it a good medium for the control of electrical current. They are used in any number of electronics, including computers.

Bruno Mourey, chef du Département intégration hétérogène sur siliciumBy Bruno Mourey, Chief Technology Officer, CEA-Leti

As these early days of the Internet of Things show the network’s promise and reveal technological challenges that could threaten its ability to meet user expectations in the years ahead, technology providers will be charged with supplying the solutions that will meet those challenges.

Chief among them for designers and chipmakers are the increased complexity and cost of IC design and yield ramp-ups, and wafer costs, said Carlo Reita, strategic marketing manager at CEA-Leti.

“Disruptive architecture and integration technologies are required,” Reita told participants at the 17th annual LetiDays in Grenoble, France, June 24-25. In his talk, “Technologies and architectures for low-power data processing,” Reita noted the spikes in both complexity and cost that accompany the industry’s progression to smaller technology nodes. The spikes are driven primarily by costly new tools and increases in both design manpower and the number of expensive licenses for software-design tools that accompany increasing device complexity.

Reita cited projections from IBS that industry-wide, non-recurring engineering (NRE) costs will total $38 million for IC designs at the 28nm node, $132 million at the 16nm node and $1.34 billion at the 5nm node.

Adding yield ramp-up costs to IC design costs, which include both new designs and specializations, the projected NREs skyrocket from $59 million at 28nm to $176 million at 16nm and $2.24 billion at 5nm. Meanwhile, the average selling price of 300mm wafers grow from $9,885 at 16nm to $19,620 at 5nm.

Reita noted that such projections underscore the pressure that the industry will face to develop new design-implementation approaches that change the cost metrics for advanced-features, so that initial products can generate revenues that justify the design and yield ramp-up costs.

He said that managing data traffic that is increasing exponentially, while maintaining data-center server performance and lowering the centers’ energy consumption, is among the top challenges for the computing industry in the years ahead. Meanwhile, mobile computing and the Internet of Things are adding a different set of challenges that will feed the design-cost escalation, ranging from the requirement for mandatory long battery life to supporting heterogeneous and power-hungry applications and the capability to adjust to process, voltage and temperature variations.

Reita also outlined Leti’s plans and vision for technologies that address these challenges in the short, medium and longer terms.

Like other speakers during the two-day event, he noted FD-SOI’s advantages compared to FinFET as a proven low-power, cost-effective solution that will meet current and mid-term needs for devices down to the 10nm node. In addition, transistor-stacking options, such as Leti’s low-temperature CoolCube technology, support denser and higher-performing CMOS devices. CoolCube also makes it easier for designers to use heterogeneous integration of material and/or functions and provides a greater degree of freedom for design partitioning, Reita said.

Other avenues of exploration include adaptive fine-grain architecture that mitigates local and dynamic PVT variations, and permits either better use of the chip surface or smaller chips

Leti also is working on resistive RAM that can reduce power consumption at the storage level by putting high-density, non-volatile memory closer to logic chips.

On Leti’s roadmap for the medium term, neuromorphic architectures may enable full transfer of successful algorithms into a specific physical system that will achieve power-efficient computation. Deep recurrent networks with spike coding are a likely candidate to best match physical implementation characteristics.

In Leti’s view, this architecture also allows co-localization of memory and computation similar to a biological system, where a synaptic element performs storage, interconnect and non-linear operations. In addition, the architecture takes full advantage of Leti’s advanced RRAM, 3D and low-power CMOS techniques to break memory-bottleneck and synaptic-density issues, while maintaining ultra low power.

Reita also spoke briefly about quantum computing, “a very long-term” technology possibility, whose appeal includes superposition of the quantum bits (qubits) states in an ultimate parallel system and reversible operators that keep power use at a minimum. This architecture, which is probably 20 years down the road, is expected to massively accelerate computation. It will be best suited for tackling complex optimization problems, Reita said.

Leti collaborates with CEA’s fundamental research departments on topics including SiGe nanowire devices, in which electronics states can act as qubits and use Pauli spin blockade for spin-charge conversion and interaction with CMOS and the external world.

Related news:

Leti workshop covers major trends in FD-SOI technologies

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Leti launches new Silicon Impulse FD-SOI Development Program

Semiconductor Manufacturing International Corporation, China’s largest and most advanced semiconductor foundry, today announced its receipt of the “2014 Foundry Supplier of the Year” award from customer Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated.

Qualcomm Technologies, one of the world’s largest fabless semiconductor vendors and a world leader in 3G, 4G and next-generation wireless technologies, gave the award to SMIC in recognition of its achievement in fabricating Qualcomm Technologies’ power management integrated circuits (PMIC). SMIC has been manufacturing Qualcomm Technologies’ PMIC products since 2009 and this award demonstrates SMIC’s excellence in its technical reliability, product quality, and customer service.

“It’s a great honor to receive this award from Qualcomm Technologies.” said Mike Rekuc, Executive Vice President of Worldwide Sales and Marketing, SMIC. “We greatly appreciate Qualcomm Technologies’ trust in SMIC and will continue to cooperate closely in both mature and advanced processes as a long-term partner.”

“SMIC is an important supplier to Qualcomm Technologies, and we highly recognize the success SMIC has achieved in serving our needs with high-quality products,” said Roawen Chen, Senior Vice President of QCT global operations, Qualcomm Technologies, Inc. “As we’ve expanded our work with SMIC to include 28nm technology and wafer manufacturing service, we look forward to SMIC becoming a more important supplier in our supply chain strategy.”

Cadence Design Systems, Inc. and Applied Materials, Inc. today announced the companies are collaborating on a development program to optimize the chemical-mechanical planarization (CMP) process through silicon characterization and modeling for advanced-node designs at 14 nanometer (nm) and below. The program allows design teams to predict the impact of CMP on both functional yield and parametric yield, and for manufacturing teams to boost planarization performance, which is increasingly critical for advanced FinFET architectures.

The Cadence and Applied Materials joint development program is focused on front end-of-line (FEOL) and wafer-level CMP modeling. Applied Materials can use the Cadence CMP Process Optimizer, a tool that allows silicon calibration of semi-physical models and optimization of CMP material and process parameters such as pressure, polish time and overall CMP uniformity, to enhance the precision performance of its Reflexion LK Prime CMP system.

Once models are calibrated, design teams can leverage Cadence CMP Predictor, a tool that enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction. It provides full-chip, multi-level CMP thickness and topography predictions for shallow trench isolation (STI) and replacement metal gate (RMG) CMP processes.

Applied Materials is an industry leader in precision CMP technology with its Reflexion LK Prime CMP system that offers high-speed planarization and multi-zone polishing heads to enable superior uniformity and efficiency with low downforce for extendibility to <14nm device generations. The Reflexion LK Prime CMP system also implements a full suite of advanced process control capabilities that ensure excellent within-wafer and wafer-to-wafer process uniformity control and repeatability for all planarization applications.

“Working together with Cadence, we’re driving advances in CMP process performance,” said Derek Witty, vice president and general manager of the CMP Products Group at Applied Materials. “From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster.”

“Cadence CMP Predictor helps turn the uncertainty of manufacturing process variation into predictable impacts, and then minimizes these impacts during the design stage,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “The joint development program with Applied Materials can allow us to drive advancements in CMP modeling processes so our design and manufacturing customers can maximize design yield and performance.”

Graham Curren, Sondrel CEO, has announced his commitment to further investment in the training of graduate engineers looking to develop a career in the IC design sector, by providing a teaching fellow, and nine scholarship awards to students engaged on the Sondrel University of Nottingham Ningbo (UNNC) School of VLSI Design.

This unique program, created in partnership with the University of Nottingham, and with the support of Mentor Graphics, is now in its third year, with over 100 students having successfully completed the course, and progressing to take up positions in the semiconductor sector. The bilingual course is run on the University of Nottingham’s Ningbo Campus, in China, as a three month intensive industry training program. There are two intakes in 2015, at the end of June, and in September, with demand continuing to be strong from students looking to enhance their EE qualifications as well as those opting to embark on a new career path.

Commenting about the award, Professor Chris Rudd, Pro-Vice-Chancellor for External Engagement at The University of Nottingham, said: “I am delighted that Sondrel has agreed to provide a scholarship fund to support integrated circuit design students and a teaching fellow at UNNC. We have an excellent relationship with Sondrel and have worked together with them very successfully over the last couple of years on the programme at our Ningbo campus. This scholarship demonstrates their commitment to build on the success of the course and we look forward to working closely with them over the years ahead to train the next generation of integrated circuit designers.”

Graham Curren, CEO of Sondrel, added: “We firmly believe in developing our new graduate talent and specifically wanted to find and train more young people for an international career in our offices around the world. Our working environment is multi-cultural and excellent communication skills coupled with cross-cultural awareness are vital for conducting business in global markets including China. These IC designers are set for an exciting career working in partnership with our clients in Europe, the US and China.”

Information on the course can be obtained from the Nottingham University website, and the Sondrel website.

Related news: 

GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students

North America-based manufacturers of semiconductor equipment posted $1.56 billion in orders worldwide in May 2015 (three-month average basis) and a book-to-bill ratio of 0.99, according to the May EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 0.99 means that $99 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in May 2015 was $1.56 billion. The bookings figure is 0.8 percent lower than the final April 2015 level of $1.57 billion, and is 11.0 percent higher than the May 2014 order level of $1.41 billion.

The three-month average of worldwide billings in May 2015 was $1.57 billion. The billings figure is 3.7 percent higher than the final April 2015 level of $1.51 billion, and is 11.6 percent higher than the May 2014 billings level of $1.41 billion.

“The May book-to-bill ratio slipped below parity as billings improved and bookings dipped slightly from April’s values,” said Denny McGuirk, president and CEO of SEMI.  “Compared to one year ago, both bookings and billings continue to trend at higher levels.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
December 2014 

$1,395.9

$1,381.5

0.99
January 2015 

$1,279.1

$1,325.6

1.04
February 2015 

$1,280.1

$1,313.7

1.03
March 2015 

$1,265.6

$1,392.7

1.10
April 2015 (final)

$1,515.3

$1,573.7

1.04
May 2015 (prelim)

$1,571.2

$1,561.4

0.99

Source: SEMI (www.semi.org), June 2015

Since the global economic recession of 2008-2009, the IC industry has been on a mission to pare down older capacity (i.e., ≤200mm wafers) in order to produce devices more cost-effectively on larger wafers.  From 2009-2014, semiconductor manufacturers have closed or repurposed 83 wafer fabs, according to data compiled, updated, and now available in IC Insights’ Global Wafer Capacity 2015-2019 report.

Figure 1 shows that 41 percent of fab closures since 2009 have been 150mm fabs and 27 percent have been 200mm wafer fabs.  Qimonda was the first company to close a 300mm wafer fab after it went out of business in early 2009.  More recently, ProMOS and Powerchip closed their respective 300mm wafer fabs in 2013.

IC fabs Fig 1

 

Semiconductor suppliers in Japan have closed 34 wafer fabs since 2009, more than any other country/region over the past six years.   In the 2009-2014 timeframe, 25 fabs were closed in North America and 17 were shuttered in Europe (Figure 2).

IC fabs Fig 2

 

Worldwide fab closures surged in 2009 and 2010 partly as a result of the severe economic recession at the end of the previous decade.  A total of 25 fabs were closed in 2009, followed by 24 being shut down in 2010.  Ten fabs closed in 2012 and 12 were removed from service in 2013.  Six fabs were closed in both 2011 and in 2014, the fewest number of closures per year during the 2009-2014 time span.

Given the flurry of merger and acquisition activity seen in the semiconductor industry recently, the skyrocketing cost of new wafer fabs and manufacturing equipment, and as more IC companies transition to a fab-lite or fabless business model, IC Insights expects the number of fab closures to accelerate in the coming years—a prediction that will likely please foundry suppliers but make semiconductor equipment and material suppliers a little bit nervous.

DCG Systems, Inc. announced today that it has acquired the assets of MultiProbe, Inc., a provider of atomic force-based nanoprobing solutions for the semiconductor industry. MultiProbe was founded in 2001 to address the growing needs of failure analysis (FA) engineers and to help the industry find solutions for device technology development. DCG’s MultiProbe operations will remain in Santa Barbara, California.

Dr. Israel Niv, DCG Systems CEO and Mr. Andy Erickson, MultiProbe founder and CEO, sealing the acquisition.

Dr. Israel Niv, DCG Systems CEO and Mr. Andy Erickson, MultiProbe founder and CEO, sealing the acquisition.

“The AFP-based nanoprobers offered by MultiProbe complement DCG Systems’ SEM-based nanoprobing product portfolio,” said Dr. Israel Niv, Chief Executive Officer of DCG Systems, Inc. “Being able to call upon the strengths of two distinct technologies will help the combined companies better address the breadth of yield-limiting electrical fault issues that our diverse customer base is facing now and in the future.”

MultiProbe’s flagship product, the Hyperion, uses atomic force probe (AFP) technology to provide characterization and localization of electrical faults in transistors. The MultiProbe systems can also be operated in a mode called PicoCurrent imaging, which simultaneously displays variations in topography and conductivity, allowing engineers to quickly identify anomalous features that can be further investigated by transistor probing.

DCG’s flagship nanoprobing system, the nProber II, is built upon a scanning electron microscope (SEM) platform. Like the Hyperion, the nProber II system delivers electrical fault localization and characterization of transistors. The nProber II can also be operated in electron-beam current (EBC) mode to localize surface and sub-surface shorts, opens and resistive faults within interconnect structures.

“I am pleased to hand over the reins of MultiProbe to DCG Systems at a time when nanoprobing is becoming increasingly critical to yield engineering,” said Andy Erickson, founder and Chief Executive Officer of MultiProbe. “In addition, our customers will benefit from the strength of the combined worldwide applications and service team.”

Both the Hyperion and nProber II nanoprobing systems have been installed at multiple customer sites worldwide, where they are being used to accelerate development and yield of devices down to the 10nm node.

Headquartered in Fremont, California, DCG Systems, Inc. is a supplier of electrical fault characterization, localization and editing equipment, serving process development, yield ramp and failure analysis applications for a wide range of semiconductor and electronics manufacturers. DCG Systems has field offices in the United States, Japan, Taiwan, Korea, Malaysia, Singapore, Israel and Germany.

SEMI today announced that SEMICON West 2015 will feature the Silicon Innovation Forum (SIF), a unique forum for strategic investors and key decision makers to meet new and emerging early-stage companies developing the future of microelectronics.  SIF is organized by SEMI (www.semi.org) in partnership with top research institutes and strategic investment groups such as Applied Ventures, Intel Capital, Samsung Ventures, and more. The event is strategically co-located with SEMICON West (www.semiconwest.org) – the U.S. electronics manufacturing event.

“Investment in semiconductor equipment and materials is increasingly crowded out by VC’s interest in software, media and entertainment and biotechnology segments. Traditional venture capital and private attention to advanced semiconductor technology development has declined in recent years, putting the future of microelectronics innovation at risk. SIF helps accelerate R&D in our industry and encourages continued innovation from new sources,” said Karen Savala, president of SEMI Americas.

SIF brings together research institutes and emerging companies in the electronics manufacturing sector with the industry’s  strategic investors and leading technology partners ─ for a two-day forum of investor panels, startup pitches, round tables, keynotes, research forum and an innovator showcase.

The Silicon Innovation Forum will be held July 14 and 15 at Moscone Center in San Francisco, Calif.  SIF includes:

“Startup/Investor Forum” agenda (July 14):

·   “Investor Pitch” Session: SIF exhibitors present directly to a panel of top investors. Examples of exciting new technologies presented include:

— Silicon thermo electronic technology enabling wearable devices to operate using energy from body heat

— Low cost, 3D printing technology for mass production

— CMP slurries with nano-sized contact release capsules to enable planarization of high aspect ratio structures

— Power management IC with reduced footprint and thickness

— Sensors based on silicon germanium capable of detecting a broader range of the IR spectrum

— Radically new, biomedical applications for semiconductor technology

·   Investor Panel discussion

·   Awards

·   New this year: Innovation Village Startup Showcase and Research Park is a new exposition segment that includes 20 emerging startups and 10 breakthrough research organizations in an interactive exposition showcase arena.

“Research and Innovation” agenda (July 15):

 ·   Advanced Research: Includes presentations from: SLAC National Accelerator Laboratory, International Consortium for Advanced Manufacturing Research, SUNY Network of Excellence – Materials & Advanced Manufacturing, Novati Technologies, MIST Center, Micro/Nano Electronics Metrology at NIST, Texas State University and Georgia Tech Heat Lab

·   INNOVATE Keynote and Reception at Innovation Village: An exclusive networking session for investors, SIF exhibitors and session partners.  Advanced registration is required.

Attendees at the Silicon Innovation Forum will include entrepreneurs engaged in silicon innovation, investment professionals from angel, venture, corporate and institutional communities, and senior executives from the microelectronics industries.

For information on exhibiting at the Silicon Innovation Forum, contact Ray Morgan, SEMI Americas at [email protected] or visit www.semiconwest.org/sif.