Category Archives: Metrology

JSR Corporation, a materials company and imec, a nanoelectronics R&D center, today signed a Letter of Intent (LOI) to partner in enabling manufacturing and quality control of EUV lithography materials for the semiconductor industry. This partnership will be formalized by establishing a joint venture with imec as minority shareholder. The signing ceremony was held at the Embassy of the Kingdom of Belgium in Tokyo (Japan).

EUV lithography is considered as one of the main drivers to extend Moore’s law towards single digit nanometer technology nodes. Imec and JSR’s collaboration, will allow both companies to leverage their strengths when developing photoresist solutions for the semiconductor industry to manufacture the most advanced devices. JSR will provide manufacturing technology to the joint venture including upgrading the facility at its wholly-owned subsidiary in Belgium, JSR Micro NV, by installing manufacturing and analytical equipment. Imec will provide expertise and services to the joint venture for quality control on materials. In addition to the manufacturing of JSR brand photoresists, the joint venture will offer toll-manufacturing capability to other material suppliers with confidentiality secured.

“JSR has been a strategic partner of imec for a long time, and I am excited with this intensified collaboration,” stated Luc Van den hove, president and CEO at imec. “This collaboration strengthens our supplier hub concept, a neutral open innovation R&D platform that involves suppliers more deeply and at an early stage of process step and module development. The partnership enabled through close proximity between the JSR manufacturing facility and the imec technology platform will allow our partners to gain access to best-in-class materials for next-generation technologies.”

“We know that EUV lithography is required to realize Moore’s law in semiconductor manufacturing technologies and we continuously focus our R&D efforts to meet industry needs,” said Nobu Koshiba, President of JSR Corporation. “JSR has successfully developed not only chemically amplified photoresists, but also newly designed chemistries with very high sensitivity and good productivity. Our strength has also extended to peripheral materials, such as multilayer materials. The industry is requesting material suppliers to prepare manufacturing infrastructure and quality control capabilities for defect-free lithography solutions, as well as to improve photoresist performance to match EUV exposure equipment. It is by knowing those industry needs and requirements very well, that we, two world leading organizations that have supported the semiconductor industry for a long time, come to this unique idea to form a manufacturing joint venture to support those future industry needs. This is done based on our very long, trust-worthy relationship with imec. This is a very exciting challenge for us and I have great respect for imec for their brave and challenging spirits.”

Synthetic diamond heat spreaders and GaN-on-Diamond wafers have emerged as a leading thermal-management technology for RF Power Amplifiers

BY THOMAS OBELOER, DANIEL TWITCHEN, JULIAN ELLIS, BRUCE BOLLIGER,
Element Six Technologies, Santa Clara, CA & MARTIN KUBALL AND JULIAN ANAYA, Center for Device Thermography and Reliability (CDTR), H. H. Wills Physics Laboratory, University of Bristol, Bristol, U.K.

GaN-based transistors and their related RF Power Amplifiers (PAs) have emerged as the leading solid-state technology to replace traveling wave tubes in radar, EW (Electronic warfare) systems, and satellite communications, and to replace GaAs transistors in cellular base stations. However, significant thermal limitations prevent GaN PAs from reaching their intrinsic performance capability. Metallized synthetic diamond heat spreaders have recently been used to address this thermal management challenge, particularly in cellular base station and military radar applications.

This article covers several important issues that advanced thermal solutions, particularly for RF power amplifiers, must address. Here, we are presenting new materials, such as CVD (chemical vapor deposition) diamond as a heat spreader to reduce overall package thermal resistance compared to today’s more commonly used materials for thermal management. Also, mounting aspects and some new developments regarding the thermal resistance at the bonding interfaces to diamond heat spreaders are discussed.

CVD diamond

Diamond possesses an extraordinary set of properties including the highest known thermal conductivity, stiffness and hardness, combined with high optical transmission across a wide wavelength range, low expansion coefficient, and low density. These characteristics can make diamond a material of choice for thermal management to significantly reduce thermal resis- tance. CVD diamond is now readily commercially available in different grades with thermal conductivities ranging from 1000 to 2000 W/mK. Also very important is the fact that CVD diamond can be engineered to have fully isotropic characteristics, enabling enhanced heat spreading in all directions. FIGURE 1 shows a comparison of the thermal conductivity of CVD diamond with other materials traditionally used for heat spreading purposes.

FIGURE 1. Comparison of thermal conductivity of CVD diamond and traditional heat spreading materials [1, 2].

FIGURE 1. Comparison of thermal conductivity of CVD diamond and traditional heat spreading materials [1, 2].

On-going development in the technologies to synthesize CVD diamond has enabled it to become readily available in volume at acceptable costs. Unmetallized CVD diamond heat spreaders are available today at a typical volume cost of $1/mm3. Prices vary dependant on the thermal-conductivity grade used. In some instances, system operation at elevated temperatures can reduce both the initial cost of the cooling sub-system and the on-going operating cost as well. When applied with appropriate die-attach methods, diamond heat spreaders provide reliable solutions for semiconductor packages with significant thermal management challenges [1].

Application notes for the use of CVD Diamond

To obtain the most effective use of the extreme properties of CVD Diamond in overall system design, package integration issues need to be carefully considered. Failure to address any one of these issues will result in a sub-optimal thermal solution. Here are the most important points to be considered:

  • Surface preparation
  • Mounting techniques
  • Diamond thickness
  • Functional considerations
  • Metallizations and thermal barrier resistance

Surface preparation: The surfaces of die-level devices have to be machined in a suitable fashion to allow good heat transfer. Surface flatness for heat spreaders should typically be less than 1 micron/mm and the roughness better than Ra < 50 nm, which can be achieved by polishing techniques. Any deficiency in flatness must be compensated for by the mounting techniques which will cause higher thermal resistance.

Mounting techniques: Whereas in some advanced device applications, such as high-power laser diodes, atomic-force bonding techniques are being considered, most applications currently employ soldering techniques for die attachment to the heat spreader. Again, solder layers should be kept to minimum thickness, particularly for the primary TIM1 (thermal interface material (TIM) between die and heat spreader), to minimize thermal resistance. An important factor in applying solder joints is the expansion mismatch between the CVD diamond and the semiconductor material, as it can significantly influence performance and lifetime. GaAs (Gallium Arsenide) devices up to an edge length of 2.5 mm can be hard soldered to CVD diamond without CTE-mismatch problems. (Note that the CTE for CVD Diamond is 1.0 ppm/K at 300K). For edge lengths greater than 2.5 mm, using a soft solder can avoid excessive stresses in the device. TABLE 1 shows a wide range of solder materials commercially available to address various needs for soldering processes.

TABLE 1. Summary of soldering materials [2].

TABLE 1. Summary of soldering materials [2].

Diamond thickness: The thickness of the CVD diamond is important. For devices with small hot spots, such as RF amplifiers or laser diodes, a thickness of 250 to 400 microns is sufficient. Diamond’s isotropic characteristics effectively spread the heat to reduce maximum operation temperature at constant power output. However, applications with larger heat spots on the order of 1 to 10 mm in diameter require thicker diamond for better results. An example is disk lasers that can have an optical output power of several kW and a power density of about 2kW/cm2; a diamond thickness of several mm has proven to be beneficial to disk laser operation [3].

Functional considerations: There are also functional requirements that may be important. One is the electrical conductivity of the heat spreader. For devices such as laser diodes, it is easiest to run the drive current through the device and use the heat spreader for the ground contact. For other devices, the heat spreader is required to be insulating. As CVD diamond is an intrinsic insulator, this insulation can be maintained by keeping the side faces free of metallization. This could be required for RF amplifiers and transistors, especially at higher frequencies (f > 2 GHz).

Thermal simulation helps optimize the heat spreader configuration to find the best solution based on power output needs, material thickness, metallization scheme, heat source geometry and package configuration. For design optimization, it is important that the thermal simulation model includes the complete junction-to-case system, including the device details, all interfaces, materials and the subsequent heat sinking solution.

Metallizations and thermal barrier resistance

Metallizations are an essential component to the application of CVD diamond in RF Amplifier and similar applications. Typically, for reasons of adhesion, mechanical and thermal robustness, three-layer metallization schemes are used. An example of such a three-layer metallization scheme fundamentally comprises: a) a carbide forming metal layer which forms a carbide bonding to the diamond component; b) a diffusion barrier metal layer disposed over the carbide forming metal layer; and c) a surface metal bonding layer disposed over the diffusion barrier metal which provides both a protective layer and a wettable surface layer onto which a metal solder or metal braze can be applied to bond the diamond heat spreader to die and other device components. A particular example of such a three-layer metalli- zation scheme is Ti / Pt / Au.

High-quality, sputter-deposited, thin-film metallizations are strongly recommended for advanced thermal solutions. As thermal contact resistance between the device
and the heat spreader must be minimized, any additional metal interface being added to the system must be avoided. Sputtered layers, especially of titanium, can form a very effective chemical bond with CVD diamond to ensure long-term stability even at elevated temperatures. To separate the required gold attach layer from the titanium adhesion layer, a platinum or titanium/tungsten (TiW) barrier layer is recommended. The Ti/Pt/Au scheme is very commonly used in high-end devices and has excellent characteristics with regards to stability and endurance, even over extended lifetime periods under changing thermal loads. However, this scheme also has a drawback, as the thermal conductivities of the titanium and platinum are relatively low (Tc=22 W/ mK and Tc=70 W/mK respectively). In the search for improved materials to be applied, the use of chromium has been identified as a viable alter- native. Chromium forms a carbide with diamond and is also readily used as a barrier layer, enabling it to perform both functions at a relatively high thermal conductivity of Tc=93.9 W/mk. To test the thermal effectiveness of chromium, samples were prepared at the CDTR (Centre for Device Thermog- raphy and Reliability) at Bristol University comparing a standard Ti/Pt/Au (100/120/500nm) metallization with this novel Cr/Au (100/500nm) configuration. The measurements of the thermal conductivity revealed that the thermal conduc- tivity of the Cr/Au metallization is about 4 times higher as compared to the Ti/Pt/Au. Results are shown in FIGURE 2.

FIGURE 2. Comparison of thermal conductivity of different metallization schemes [4].

FIGURE 2. Comparison of thermal conductivity of different metallization schemes [4].

Application example

To demonstrate the impact of this Cr adhesion/ barrier layer advantage versus Ti/Pt/Au, high power GaN on SiC HEMT (High Electron Mobility Transistor) devices were mounted to a CVD Diamond heat spreader. A cap layer of AuSn with a thickness of 25 microns was chosen. To ensure comparable results for all samples prepared, these samples were placed on a temperature stable platform also made from high thermally conductive diamond material. Results are shown in FIGURE 3: In the left diagram, the base temperature is plotted for increasing power output from the device. As can be seen, the temperature for the Cr/Au configuration is significantly lower, at 9W device power output by about 10 degrees C. On the right hand side, the graph shows the temperature as measured on the transistor channel directly.

FIGURE 3. Temperatures as a function of power for different metallization schemes and solder thickness [4].

FIGURE 3. Temperatures as a function of power for different metallization schemes and solder thickness [4].

In this case, the lower thermal resistivity of the Cr-based metallization layer decreases the channel temperature by more than 20 degrees C at 9W power output.

This significant temperature reduction will result in as much as a 4 times longer lifetime of the device. Alternatively, such devices could be packaged in smaller footprints, at higher power densities, to make use of this increased effectiveness in heat spreading.

Outlook, future developments

One important finding from the above example is the need to modify device architecture for improved thermal management. The main temperature rise is within the device itself. Here, a thinning of the substrate, to bring it closer to the diamond heat spreader, would further enhance the thermal design. Also, mounting such devices with the active layers facing the diamond would provide even further benefit. An example would be the mounting laser diodes p-face down with the quantum well structures soldered directly against the heat spreader. Another way to bring the device gate junction closer to the diamond is the use of a different substrate altogether. This has been demonstrated by using GaN (Gallium Nitride) on diamond wafers, which remove both the Si substrate and transition layers, replacing them instead with CVD diamond [5]. The result brings the diamond material within 1 micron of the heat generating gate junctions. Initial users of GaN-on-diamond wafers for RF HEMT devices have demon- strated as much as 3 times the power density when compared to equivalent GaN/SiC (Silicon Carbide) devices, today’s leading technology for advanced power devices. [6]

Summary

As can be seen, significant thermal-management improvements to electronic systems can be realized by using advanced materials such as CVD diamond. The integration can be relatively straightforward as the diamond heat spreader can be a direct replacement to AlN (Aluminium nitride), BeO (Berillium oxide) or other advanced ceramics. Attention to detail at the interfaces, both in terms of the choice of metals and its thickness, is important to keep overall thermal resistance low and thereby optimizing the effectiveness of the diamond.

As CVD diamond becomes more attractive as a heat spreader through improved synthesis technology, advanced processing and on-going cost reduction efforts, its use in high power density applications has been increasing. It is expected that this trend will be continued in the years to come in line with the ever increasing need for smaller and more powerful electronic devices and systems.

References

1. R. Balmer, B. Bolliger “Integrating Diamond to Maximize Chip Reliability and Performance,“ in Chip Scale Review, July/August 2013, pp. 26 – 30.
2. Internal Element Six Technologies research and report.
3. Element Six internal thermal simulation, C. Bibbe, 2006.
4. GaN-on-Diamond High-Electron-Mobility Transistor – Impact of Contact and Transition Layers, J.Anaya, J.W. Pomeroy, M. Kuball, Center for Device Thermography and Reliability (CDTR), H. H. Wills Physics Laboratory, University of Bristol, BS8 1TL Bristol, U.K.
5. G.D. Via, J.G. Felbinger, J. Blevins, K. Chabak, G. Jessen, J. Gillespie, R. Fitch, A. Crespo, K. Sutherlin,
B. Poling, S. Tetlak, R. Gilbert, T. Cooper, R. Baranyai, J.W. Pomeroy, M. Kuball, J.J. Maurer, and A. Bar-Cohen,
“Wafer-Scale GaN HEMT Performance Enhancement
by Diamond Substrate Integration” in 10th Interna- tional Conference on Nitride Semiconductors, ICNS-10, August 25-30, 2013, Washington DC, USA.
6. M. Tyhach, D. Altman, and S. Bernstein, “Analysis and Characterization of Thermal Transport in GaN HEMTs on SiC and Diamond Substrates”, in GOMACTech 2014, March 31-April 3, 2014, Charleston, SC, USA.

THOMAS OBELOER, DANIEL TWITCHEN, JULIAN ELLIS, BRUCE BOLLIGER, Element Six Technologies, Santa Clara, CA

MARTIN KUBALL AND JULIAN ANAYA, Center For Device Thermography And Reliability (Cdtr), H. H. Wills Physics Laboratory, University Of Bristol, Bristol, U.K. contact: [email protected]

A new study coauthored by Wellesley economist, Professor Daniel E. Sichel, reveals that innovation in an important technology sector is happening faster than experts had previously thought, creating a backdrop for better economic times ahead.

The Producer Price Index (PPI) of the United States suggests that the prices of semiconductors have barely fallen in recent years. The slow decline in semiconductor prices stands in sharp contrast to the rapidly falling prices reported from the mid-1980s to the early 2000s, and has been interpreted as a signal of sluggish innovation in this key sector.

The apparent slowdown puzzled Sichel and his coauthors, David M. Byrne of the Federal Reserve Board, and Stephen D. Oliner, of the American Enterprise Institute and UCLA–particularly in light of evidence that the performance of microprocessor units (MPUs), which account for about half of U.S. semiconductor shipments, has continued to improve at rapid pace. After closely examining historical pricing data, the economists found that Intel, the leading producer of MPUs, dramatically changed the way it priced these chips in the mid-2000s–roughly the same time when the slowdown reported by government data occurs. Prior to this period, Intel typically lowered the list prices of older chips to remain competitive with newly introduced chips. However, after 2006, Intel began to keep chip prices relatively unchanged over their life cycle, which affected official statistics.

To obtain a more accurate assessment of the pace of innovation in this important sector, Sichel, Byrne, and Oliner developed an alternative method of measurement that evaluates changes in actual MPU performance to gauge the rate of improvement in price-performance ratios. The economists’ preferred index shows that quality-adjusted MPU prices continued to fall rapidly after the mid-2000s, contrary to what the PPI indicates–meaning that worries about a slowdown in this sector are likely unwarranted.

According to Sichel, these results have important implications, not only for understanding the rate of technological progress in the semiconductor industry but also for the broader debate about the pace of innovation in the U.S. economy.

“These findings give us reason to be optimistic,” said Sichel. “If technical change in this part of the economy is still rapid, it provides hope for better times ahead.”

Sichel and his coauthors also acknowledge that their results raise a new puzzle. “In recent years,” they write, “the price index for computing equipment has fallen quite slowly by historical standards. If MPU prices have, in fact, continued to decline rapidly, why have prices for computers–which rely on MPUs for their performance–not followed suit?” The researchers believe it is possible that the official price indexes for computers may also suffer from measurement issues, and they are investigating this possibility in further work.

“How Fast Are Semiconductor Prices Falling,” coauthored by Daniel E. Sichel, Wellesley College and NBER; David M. Byrne, Federal Reserve Board; and Stephen D. Oliner, American Enterprise Institute and UCLA, is available as an NBER working paper and is online at http://www.nber.org/papers/w21074 and https://www.aei.org/publication/how-fast-are-semiconductor-prices-falling/.

Brewer Science, Inc., and Nissan Chemical Industries, Ltd., announced they have formally extended their business relationship through 2028. For nearly 20 years, Brewer Science has licensed its ARC technology to Nissan Chemical, and the agreement was soon to expire.

This new agreement focuses on continuing access to an expanded portfolio of the most advanced ARC and OptiStack materials, and allows access to a dual supply of products from Brewer Science and Nissan Chemical under a new joint label to customers in Asia. Both companies are committed to guaranteeing business and industry continuity by providing an uninterrupted leading-edge product supply for customers in Asia into the future.

“Our customers in Asia will notice a new logo on the products they receive through Nissan Chemical,” said Dr. Terry Brewer, founder and CEO of Brewer Science. “The logo symbolizes the continuing commitment made by Brewer Science and Nissan Chemical to support customers with world-class products and service. We are focused on discovering unique and creative solutions that enable our customers to meet tomorrow’s industry challenges.”

“Brewer Science and Nissan Chemical have been business partners for nearly two decades, and this new agreement will bring us even further. Such an agreement doesn’t happen very often,” said Kojiro Kinoshita, CEO of Nissan Chemical. “We have a shared vision with Brewer Science, and our customers in Asia will continuously receive the best solution with enhanced products and sharpened services from this partnership, which is always our goal.”

The formal relationship between Brewer Science and Nissan Chemical began in 1997 and will continue to build on their commitment of collaboration in providing the global marketplace with an expanding supply of original technology products of superior performance and quality.

In 2013 James Hone, Wang Fong-Jen Professor of Mechanical Engineering at Columbia Engineering, and colleagues at Columbia demonstrated that they could dramatically improve the performance of graphene–highly conducting two-dimensional (2D) carbon–by encapsulating it in boron nitride (BN), an insulating material with a similar layered structure. In work published this week in the Advance Online Publication on Nature Nanotechnology‘s website, researchers at Columbia Engineering, Harvard, Cornell, University of Minnesota, Yonsei University in Korea, Danish Technical University, and the Japanese National Institute of Materials Science have shown that the performance of another 2D material–molybdenum disulfide (MoS2)–can be similarly improved by BN-encapsulation.

“These findings provide a demonstration of how to study all 2D materials,” says Hone, leader of this new study and director of Columbia’s NSF-funded Materials Research Science and Engineering Center. “Our combination of BN and graphene electrodes is like a ‘socket’ into which we can place many other materials and study them in an extremely clean environment to understand their true properties and potential. This holds great promise for a broad range of applications including high-performance electronics, detection and emission of light, and chemical/bio-sensing.”

Two-dimensional (2D) materials created by “peeling'” atomically thin layers from bulk crystals are extremely stretchable, optically transparent, and can be combined with each other and with conventional electronics in entirely new ways. But these materials–in which all atoms are at the surface–are by their nature extremely sensitive to their environment, and their performance often falls far short of theoretical limits due to contamination and trapped charges in surrounding insulating layers. The BN-encapsulated graphene that Hone’s group produced last year has 50× improved electronic mobility–an important measure of electronic performance–and lower disorder that enables the study of rich new phenomena at low temperature and high magnetic fields.

“We wanted to see what we could do with MoS2–it’s the best-studied 2D semiconductor, and, unlike graphene, it can form a transistor that can be switched fully ‘off’, a property crucial for digital circuits,” notes Gwan-Hyoung Lee, co-lead author on the paper and assistant professor of materials science at Yonsei. In the past, MoS2 devices made on common insulating substrates such as silicon dioxide have shown mobility that falls below theoretical predictions, varies from sample to sample, and remains low upon cooling to low temperatures, all indications of a disordered material. Researchers have not known whether the disorder was due to the substrate, as in the case of graphene, or due to imperfections in the material itself.

In the new work, Hone’s team created heterostructures, or layered stacks, of MoS2 encapsulated in BN, with small flakes of graphene overlapping the edge of the MoS2 to act as electrical contacts. They found that the room-temperature mobility was improved by a factor of about 2, approaching the intrinsic limit. Upon cooling to low temperature, the mobility increased dramatically, reaching values 5-50× that those measured previously (depending on the number of atomic layers). As a further sign of low disorder, these high-mobility samples also showed strong oscillations in resistance with magnetic field, which had not been previously seen in any 2D semiconductor.

“This new device structure enables us to study quantum transport behavior in this material at low temperature for the first time,” added Columbia Engineering PhD student Xu Cui, the first author of the paper.

By analyzing the low-temperature resistance and quantum oscillations, the team was able to conclude that the main source of disorder remains contamination at the interfaces, indicating that further improvements are possible.

“This work motivates us to further improve our device assembly techniques, since we have not yet reached the intrinsic limit for this material,” Hone says. “With further progress, we hope to establish 2D semiconductors as a new family of electronic materials that rival the performance of conventional semiconductor heterostructures–but are created using scotch tape on a lab-bench instead of expensive high-vacuum systems.”

Applied Materials, Inc. and Tokyo Electron Limited today announced that they have agreed to terminate their Business Combination Agreement (BCA). No termination fees will be payable by either party.

The decision came after the U.S. Department of Justice (DoJ) advised the parties that the coordinated remedy proposal submitted to all regulators would not be sufficient to replace the competition lost from the merger. Based on the DoJ’s position, Applied Materials and Tokyo Electron have determined that there is no realistic prospect for the completion of the merger.

“We viewed the merger as an opportunity to accelerate our strategy and worked hard to make it happen,” said Gary Dickerson, president and chief executive officer of Applied Materials. “While we are disappointed that we are not able to pursue this path, our existing growth strategy is compelling. We have been relentlessly driving this strategy forward and we have made significant progress towards our goals. We are delivering results and gaining share in the semiconductor and display equipment markets, while making meaningful advances in areas that represent the biggest and best growth opportunities for us.

“I would like to thank our employees for their focus on delivering results throughout this process. As we move forward, Applied Materials has tremendous opportunities to leverage our differentiated capabilities and technology in precision materials engineering and drive a significant increase in the value we create for our customers and investors.”

By Paula Doe, SEMI

In this 50th year anniversary of Moore’s Law, the steady scaling of silicon chips’ cost and performance that has so changed our world over the last half century is now poised to change it even further through the Internet of Things, in ways we can’t yet imagine, suggests Intel VP of IoT Doug Davis, who will give the keynote at SEMICON West (July 14-16) this year.  Powerful sensors, processors, and communications now make it possible to bring more intelligent analysis of the greater context to many industrial decisions for potentially significant returns, which will drive the first round of serious adoption of the IoT. But there is also huge potential for adding microprocessor intelligence to all sorts of everyday objects and connecting them with outside information, to solve all sorts of real problems, from saving energy to saving babies’ lives. “We see a big impact on the chip industry,” says Davis, noting the needs to deal with highly fragmented markets, as well to reduce power, improve connectivity, and find ways to assure security.

The end of the era of custom embedded designs?

The IoT may mean the end of the era of embedded chips, argues Paul Brody, IBM’s former VP of IoT, who moves to a new job this month, one of the speakers in the SEMICON West TechXPOT program on the impact of the IoT on the semiconductor sector.  Originally, custom embedded solutions offered the potential to design just the desired features, at some higher engineering cost, to reduce the total cost of the device as much as possible. Now, however, high volumes of mobile gear and open Android systems have brought the cost of a loaded system on a chip with a dual core processor, a gigabit of DRAM and GPS down to only $10.  “The SoC will become so cheap that people won’t do custom anymore,” says Brody. “They’ll just put an SoC in every doorknob and window frame.  The custom engineering will increasingly be in the software.”

Security of all these connected devices will require re-thinking as well, since securing all the endpoints, down to every light bulb, is essentially impossible, and supposedly trusted parties have turned out not to be so trustworthy after all. “With these SoCs everywhere, the cost of distributed compute power will become zero,” he argues, noting that will drive systems towards more distributed processing.  One option for security then could be a block chain system like that used by Bit Coin, which allows coordination with no central control, and when not all the players are trustworthy. Instead of central coordination, each message is broadcast to all nodes, and approved by the vote of the majority, requiring only that the majority of the points be trustworthy.

While much of the high volume IoT demand may be for relatively standard, low cost chips, the high value opportunity for chip makers may increasingly be in design and engineering services for the expanding universe of customers. “Past waves of growth were driven by computer companies, but as computing goes into everything this time, it will be makers of things like Viking ranges and Herman Miller office furniture who will driving the applications, who will need much more help from their suppliers,” he suggests.

Intel Graphics

Source: Intel, 2015

Adding context to the data from the tool

The semiconductor industry has long been a leader in connecting things in the factory, from early M2M for remote access for service management and improving overall equipment effectiveness, to the increased automation and software management of 300mm manufacturing, points out Jeremy Read, Applied Materials VP of Manufacturing Services, who’ll be speaking in another SEMICON West 2015 program on how the semiconductor sector will use the IoT. But even in today’s highly connected fabs, the connections so far are still limited to linking individual elements for dedicated applications specifically targeting a single end, such as process control, yield improvement, scheduling or dispatching.  These applications, perhaps best described as intermediate between M2M and IoT, have provided huge value, and have seen enormous growth in complexity. “We have seen fabs holding 50 TB of data at the 45nm node, increasing to 140 TB in 20nm manufacturing,” he notes.

Now the full IoT vision is to converge this operational technology (OT) of connected things in the factory with the global enterprise (IT) network, to allow new ways to monitor, search and manage these elements to provide as yet unachievable levels of manufacturing performance. “However, we’ve learned that just throwing powerful computational resources at terabytes of unstructured data is not effective – we need to understand the shared CONTEXT of the tools, the process physics, and the device/design intent to arrive at meaningful and actionable knowledge,” says Read.  He notes that for the next step towards an “Internet-of-semiconductor-manufacturing-things” we will need to develop the means to apply new analytical and optimizing applications to both the data and its full manufacturing context, to achieve truly new kinds of understanding.

With comprehensive data and complete context information it will become possible to transform the service capability in a truly radical fashion – customer engineers can use the power of cloud computation and massive data management to arrive at insights into the precise condition of tools, potentially including the ability to predict failures or changes in processing capability. “This does require customers to allow service providers to come fully equipped into the fab – not locking out all use of such capabilities,” he says. “If we are to realize the full potential of these opportunities, we must first meet these challenges of security and IP protection.”

Besides these programs on the realistic impact of the IoT on the semiconductor manufacturing technology sector, SEMICON West 2015, July 14-16 in San Francisco, will also feature related programs on what’s coming next across MEMS, digital health, embedded nonvolatile memory, flexible/hybrid systems, and connected/autonomous cars.  

North America-based manufacturers of semiconductor equipment posted $1.37 billion in orders worldwide in March 2015 (three-month average basis) and a book-to-bill ratio of 1.10, according to the March EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in March 2015 was $1.37 billion. The bookings figure is 4.6 percent higher than the final February 2015 level of $1.31 billion, and is 5.9 percent higher than the March 2014 order level of $1.30 billion.

The three-month average of worldwide billings in March 2015 was $1.25 billion. The billings figure is 2.4 percent lower than the final February 2015 level of $1.28 billion, and is 1.9 percent higher than the March 2014 billings level of $1.23 billion.

““Three-month average bookings reported by North American-based semiconductor manufacturing equipment providers reflected sequential and year-over-year momentum in the first quarter of 2015,”” said SEMI president and CEO Denny McGuirk. “This marks the third consecutive month that bookings exceeded billing and the ratio remained above parity.””

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
October 2014 

$1,184.2

$1,102.3

0.93
November 2014 

$1,189.4

$1,216.8

1.02
December 2014 

$1,395.9

$1,381.5

0.99
January 2015 

$1,279.1

$1,325.6

1.04
February 2015 (final)

$1,280.1

$1,313.7

1.03
March 2015 (prelim)

$1,249.1

$1,374.4

1.10

Source: SEMI, April 2015

IC Insights will release its April Update to the 2015 McClean Report later this month. The Update includes the final 2014 company sales rankings for the top 50 semiconductor and top 50 IC companies, and the leading IC foundries. Also included are 2014 IC company sales rankings for various IC product segments (e.g., DRAM, MPU, etc.).

In 2014, there were only two Japanese companies—Toshiba and Renesas—that were among the top 10 semiconductor suppliers (Figure 1). Assuming the NXP/Freescale merger is completed later this year, IC Insights forecasts that Toshiba will be the lone Japanese company left in the top 10 ranking. Anyone who has been involved in the semiconductor industry for a reasonable amount of time realizes this is a major shift and a big departure for a country that once was feared and revered when it came to its semiconductor sales presence in the global market.

Fig 1

Fig 1

Figure 1 traces the top 10 semiconductor companies dating back to 1990, when Japanese semiconductor manufacturers wielded their greatest influence on the global stage and held six of the top 10 positions.  The six Japanese companies that were counted among the top 10 semiconductor suppliers in 1990 is a number that has not been matched by any country or region since (although the U.S. had five suppliers in the top 10 in 2014). The number of Japanese companies ranked in the top 10 in semiconductor sales slipped to four in 1995, fell to three companies in 2000 and 2006, and then to only two companies in 2014.

Figure 1 also shows that, in total, the top 10 semiconductor sales leaders are making a marketshare comeback. After reaching a marketshare low of 45 percent in 2006, the top 10 semiconductor sales leaders held a 53 percent share of the total semiconductor market in 2014.  Although the top 10 share in 2014 was eight points higher than in 2006, it was still six points below the 59 percent share they held in 1990.  As fewer suppliers are able to achieve the economies of scale needed to successfully invest and compete in the semiconductor industry, it is expected that the top 10 share of the worldwide semiconductor market will continue to slowly increase over the next few years.

Today, KLA-Tencor Corporation announced two new systems that support advanced semiconductor packaging technologies: CIRCL-AP and ICOS T830. Designed for characterization and monitoring of the diverse processes used in wafer-level packaging, CIRCL-AP enables all-surface wafer defect inspection, review and metrology at high throughput. The ICOS T830 provides fully automated optical inspection of integrated circuit (IC) packages, leveraging high sensitivity with 2D and 3D measurements to determine final package quality for a wide range of device types and sizes. Both systems help IC manufacturers and outsourced semiconductor assembly and test (OSAT) facilities address challenges, such as finer feature sizes and tighter pitch requirements, as they adopt innovative packaging techniques.

“Consumer mobile electronics continue to drive production of smaller, faster and more powerful devices,” stated Brian Trafas, chief marketing officer of KLA-Tencor. “Advanced packaging technologies offer device performance advantages, such as increased bandwidth and improved energy efficiency. The packaging production methods, however, are more complex—involving the implementation of typical front-end IC manufacturing processes, such as chemical mechanical planarization and high aspect ratio etch, and unique processes, such as temporary bonding and wafer reconstitution. By combining our expertise in front-end semiconductor manufacturing process control with experience gained through collaborations at key R&D sites and industry consortia, we have developed flexible and efficient inspection solutions that can help address packaging challenges from wafer-level to final component.”

The CIRCL-AP includes multiple modules that utilize parallel data collection for fast, cost-efficient process control of advanced wafer-level packaging processes. It supports a range of packaging technologies, including wafer-level chip scale packaging, fan-out wafer-level packaging and 2.5D/3D IC integration using through silicon vias (TSVs). The industry-proven 8-Series serves as the CIRCL-AP’s front side defect inspection and metrology module, which couples LED scanning technology with automated defect binning to reduce nuisance and speed detection of critical packaging defects, such as TSV cracks and redistribution layer shorts. The CV350i module, based on KLA-Tencor’s VisEdge technology, enables leading detection, binning and automated review of wafer edge defects and metrology for critical edge trim and bonding steps in the TSV process flow. With multiple imaging and illumination modes, the Micro300 module can produce high precision 2D and 3D metrology for bump, redistribution and TSV processes. Utilizing a flexible architecture, the CIRCL-AP can be configured with one or more modules to address the requirements of specific packaging applications, while the handler supports bonded, thinned and warped substrates.

The ICOS T830 extends the industry-leading ICOS component inspection series to address yield challenges associated with advanced packaging types, including lead frame, fan-out wafer-level, flip-chip and stacked packages. Enhanced package visual inspection capability, xPVI, enables high sensitivity detection of top and bottom component surface defects, such as voids, scratches, pits, chips and exposed wires. To ensure quality standards are being met for leading-edge memory and logic packaged devices, the ICOS T830 offers high speed 3D ball, lead and capacitor metrology, package z-height measurement and component side inspection. The xCrack+ inspection station enables accurate detection of micro-crack defects—a key failure mechanism of thinner components used in mobile applications. The ICOS T830 incorporates high-throughput operation of four independent inspection stations and high-speed sorting of the inspected packaged components to achieve cost-effective component quality control.

Multiple CIRCL-AP systems in various configurations have been installed worldwide for use in development and production of TSV, fan-out wafer-level packaging and other wafer-level packaging technologies. ICOS T830 systems are in use at many worldwide IC packaging facilities, providing accurate feedback on package quality across a range of device types and sizes. To maintain the high performance and productivity demanded by semiconductor packaging providers, the CIRCL-AP and ICOS T830 systems are backed by KLA-Tencor’s global, comprehensive service network.