Reno Sub-Systems (Reno) today announced that it has closed its first venture funding round with Intel Capital, early stage Canadian venture capital organization Innovacorp and other investors. Support from these investors will help Reno’s efforts to bring innovative technologies to market and enable next generation advanced semiconductor manufacturing process technology nodes.
Reno designs, develops and delivers sub-systems used to control process systems made by Original Equipment Manufacturers (OEMs), including vacuum-based chambers to deposit and etch specialty materials needed in advanced integrated circuit (IC) fabrication. Reno’s initial sub-system offerings provide RF-power generation and matching, process gas delivery and high- vacuum process control that radically changes the processing speed, range, development and total cost of ownership.
“Reno impresses us as a young company working to advance Moore’s Law,” said Bob Bruck, Vice President and General Manager of Global Supply Management at Intel. “We are pleased to support their efforts to develop innovative solutions for semiconductor capital equipment sub-systems.” Intel Capital’s investment was led by Director Sean Doyle.
“Demand for integrated circuits continues to grow exponentially. Reno has developed evolutionary technologies that allow semiconductor manufacturers to fulfill market demand – faster and at a lower cost than the competition,” said Gregory Phipps, managing director of investment at Innovacorp. “Innovacorp is excited to join Intel Capital in supporting Reno and its growth and commercialization objectives.”
“We are very grateful that our investors understand and support our vision to create radically better solutions to address the manufacturing challenges facing the global micro-electronics industry,”
The Global Semiconductor Alliance (GSA) is pleased to announce the 2014 award nominees for the GSA Awards Dinner Celebration taking place on Thursday, December 11, 2014, at the Santa Clara Convention Center in Santa Clara, Calif. GSA is celebrating 20 years of industry collaboration this year and over the past 20 years the awards program has recognized companies that have demonstrated excellence through their vision, strategy, execution and future opportunity. The commemorative celebration will honor the achievements of semiconductor companies in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry.
This year, in recognition of GSA’s 20 years of global collaboration, there will be a special presentation honoring past Dr. Morris Chang Exemplary Leadership Award recipients, GSA’s most prestigious award. The evening will culminate with a keynote by Jay Leno.
The evening’s program will recognize leading semiconductor companies that have exhibited market growth through technological innovation and exceptional business management strategies. The award categories and nominees (in alphabetical order) are as follows:
Start-Up to Watch Award
- Ineda Systems Pvt. Ltd.
- Movidius
- XMOS Ltd.
Most Respected Private Semiconductor Company Award
- Aquantia Corporation
- Quantenna Communications, Inc.
- Spreadtrum Communications, Inc.
Most Respected Emerging Public Semiconductor Company Award (Achieving $100 to $250 Million in Annual Sales):
- Ambarella, Inc.
- Nordic Semiconductor
- Silicon Motion Technology Corporation (Silicon Motion, Inc.)
Most Respected Public Semiconductor Company Award (Achieving $251 Million to $1 Billion in Annual Sales)
- InvenSense, Inc.
- Silicon Labs
- Synaptics, Inc.
Most Respected Public Semiconductor Company Award (Achieving Greater than $1 Billion in Annual Sales)
- Avago Technologies
- MediaTek Inc.
- QUALCOMM Incorporated
Best Financially Managed Semiconductor Company Award (Achieving Up to $500 Million in Annual Sales):
- Ambarella, Inc.
- Monolithic Power Systems
- Montage Technology
Best Financially Managed Semiconductor Company Award (Achieving Greater than $500 Million in Annual Sales)
- MediaTek Inc.
- QUALCOMM Incorporated
- Skyworks Solutions, Inc.
Analyst Favorite Semiconductor Company Award Nominees (chosen by analyst Rajvindra Gill of Needham & Company, LLC)
- Micron Technology, Inc.
- Spansion, Inc.
- Synaptics, Inc.
Outstanding Asia Pacific Semiconductor Company Award
- MediaTek Inc.
- Samsung Electronics Co., Ltd.
- Spreadtrum Communications, Inc.
Outstanding EMEA Semiconductor Company Award
- ams AG
- Infineon Technologies AG
- Sensirion AG
The dinner is made possible by title sponsor TSMC, VIP and networking reception sponsor Optimal+, as well as general sponsors Advantest, Alix Partners, Altera, AMD, Amkor, ARM, ASE Group, Broadcom, Cadence Design Systems, CSR, eSilicon, GLOBALFOUNDRIES, IBM, Jefferies Group LLC, J.P. Morgan, KPMG, Marvell, MediaTek, Mentor Graphics, Micron, Microsemi, Model N, Morgan Stanley, Needham & Co., NVIDIA, Open-Silicon, QUALCOMM, QuickLogic, Rambus, RFMD, Samsung, SanDisk, Silicon Labs, SMIC, Synopsys, UMC, VeriSilicon and Wells Fargo. To make reservations to attend the Awards Dinner, please visit the reservations page.
IBM and GLOBALFOUNDRIES today announced that GLOBALFOUNDRIES will acquire IBM’s global commercial semiconductor technology business, including IBM’s intellectual property, technologists and technologies.
IBM will pay GLOBALFOUNDRIES $1.5 billion in cash over the next three years to take the chip operations off its hands. The cash consideration will be adjusted by the amount of working capital which is estimated to be $200 million.
Workers prep Global Foundries’ newest semiconductor factory, “Fab 8” in Saratoga County, New York State. Source: IBM
GLOBALFOUNDRIES will also become IBM’s exclusive server processor semiconductor technology provider for 22nm, 14nm and 10nm semiconductors for the next 10 years.
It its official statement, IBM said the agreement will enable the company to further focus on fundamental semiconductor research and the development of future cloud, mobile, big data analytics, and secure transaction-optimized systems. IBM will continue its previously announced $3 billion investment over five years for semiconductor technology research to lead in the next generation of computing. GLOBALFOUNDRIES will have primary access to the research that results from this investment through joint collaboration at the Colleges of Nanoscale Science and Engineering (CNSE), SUNY Polytechnic Institute, in Albany, N.Y.
Through the acquisition, GLOBALFOUNDRIES will gain substantial intellectual property including thousands of patents, making GLOBALFOUNDRIES the holder of one of the largest semiconductor patent portfolios in the world.
GLOBALFOUNDRIES will acquire and operate existing IBM semiconductor manufacturing operations and facilities in East Fishkill, New York and Essex Junction, Vermont, adding capacity to serve its customers and thousands of jobs to GLOBALFOUNDRIES’ workforce. GLOBALFOUNDRIES plans to provide employment opportunities for substantially all IBM employees at the two facilities who are part of the transferred businesses, except for a team of semiconductor server group employees who will remain with IBM. After the close of this transaction, GLOBALFOUNDRIES will be the largest semiconductor technology manufacturing employer in the Northeast.
GLOBALFOUNDRIES will also acquire IBM’s commercial microelectronics business, which includes ASIC and specialty foundry, manufacturing and related operations and sales. GLOBALFOUNDRIES plans to invest to grow these businesses.
IBM took a related pre-tax charge of $4.7 billion in its third quarter. It also reported a 4 percent drop in revenue on Monday.
What the analysts are saying
In terms of its 14nm FinFET collaboration with Samsung, the acquisition and the sudden influx of top talent from IBM will certainly help get GLOBALFOUNDRIES up to speed, Robert Maire of Semiconductor Advisors LLC reported.
“Even though Samsung still holds the keys and most of the cards in their relationship, the addition of the IBM horsepower does help even things a little bit even though IBM hasn’t been a serious player in the semiconductor business for quite a while it still has a deep well of expertise,” said Mr. Maire.
Currently, analysts at Summit Research Partners are not concerned about the long-term financial impact of the acquisition.
“We think that at present, when the transfer of IBM’s chip manufacturing assets to GLOBALFOUNDRIES is done, this is a non-event to the semiconductor industry for the most part,” said Srini Sundararajan, Semiconductor, Semi-cap Equipment Analyst at Summit Research Partners. “That is sad considering that there were times in the 90s that IBM and Intel competed with one another over bragging rights for technological advancements.”
“In terms of potential impact to semiconductor equipment companies, there would likely be minimal to no impact as potential capex spend would be absorbed within the capex spend of Global Foundries,” Mr. Sundararajan concluded.
By Bettina Weiss, VP, Business Development, SEMI
The 2nd annual SEMI Vietnam Semiconductor Strategy Summit, co-organized with the Saigon Hi-Tech Park and with FabMax as the premier sponsor, was held September 16-17, 2014 in Ho Chi Minh City. This year’s conference drew over 160 attendees from Vietnam, Europe, U.S. and other Southeast Asian countries for a full day of presentations, panel discussions, networking opportunities and interactions with government, the Ho Chi Minh City Semiconductor Industry Association (HSIA) and the Saigon Hi-Tech Park (SHTP).
Building on the success of the inaugural Summit in September of 2013, attendees and speakers commented on the sense of progress and growing vitality of the emerging semiconductor manufacturing ecosystem in Vietnam. In his welcome remarks, Kai Fai Ng, president, SEMI Southeast Asia spoke to the importance of Vietnam in Southeast Asia, and SEMI’s plans to facilitate business interactions between Vietnamese and Southeast Asian companies, support efforts in workforce development and education, and continue to strengthen the relationship with key stakeholders in the country.
Of particular interest to the audience was the keynote presentation by Dr. Pham Ba Tuan, senior expert at CNS, the company tasked with executing the 200mm fab project in Saigon Hi-Tech Park that was announced last year. Tuan stressed the importance of domestically manufactured devices to satisfy a rapidly growing need in Vietnam thanks to the country’s young population and high university graduation rates. Tuan indicated that, depending on the product choice and the cost structure of the new wafer fab, at least 5,000 wafer starts per months would be needed. Fab capacity would be a function of product mix, so wafer starts need to be adjustable from 5,000 to 10,000 wafer starts per month. This would necessitate an investment of “a few million USD” to enable equipment purchases, fab construction and infrastructure readiness.
Source: Saigon Industry Corporation (CNS)
Tuan emphasized the fact that the choice of technology was a crucial factor for the wafer fab, since it influences investment volume, product portfolio, as well as the ability to develop a skilled workforce throughout the manufacturing process. The choice for the wafer fab in Saigon Hi-Tech Park is 180nm on 200mm wafers, a node and substrate size choice that will enable the production of a wide variety of products. According to CNS, revenue from all products made in technologies down to 180nm already account for US$1 billion.
The project timeline presented at the SEMI conference shows construction to begin in Q3 2015 and equipment move-in starting in Q2 2016.
The CNS presentation was followed by a brief company introduction to NXP delivered by Mr. Frederic Vincentini.
Kicking of the second session on Semiconductor Manufacturing in Vietnam, Ms. Sherry Boger, general manager, Intel Vietnam, provided an update on Intel’s plans to extend the production of flagship products to Vietnam — such as the Haswell microprocessor, which was recently announced. Intel’s Vietnam facility is the largest assembly and test facility in the global Intel network, employing over 3,000 Vietnamese employees when fully ramped.
Fab-Finder’s Todd Curtis shared his company’s learning experiences when they started doing business in Vietnam. He stated that the Fab-Finder management team brought over 100 years of semiconductor experience to the table — but 0 years in this country, making it imperative to rapidly get up to speed with respect to laws and taxes, cultural differences and sensitivities and different business practices. Mr. Curtis made a point of thanking his Vietnamese business partners, legal and tax advisors, HSIA and the Saigon Hi-Tech Park for the education they provided.
Prof. Cor Claeys of Imec presented Imec’s Open Innovation Model. Given the ever shrinking features, the complexity of new devices and applications and the rising cost in R&D, Claeys stressed the need for collaborative efforts in the semiconductor industry in order to keep up with the increasing need and speed of innovation.
Open Innovation
Source: Samsung
Contrasting Imec’s Open Innovation model with the traditional R&D approach – where most of the R&D is done in-house, no IP is shared and projects occur in silos –Claeys emphasized the need to share risk, cost, talent and IP among R&D partners in order to jointly reap the benefits of an accelerated, cost-effective RD activity.
This discussion provided a nice introduction into two presentations in the afternoon addressing technology transfers, IP creation and protection. Ms. Radhika Snirivasan, Ph.D., from IBM talked about the process by which technology transfers occur, and how opportunities and risks can be managed. Snirivasan described technology transfers as “quintessential” to any technology installation and shared IBM’s methodology, from preparation and training through installation and debug, qualification and yield learning to product qualification and ramp. She pointed to the added value when IP transfers are managed in highly customizable and flexible scenarios, providing protection and safeguards against risks such as the transfer infrastructure, adequacy of documentation and lack of technology readiness/maturity.
Dr. John Schmitz of NXP elaborated on the subject by presenting NXP’s view on the growing importance of Intellectual Property Rights (IPRs) since knowledge has become a critical driver in the economy. “IPRs are the economical manifestation of technical and business knowledge,” said Schmitz, stressing that IPRs provide a mechanism of protection against misuse. Speaking to current and future patent portfolios, he stated the requirement for future patents to be aligned with the overall company strategy, but stressed the inherent risk of having to look at least 5 years ahead — a mandate he contrasted with the product lifecycle of mobile phones, which is currently about 6 months.
The last formal presentation of the day was M+W Group’s “Integrated Approach for Semiconductor Wafer Fab Implementation,” presented by Mr. Andreas Authenrieth, M+W Group. His presentation focused on the prerequisites for a sustainable and cost-effective fab design, with particular emphasis on energy efficiency, environmental technology and the use of renewable energy. Authenrieth also included the use of secondary equipment in his presentation, explaining the importance of correlating tool specifications with technology requirements, paying close attention to consumables and spares and managing equipment testing and documentation. These considerations could be of particular importance for the CNS wafer fab project.
The 2nd annual SEMI Vietnam Semiconductor Strategy Summit concluded with two panel discussions: The first panel – investing and operating in the technology sector in Vietnam – was moderated by Eduard Hoeberichts, FabMax and included two presentations which addressed both the side of the operator and the side of the government. Johnny Choo of ON Semiconductor shared the experience as an operator of two back-end facilities in Vietnam and highlighted the very positive experience over the last several years as well as some of the areas for potential improvement.
This perspective was consistent with the observations that Sherry Boger of Intel made in the morning presentation. Dr. Le Hoai Quoc as president of Saigon High Tech Park presented the capabilities of the High Tech Park as well as the general government support in various areas for operators and new investors in Vietnam. The “two sides of the coin” perspective led to a lively discussion at the end of the panel session.
The second panel – Education and Workforce Development – was moderated by Ms. Bettina Weiss, SEMI, and included: Ms. Sherry Boger, Intel Vietnam; Dr. Carel von der Poel, Technical University Delft; Dr. Pham Ba Tuan, CNS; and Cao Nguyen, ON Semiconductor. The importance of developing a skilled talent pool in Vietnam was also a prominent topic in SEMI’s 2013 Vietnam Semiconductor Strategy Summit. Panelists engaged in a lively debate about the need to do more for women in high tech, partnerships with international universities and special programs like HEEAP (Higher Engineering Education Alliance Program) which Intel is very actively supporting, as well as the Technical University Delft/DIMES Center, which has been engaged with Vietnam’s Hanoi University of Technology, Hanoi University of Civil Engineering and the Ministry of Science and Technology in various programs. According to Dr. van der Poel, it would be fairly easy to extend these programs to the semiconductor space, as Vietnam starts focusing on workforce readiness in this sector.
At the networking reception, attendees and speakers alike commented on the sense of progress and excitement over the last 12 months. Local attendees in particular appreciated the rich presentations and perspectives from the conference speakers, and international companies, including our sponsors, left with a lot of new contacts and business opportunities in country — and the sense that Vietnam is very serious about becoming a stakeholder in the global semiconductor market.
SEMI is grateful for the support of the sponsoring companies who helped make this year’s Summit possible: FabMax, CNS, M+W Group, Advantest, Fab-Finder, GES, Lam Research, NXP, QAM, and Surplus Global.
The development of increasingly sophisticated and energy-efficient CMOS technology for mobile, client and cloud computing depends on a continuing stream of advances in the process technologies with which the complex integrated circuits are built. Among the most promising chip technologies are transistors called FinFETs, which have attracted significant R&D investment and have begun to appear in commercial products.
But the technology is complex and the path forward isn’t settled, and in two late-news papers to be given at this December’s IEEE International Electron Devices Meeting (IEDM), Intel and IBM will present dueling approaches to the development of FinFET technology for the 14nm technology node, the semiconductor industry’s next big hurdle.
The IEDM is the forum where top technical experts in micro- and nanoelectronics gather to disclose, discuss and debate breakthrough technologies in the field. The 60th annual IEDM will be held at the Hilton San Francisco Union Square Hotel from December 15-17, 2014, preceded by day-long short courses on Sunday, Dec. 14 and a program of 90-minute tutorials on Saturday, Dec. 13.
All modern transistors have a channel to conduct electricity and one or more gates to turn the current on and off. FinFETs have long, thin fin-like channels (hence the name) surrounded by multiple gates. This design leads to greater performance and enhanced energy efficiency. Both Intel and IBM will present fully integrated 14nm FinFET technologies at the IEDM.
Intel, which began using FinFET transistors commercially in its “Ivy Bridge” and “Haswell” processors at the 22nm node, will detail the second generation of that technology.[i] Made on a standard bulk silicon substrate, the new “Broadwell” 14nm technology has been released commercially and is in production as part of Intel’s latest family of microprocessors.
Among the technical features Intel will discuss at the IEDM are: a novel doping technique to prevent current leakage under the fins and to maintain very low doped fins, resulting in improvement in variation; two levels of air-gap-insulated interconnects (electrical connections) at ultra-narrow 80 and 160nm minimum pitches, yielding a 17% reduction in capacitance delays; eight layers of 52nm pitch interconnects embedded in low-k dielectrics; an embedded 140Mb SRAM memory with a tiny cell size of 0.0588µm2; and saturated drive currents significantly higher than for Intel’s 22nm first-generation FinFETs (improvements of 15% and 41% for NMOS and PMOS transistors, respectively). The transistors operate with a supply voltage of only 0.7 Volts.
The researchers also will discuss how aggressive design rules enabled the production of very high aspect ratio rectangular fins (8nm wide and 42nm high) at unprecedented levels of uniformity.
IBM, meanwhile, will describe a very different approach to 14nm FinFET transistors.[ii] The IBM devices are made not from a standard bulk silicon substrate but from an insulating substrate known as SOI, a more expensive material but one which simplifies manufacturing in terms of device isolation. These devices are more than 35% faster than IBM’s 22nm planar (i.e. standard, non-FinFET) transistors, with an operating voltage of just 0.8 volts.
The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. IBM also designed an elegant way to make the technology suitable for both low-power and high-speed applications, using a unique dual-workfunction process that optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel.
Because the technology is envisioned for use in system-on-a-chip (SoC) applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom that ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.
Making transistors smaller, or scaling them according to Moore’s Law, is what has traditionally driven exponential progress in nanoelectronics and information technology. With today’s nanoscale-sized devices that has become difficult and expensive, which is why new transistor architectures such as FinFETs have become so appealing.
[i] Paper #3.7, “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588µm2 SRAM Cell Size,” S. Natarajan et al, Intel
[ii] Paper #3.8, “High Performance 14nm SOI FinFET CMOS Technology with 0.0174µm2 Embedded DRAM and 15 Levels of Cu Metallization,” C.-H. Lin et al, IBM
India has a very large industry base of electronics items, but there is little manufacturing base for semiconductors. As of now India doesn’t have any operational wafer fabrication plants and depends extensively on the imports. Semiconductor industry is 100 percent import based with India importing semiconductors worth $10 billion in 2013. Since In 2013, India spent $169 billion on oil imports, $54 billion on gold imports and $31.5 billion on electronic imports.
Semiconductors are used extensively in various applications, which offer immense potential for the growth of this industry in India. Semiconductors are used majorly in Mobile Devices, Telecommunications, Information Technology & Office Automation (IT & OA), Industrial, Automotive and other industries (Aerospace, Defense and Medical industries).
The latest research report by NOVONOUS finds that the semiconductor industry is estimated to grow from $10.02 billion in 2013 to $52.58 billion in 2020 at CAGR of 26.72 percent.
According to this research report, mobile devices are expected to grow at CAGR of 33.4 percent from 2013 to 2020. The contribution to semiconductor revenue is expected to grow from 35.4 percent in 2013 to 50.7 percent in 2020.
Telecommunication segment is expected to grow at CAGR of 26.8 percent from 2013 to 2020 and its contribution to total revenue will remain the same at 19.7 percent in 2020.
IT&OA contribution to the total semiconductor revenue will come down from 28.3 percent in 2013 to 17.4 percent in 2020 due to consolidation in this sector. This segment will grow at CAGR of 18.2 percent over the next seven years.
Consumer electronics segment is expected to grow at CAGR of 18.8 percent and the contribution to the total semiconductor revenue will come down from the current level of 5.6 percent in 2013 to 3.5 percent in 2020. Industrial electronics segment is expected to grow at CAGR of 19.6 percent and the contribution to the total semiconductor revenue will come down from current level of 4 percent to 2.7 percent.
Automotive electronics segment is expected to grow faster at CAGR of 30.5 percent from 2013 to 2020; its revenue contribution will increase from 3.2 percent in 2013 to 3.9 percent in 2020.
The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced that John P. Daane, President, CEO, and Chairman of the Board of Altera, has been named the 2014 recipient of SIA’s highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the U.S. semiconductor industry in technology or public policy. Daane will accept the award at SIA’s annual award dinner on Thursday, Nov. 13.
“For many years, John Daane has been one of the semiconductor industry’s strongest and most influential leaders,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “John represents the heart and soul of our industry and the glue that has strengthened our association. Throughout his career, John has brought together our industry’s leaders to tackle challenges and advance core industry priorities. His leadership has helped the semiconductor industry create jobs, boost economic growth, and maintain America’s global technology leadership. On behalf of the SIA board of directors, it is a privilege to announce John’s selection as the 2014 Robert N. Noyce Award recipient in recognition of his outstanding accomplishments.”
Daane has served as Altera’s president and CEO since November 2000 and was named chairman of the board in May 2003. Prior to joining Altera, Daane spent 15 years at LSI Logic, a semiconductor manufacturer, most recently as executive vice president, communications products group. Daane earned a Bachelor’s Degree from the University of California, Berkeley.
“I am honored and humbled to be selected by my friends and colleagues to receive this award and to join the company of previous Noyce recipients, individuals who are recognized as some of the semiconductor industry’s greatest pioneers and champions,” said Daane. “Perhaps our industry’s greatest strength is our ability to continuously and relentlessly look forward – to the next great achievement or innovation. It is in that spirit that I gratefully accept this award and look forward to helping build an even stronger semiconductor industry.”
The Noyce Award is named in honor of semiconductor industry pioneer Robert N. Noyce, co-founder of Fairchild Semiconductor and Intel.
Boston Semi Equipment LLC (BSE) today announced it has combined all of its automated test equipment (ATE) businesses under the Boston Semi Equipment brand name. Effective immediately, the Test Advantage Hardware and MVTS Technologies businesses will operate using the Boston Semi Equipment name. This follows the company’s announcement in July that it was integrating all sales and service for ATE, Prober and Test Handler products into the Boston Semi Equipment field sales organization.
Boston Semi Equipment has now built an organization of tester, handler and prober integration specialists to address the semiconductor industry’s need for a vendor-independent test cell solution provider. BSE can provide equipment configured to the customer’s exact requirements, deliver a complete test cell solution across all tester platforms fully utilizing the original OEM technology, and provide service and support to keep ATE at peak performance.
“We believe we have created the largest ATE-focused organization outside of the OEMs,” stated Bryan Banish, CEO of Boston Semi Equipment. “Our ATE organizations have been delivering standard ATE configurations, test services, custom equipment solutions, and service and support programs for our semiconductor ATE customers since 1994. Because we have experience on all major current generation and legacy ATE models, we can support any and all ATE-related projects to meet our customers’ test needs.”
BSE acquired Test Advantage Hardware in 2010 and has steadily expanded the company’s capabilities in current-generation ATE platforms. In June, 2014 the company also acquired MVTS Technologies (MVTS), which has extensive experience extending the life of legacy ATE, maximizing the investment of semiconductor companies in their test assets. The combined capabilities provide Boston Semi Equipment customers with an alternate source for high quality and economical ATE equipment, service, and test cell solutions.
Boston Semi Equipment LLC is a semiconductor equipment company that has established a reputation as a reliable source for affordable back end test equipment, fab tools and service solutions for semiconductor manufacturers and OSATs worldwide.
SEMATECH, the global consortium of chipmakers, announced today that Kurita Water Industries Limited has partnered with SEMATECH to develop innovative technologies for low defectivity ultrapure water (UPW) applications used in semiconductor manufacturing.
“SEMATECH, along with suppliers, is working to improve preparation and cleaning techniques by both optimizing existing technologies, testing novel methods and developing new characterization technologies that will address current and projected challenges in semiconductor and wafer manufacturing processes,” said Kevin Cummings, SEMATECH’s Director of Lithography. “The collaborative effort between SEMATECH and Kurita illustrates the demand for next-generation ultrapure water systems in the semiconductor industry.”
As a SEMATECH member, Kurita will collaborate with metrology, process and manufacturing experts at SEMATECH to identify and develop UPW defect removal techniques that will improve capabilities for key process applications in semiconductor manufacturing.
“Ultrapure water plays a critical role in manufacturing today’s extremely compact semiconductor chips and, as such, SEMATECH continues to expand our expertise and capabilities in liquid-phase defectivity, including ultrapure water, chemicals and resists,” said Edward Barth, SEMATECH’s Director of Strategic Growth Initiatives. “SEMATECH will leverage Kurita’s unique ultrapure water technology to investigate methods for improving lifecycle costs and increasing efficiency of critical manufacturing process applications and equipment components.”
Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs). Copper pillar bumps are a critical component of many advanced packaging technologies and TSVs provide a means for signals to pass through multiple vertically stacked chips in three dimensional integrated circuits (3DIC). The new SONUS Technology is non-contact and non-destructive, and is designed to provide faster, less costly measurements and greater sensitivity to smaller defects than existing alternatives such as X-ray tomography and acoustic microscopy.
“SONUS Technology meets a critical need for measuring and inspecting the structures used to connect chips to each other and to the outside world,” said Tim Kryman, Rudolph’s director of metrology product management. “Copper pillar bumps and TSVs are critical interconnect technologies enabling 2.5D and 3D packaging. The mechanical integrity of the interconnect and final device performance are directly dependent on tight control of the plating processes used to create copper pillar bumps. Likewise, the quality of the TSV fill is critical to the electrical performance of stacked devices. This new technology allows us to measure individual films and film stacks with thicknesses up to 100µm, and detect voids as small as 0.5µm in TSVs with aspect ratios of 10:1 or greater.”
Kryman added, “SONUS Technology builds on the expertise we developed in acoustic metrology for our industry-standard MetaPULSE systems, which are widely used for front-end metal film metrology. By offering similar improvements in yield and time-to-profitability in high volume manufacturing (HVM), SONUS offers a compelling value proposition to advanced packaging customers.”
Both MetaPULSE and SONUS systems use a laser to initiate an acoustic disturbance at the surface of the sample. As the acoustic wave travels down through the film stack, it is partially reflected at interfaces between different materials. Although the detection schemes are different, the reflected waves are detected when they return to the surface and the elapsed time is used to calculate the thickness of each layer. In the case of SONUS Technology, two lasers are used. The first laser excites the sample and the second probes for the returning acoustics. This decouples excitation and detection allowing SONUS to continuously probe the sample resulting in a much larger film thickness range. So, where MetaPULSE can measure metal films and stacks to ~10 microns, SONUS can measure films in excess of 100 microns. In addition, SONUS Technology’s use of interferometry to characterize the surface displacement provides a rich data set that can be analyzed to not only characterize film thickness, but perform defect detection.
The primary alternatives for such measurements are X-ray based tomographic analysis and acoustic microscopy. SONUS Technology’s ability to detect voids as small as half a micrometer is approximately twice as good as current X-ray techniques, which have a spatial resolution of about 1 micrometer. Acoustic microscopy can make similar measurements, but the sample must be immersed in water, which, though not strictly destructive, does effectively preclude the return of the sample to production. SONUS is both non-contact and non-destructive and is designed for R&D and high-volume manufacturing.
In the run up to the product introduction, Rudolph worked closely with TEL NEXX to develop SONUS-based process control for pillar bump and TSV plating processes. Arthur Keigler, chief technology officer of TEL NEXX, said, “We are attracted by the opportunity SONUS Technology offers our mutual customers in the advanced packaging market. The ability to measure multi-metal film stacks for Cu pillar, and then continue to use the same tool for TSV void detection offers immediate productivity and cost benefits to manufacturing and development groups alike.”
While Rudolph is initially focused on using the technology for copper pillar bump process metrology and TSV inspection, they are also investigating other applications, ranging from detecting film delamination to metrology and process control for MEMS fabrication processes.