Category Archives: Metrology

Sanjay Mehrotra, President and CEO, Micron Technology, 2019 SIA Chair

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced the SIA Board of Directors has elected Sanjay Mehrotra, President and CEO of Micron Technology, Inc. (NASDAQ: MU), as its 2019 Chair and Keith Jackson, President, CEO, and Director of ON Semiconductor (NASDAQ: ON), as its 2019 Vice Chair.

“It is a great pleasure to welcome Sanjay Mehrotra as SIA’s 2019 Chair and Keith Jackson as SIA’s Vice Chair,” said John Neuffer, SIA President and CEO. “A design engineer by trade, Sanjay is a highly accomplished industry veteran and a leading voice on semiconductor technology. With more than 30 years of experience, Keith is a mainstay in our industry and a devoted champion for semiconductor priorities. Their combined skills and experience will be a tremendous asset to SIA as we pursue our industry’s interests in Washington and around the world.”

A 39-year veteran of the semiconductor industry, Mehrotra joined Micron in May 2017 after a long and distinguished career at SanDisk Corporation, where he led the company from a start-up in 1988 until its eventual sale in 2016. In addition to being a SanDisk co-founder, Mehrotra served as its President and CEO from 2011 to 2016, overseeing its growth to an industry-leading Fortune 500 company.

Prior to SanDisk, Mehrotra held design engineering positions at Integrated Device Technology, Inc., SEEQ Technology, and Intel Corporation. Mehrotra earned both bachelor’s and master’s degrees in electrical engineering and computer science from the University of California, Berkeley. He holds more than 70 patents and has published articles in the areas of non-volatile memory design and flash memory systems.

“The semiconductor industry is leading the greatest period of technological advancement in human history, making the seemingly impossible possible and opening up tremendous opportunities for economic growth,” said Mehrotra. “Driving innovation requires our industry to speak with one voice and promote policies that support our industry vision, and I look forward to helping lead that effort as 2019 SIA Chair.”

Jackson began serving as President, CEO, and Director of ON Semiconductor in November 2002. Before joining ON Semiconductor, he was with Fairchild, serving as Executive Vice President and General Manager, Analog, Mixed Signal, and Configurable Products Groups, and was head of its Integrated Circuits Group.

Previously, Jackson served as President and a Member of the Board of Directors of Tritech Microelectronics in Singapore and worked for National Semiconductor Corporation, most recently as Vice President and General Manager of the Analog and Mixed Signal division. He also held various positions at Texas Instruments Incorporated, including engineering and management positions, from 1973 to 1986. Mr. Jackson earned his bachelor’s and master’s degrees from Southern Methodist University.

“It is an honor to serve as 2019 SIA Vice Chair,” Jackson said. “Many issues of great importance to the semiconductor industry are being debated in Washington and around the world. We look forward to promoting policies that advance semiconductor technology and move our industry forward.”

 

By David W. Price, Jay Rathert and Douglas G. Sutherland

Author’s Note:The Process Watch series explores key concepts about process control—defect inspection, metrology and data analytics—for the semiconductor industry. This article is the fourth in a series on process control strategies for automotive semiconductor devices.

The first three articles1-3 in this series discussed methods that automotive semiconductor manufacturers can use to better meet the challenging quality requirements of their customers. The first paper addressed the impact of automotive IC reliability failures and the idea that combating them requires a “Zero Defect” mentality. The second paper discussed continuous improvement programs and strategies that automotive fabs implement to reduce the process defects that can become chip reliability problems. The third paper focused on the additional process control sensitivity requirements needed to capture potential latent (reliability) defects. This installment discusses excursion monitoring strategies across the entire automotive fab process so that non-conforming material can be quickly found and partitioned.

Semiconductor fabs that make automotive ICs typically offer automotive service packages (ASPs). These ASPs provide differentiated process flows – with elements such as more process control and process monitoring, or guaranteed use of golden process tools. The goal of ASPs is to help ensure that the chips produced meet the stringent reliability requirements of the automotive industry.

But even with the use of an automotive service package, excursions are inevitable, as they are with any controlled process. Recognizing this, automotive semiconductor fabs pay special attention to creating a comprehensive control plan for their critical process layers as part of their Process Failure Mode and Effects Analysis (PFMEA). The control plan details the process steps to be monitored and how they are monitored – specifying details such as the inspection sensitivity, sampling frequency and the exact process control systems to be used. A well-designed control plan will detect all excursions and keep “maverick” wafers from escaping the fab due to undersampling. Additionally, it will clearly indicate which wafers are affected by each excursion so that they can be quarantined and more fully dispositioned – thereby ensuring that non-conforming devices will not inadvertently ship.

To meet these objectives, the control plan of an automotive service package will invariably require much more extensive inspection and metrology coverage than the control plan for production of ICs for consumer products. An analysis of process control benchmarking data from fabs running both automotive and non-automotive products at the same design rule have shown that the fabs implement more defect inspection steps and more types of process control (inspection and metrology) for the automotive products. The data reveals that on average:

  • Automotive flows use approximately 1.5 to 2 times more defect inspection steps
  • Automotive flows employ more frequent sampling, both as a percentage of lots and number of wafers per lot
  • Automotive flows use additional sensitivity to capture the smaller defects that may affect reliability

The combined impact of these factors results in the typical automotive fab requiring 50% more process control capacity than their consumer product peers. A closer look reveals exactly how this capacity is deployed.

Figure 1 below shows an example of the number of lots between inspection points for both an automotive and a non-automotive process flow in the same fab. As a result of the increased number of inspection steps, if there is a defect excursion, it will be found much more quickly in the automotive flow. Finding the excursion sooner limits the lots at risk: a smaller and more clearly defined population of lots are exposed to the higher defect count, thereby helping serve the automotive traceability requirement. These excursion lots are then quarantined for high-sensitivity inspection of 100% of the wafers to disposition them for release, scrap, or when applicable, a downgrade to a non-automotive application.

Figure 1. Example demonstrating the lots at risk between inspection points for an automotive process flow (blue) and a non-automotive (baseline) process blow (pink). The automotive process flow has many more inspection points in the FEOL and therefore fewer lots at risk when a defect excursion does occur.

The additional inspection points in the automotive service package have the added benefit of simplifying the search for the root cause of the excursion by reducing the range of potential sources. Fewer potential sources helps speed effective 8D investigations4 to find and fix the problem. Counterintuitively, the increased number of inspection points also tends to reduce production cycle time due to reduced variability in the line.5

While increasing inspection capacity helps monitor and contain process excursions, there remains risk to automotive IC quality. Because each wafer may take a unique path through the multitude of processing chambers available in the fab, the sum of minor variations and marginalities across hundreds of process steps can create “maverick” wafers. These wafers can easily slip through a control plan that relies heavily on sub-sampling, allowing at-risk die into the supply chain. To address this issue, many automotive fabs are adding high-speed macro defect inspection tools to their fleet to scan more wafers per lot. This significantly improves the probability of catching maverick wafers and preventing them from entering the automotive supply chain.

Newer generation macro defect inspection tools6 can combine the sensitivity and defect capture of many older generation brightfield and darkfield wafer defect inspection tools into a single platform that can operate at nearly 150 wafers per hour, keeping cost of ownership low. In larger design rule 200mm fabs, the additional capacity often reveals multiple low-level excursions that had previously gone undetected, as shown in Figure 2.

Figure 2. The legacy sample plan of 5 wafers per lot (yellow circles) would have allowed the single maverick wafer excursion (red square) to go undetected. High capacity macro defect inspection tools can stop escapes by reducing undersampling and the associated risks.

In advanced, smaller design rule fabs, macro defect inspection tools lack the needed sensitivity to replace the traditional line monitoring and patterned wafer excursion monitoring roles occupied by broadband plasma and laser scanning wafer defect inspection tools. However, their high capacity has found an important role in augmenting the existing sample plan to find wafer-level signatures that indicate a maverick wafer.

A recent development in automotive control strategies is the use of defect inspection for die-level screening. One such technique, known as Inline Defect Part Average Testing (I-PAT™), uses outlier detection techniques to further enhance the fab’s ability to recognize die that may pass electrical test but become reliability failures later due to latent defects. This method will be discussed in detail in the next installment of this series.

About the authors:

Dr. David W. Price and Jay Rathert are Senior Directors at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 15 years, they have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall process control strategy for a variety of specific markets, including implementation of strategies for automotive reliability, legacy fab cost and risk optimization, and advanced design rule time-to-market. The Process Watch series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

  1. Price, Sutherland and Rathert, “Process Watch: The (Automotive) Problem With Semiconductors,” Solid State Technology, January 2018.
  2. Price, Sutherland and Rathert, “Process Watch: Baseline Yield Predicts Baseline Reliability,” Solid State Technology, March 2018.
  3. Price, Sutherland, Rathert, McCormack and Saville, “Process Watch: Automotive Defect Sensitivity Requirements,” Solid State Technology, August 2018.
  4. 8D investigations involve a systematic approach to solving problems. https://en.wikipedia.org/wiki/Eight_disciplines_problem_solving
  5. Sutherland and Price, “Process Watch: Process Control and Production Cycle Time,” Solid State Technology, June 2016.
  6. For example, see: https://www.kla-tencor.com/products/chip-manufacturing/defect-inspection-review.html#product-8-series

 

IC Insights revised its outlook for total semiconductor industry capital spending and presented its forecast of semiconductor capex spending for individual companies in its November Update to The McClean Report 2018, which was released earlier this month.

Samsung is expected to have the largest capex budget of any IC supplier again in 2018.  After spending $24.2 billion for semiconductor capex in 2017, IC Insights forecasts that Samsung’s spending will edge slightly downward, but remain at a very strong level of $22.6 billion in 2018 (Figure 1).  If it comes in at this amount, Samsung’s two-year semiconductor capital spending will be an astounding $46.8 billion.

Figure 1

As seen in Figure 1, Samsung’s semiconductor capital outlays from 2010, the first year the company spent more than $10 billion in semiconductor capex, through 2016 averaged $12.0 billion per year. However, after spending $11.3 billion in 2016, the company more than doubled its 2017 capex budget. The fact that Samsung’s continued its strong capex spending in 2018 is just as impressive.

IC Insights believes that Samsung’s massive spending outlays in 2017 and 2018 will have repercussions far into the future.  One effect that has already begun is a period of overcapacity in the 3D NAND flash market.  This overcapacity situation is due not only to Samsung’s huge spending for 3D NAND flash, but also from spending by competitors (e.g., SK Hynix, Micron, Toshiba, Intel, etc.) that attempt to keep pace in this market segment.

With the DRAM and NAND flash memory markets showing strong growth through the first three quarters of 2018, SK Hynix ramped up its capital spending this year.  In 1Q18, SK Hynix said that it intended to increase its capex spending by “at least 30%” this year. In the November Update, IC Insights forecasts that SK Hynix will see a 58% surge in its semi capex spending.  The increased spending by SK Hynix this year is focused primarily on bringing new capacity online at two of its large memory fabs—M15, a 3D NAND flash fab in Cheongju, South Korea, and the expansion of its huge DRAM fab in Wuxi, China. The Cheongju fab is being pushed to open before the end of this year.  The Wuxi fab is also targeted to open by the end of this year, a few months earlier than its original start date of early 2019.

Overall, IC Insights’ now forecasts total semiconductor industry capital spending will climb 15% to $107.1 billion this year, the first time that annual industry capex is expected to top $100.0 billion. Following the industry-wide growth this year, semiconductor capex is expected to decline 12% in 2019 (Figure 2).

Figure 2

Given that the current softness in the memory market is expected to extend into at least the first half of next year, the combined capital spending by the three largest memory suppliers—Samsung, SK Hynix, and Micron—is forecast to drop from $45.4 billion in 2018 to $37.5 billion in 2019, a decline of 17%.

In total, the top five spenders, which are expected to represent 66% of total outlays this year, are forecast to cut their capital spending by 14% in 2019 with the remaining semiconductor industry companies registering a 7% decline.

GLOBALFOUNDRIES today announced its advanced silicon germanium (SiGe) offering, 9HP, is now available for prototyping on the company’s 300mm wafer manufacturing platform. The move signifies the strong growth in data center and high-speed wired/wireless applications that can leverage the scale advantages of a 300mm manufacturing footprint. By tapping into GF’s 300mm manufacturing expertise, clients can take advantage of increased production efficiency and reproducibility for high-speed applications such as optical networks, 5G millimeter-wave wireless communications and automotive radar.

GF is the industry leader in the manufacturing of high-performance SiGe solutions on its 200mm production line in Burlington, Vermont. The migration of 9HP, a 90nm SiGe process, to 300mm wafers manufactured at GF’s Fab 10 facility in East Fishkill, N.Y., continues this leadership and establishes a 300mm foothold for further roadmap development, ensuring continued technology performance enhancements and scaling.

“The increasing complexity and performance demands of high-bandwidth communication systems have created the need for higher performance silicon solutions,” said Christine Dunbar, vice president of RF business unit at GF. “GF’s 9HP is specifically designed to provide outstanding performance, and in 300mm manufacturing will support our client’s requirements for high-speed wired and wireless components that will shape future data communications.”

GF’s 9HP extends a rich history of high-performance SiGe BiCMOS technologies designed to support the massive growth in extremely high data rates at microwave and millimeter-wave frequencies for the next generation of wireless networks and communications infrastructure, such asterabit-level optical networks, 5G mmWave and satellite communications (SATCOM) and instrumentation and defense systems. The technology offers superior low-current/high-frequency performance with improved heterojunction bipolar transistor (HBT) performance and up to a 35 percent increase in maximum oscillation frequency (Fmax) to 370GHz compared to its predecessors, SiGe 8XP and 8HP.

Client prototyping of 9HP on 300mm at Fab 10 in East Fishkill, N.Y. on multi-project wafers (MPWs) is underway now, with qualified process and design kits scheduled in 2Q 2019.

SEMI, the global industry association serving the global electronics manufacturing supply chain, today announced the industry’s first worldwide fab data for power and compound semiconductors. The new report, Power and Compound Fab Outlook, provides comprehensive front-end semiconductor fab information and a forecast to 2022 for global manufacturing capabilities of power and compound semiconductors.

Power devices are rising in importance as energy-efficiency standards tighten to meet growing demand for power-thrifty high-end consumer electronics, wireless communications, electric vehicles, green energy, data centers, and both industrial and consumer IoT (Internet of Things) applications. Semiconductor fabs around the globe have responded with improvements to power usage in every aspect of electronics including power harvesting, delivery, transformation, storage, and consumption. Cost structure and performance are critical in power electronics, dictating the pace of market growth and technology adoption.

With compound materials driving significant gains in the energy efficiency of power devices, the Power and Compound Fab Outlook highlights particular compound materials that have been adopted in semiconductor fabs. The report is an essential business tool for anyone interested in related tool and material markets as well as power and compound materials capacity in fabs by region and wafer sizes.

Figure 1

North America-based manufacturers of semiconductor equipment posted $2.06 billion in billings worldwide in October 2018 (three-month average basis), according to the October Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 0.9% percent lower than the final September 2018 level of $2.07 billion, and is 2.0 percent higher than the October 2017 billings level of $2.02 billion.

“October billings of North American equipment suppliers reflect near-term weakening of demand for PC, mobile phones and servers,” said Ajit Manocha, president and CEO of SEMI. “Additionally, memory manufacturers have pulled back investments in response to recent softening of memory pricing.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg.)
Year-Over-Year
May 2018
$2,702.3
19.0%
June 2018
$2,484.3
8.0%
July 2018
$2,377.9
4.8%
August 2018
$2,236.8
2.5%
September 2018 (final)
$2,078.6
1.2%
October 2018 (prelim)
$2,059.1
2.0%

Source: SEMI (www.semi.org), November 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases.

By Jay Chittooran

Meeting Attended by More than 100 Tech Company Representatives

Over the past decade, China has become a central market for the semiconductor industry. China is now home to more than 30 percent of semiconductor end users worldwide. All semiconductor companies, regardless of size, operate in China. The rise of China’s semiconductor market has been enabled by global commerce and a vast network of supply chains that span the globe.

With China now a prominent player in the industry, it has become critically important for semiconductor companies to effectively engage with China. In order to help our member companies better understand the challenges and opportunities and navigate what can be a complex landscape, SEMI hosts annual trade compliance conferences in China for trade professionals. This year, SEMI, with CompTIA and U.S. Information Technology Office (USITO), hosted two global trade seminars in China, one in Shanghai on October 30th and the other in Beijing on November 1st.

Over 120 representatives from more than two dozen technology companies attended the 2018 trade compliance seminars. Over the course of the two sessions, speakers from government, business, and law firms highlighted the most pressing trade issues in China. Speakers included thought leaders, trade practitioners and senior Chinese government officials.

Sessions included a deep dive on China’s draft customs reform law, a panel discussion on U.S. export controls, and a briefing on how best to engage with China Customs and how China’s products are classified. Another well-received session focused on the status of China’s export control law, which has been in the drafting process for years.

However, the overarching question for many attendees was U.S.-China economic relations, which are undergoing a sea change, with the U.S. having imposed or threatened tariffs on all imports from China – totaling more than $500 billion in goods – over the past six months. As a speaker noted during a session on the U.S.-China tensions and the surrounding broader geopolitical impacts, the environment is becoming increasingly complex and volatile. In fact, on the morning of the first session, Fujian Jinhua Integrated Circuit was added to the U.S. Commerce Department’s entity list, which effectively restricts exports to the company.

As a result of the trade actions, ranging from tariffs to enhanced export controls, U.S. semiconductor companies are beginning to increase prices, reduce research and development (R&D) budgets, restructure supply chains and take other mitigation actions that will ultimately slow innovation. Certain export controls and other regulations that prohibit U.S.-companies from conducting business with targeted companies will put the U.S. at a competitive disadvantage.

In fact and as we speak, some companies with China-based operations have cancelled orders from U.S. companies and shifted to suppliers that are not subject to U.S. actions to reduce the associated risks of supply interruption and cost increases. Ultimately, U.S. trade policy could backfire, threatening jobs, curbing growth, cutting U.S. R&D investments and compromising the competitiveness of U.S. firms.

SEMI will begin planning next year’s Global Trade Seminar in the coming months. If you would like to be involved in the planning, or would simply like more information about the seminar, please contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

Sales of automotive electronic systems are forecast to increase 7.0% in 2018 and 6.3% in 2019, the highest growth rate in both years among the six major end-use applications for semiconductors.  Figure 1 shows that sales of automotive-related electronic systems are forecast to increase to $152 billion in 2018 from $142 billion in 2017, and are forecast to rise to $162 billion in 2019.  Furthermore, automotive electronic systems are expected to enjoy a compound annual growth rate (CAGR) of 6.4% from 2017 through 2021, again topping all other major system categories, based on recent findings by IC Insights.

Figure 1

Overall, the automotive segment is expected to account for 9.4% of the $1.62 trillion total worldwide electronic systems market in 2018 (Figure 2), a slight increase from 9.1% in 2017. Automotive has increased only incrementally over the years, and is forecast to show only marginal gains as a percent of the total electronic systems market through 2021, when it is forecast to account for 9.9% of global electronic systems sales.  Though accounting for a rather small percentage of total electronic system marketshare in 2018, (larger only than the government/military category), automotive is expected to be the fastest-growing segment through 2021.

Figure 2

Technology features that are focused on self-driving (autonomous) vehicles, ADAS, vehicle-to-vehicle (V2V) communications, on-board safety, convenience, and environmental features, as well as ongoing interest in electric vehicles, continues to lift the market for automotive electronics systems, despite some highly publicized accidents involving self-driving vehicles this year that were at least partly blamed on technology miscues.

New advancements are more widely available onboard mid range and entry-level cars and as aftermarket products, which has further raised automotive system growth in recent years.  In the semiconductor world, this is particularly good news for makers of analog ICs, MCUs, and sensors since a great number of all of these devices are required in most of these automotive systems. It is worth noting that the Automotive—Special Purpose Logic category is forecast to increase 29% this year—second only to the DRAM market, and the Automotive—Application-Specific Analog market is forecast to jump 14% this year—as backup cameras, blind-spot (lane departure) detectors, and other “intelligent” systems are mandated or otherwise being added to more vehicles.  Meanwhile, memory (specifically, DRAM and flash memory) is increasingly playing a more critical role in the development of new automotive system solutions used in vehicles.

By Emir Demircan

Joining distinguished speakers from the European Commission, industry, academia and Member States, Laith Altimime, SEMI Europe president, will keynote on “European Competitiveness in the Context of the Global Digital Economy” on 20 November at the European Forum for Electronic Components and Systems (EFECS) in Lisbon, Portugal.

Players across the European electronics manufacturing value chain will gather 20-22 November, 2018, at EFECS to share the industry’s vision and set the future direction of technology innovation. Themed “Our Digital Future,” this year’s forum focuses on how rapid innovation in electronics components and systems-based applications are shaping Europe’s digital future. Start-ups, SMEs, research institutes, academia, large and medium enterprises and public authorities will learn about new collaboration initiatives and the latest developments in European funding instruments while offering their expectations for future funding programmes.

Organized by AENEAS, ARTEMIS-IA, EPoSS, ECSEL Joint Undertaking and the European Commission, in association with EUREKA, EFECS will also highlight the impact and results of various European funding instruments.

For more information about the event, please click here.

Emir Demircan senior manager for advocacy and public policy at SEMI Europe. 

Micron Technology, Inc. today announced the company has joined CERN openlab, a unique public-private partnership, by signing a three-year agreement. Under the agreement, Micron will provide CERN with advanced next-generation memory solutions to further machine learning capabilities for high-energy physics experiments at the laboratory. Micron’s memory solutions that combine neural network capabilities will be tested in the data-acquisition systems of experiments at CERN.

High-energy physics scientists are looking to deploy leading-edge technologies that can support their experiments’ computing and data processing requirements. Memory plays a vital role in accelerating intelligence by processing vast amounts of data, helping researchers gain valuable insights from data generated by high-energy physics experiments.

As part of the work with CERN, Micron will develop and introduce a specially designed Micron memory solution that will be tested by researchers at CERN for use in rapidly combing through the vast amount of data generated by experiments. The project will feature FPGA-based boards with Micron’s most advanced high-performance memory combined with an advanced neural network technology developed in collaboration between Micron and FWDNXT, a provider of deep learning and AI solutions.

“Micron is committed to pushing the limits of innovation by providing high-performance memory and storage solutions to solve the world’s greatest computing and data processing challenges in data analytics and machine learning,” said Steve Pawlowski, vice president of advanced computing solutions at Micron Technology. “We’re proud to work with CERN to deliver machine learning capabilities that will enable high-energy physics scientists to make advances in their science and research experiments.”

“CERN collaborates openly with both the public and private sector, and working with technology partners like Micron helps ensure that members of the research community have access to the advanced computing technologies needed to carry out our groundbreaking work,” said Maria Girone, CTO at CERN openlab. “It is critical to the success of the Large Hadron Collider that we are able to examine the petabytes of data generated in a fast and intelligent manner that enables us to unlock new scientific discoveries. These latest-generation memory solutions from Micron and machine learning solutions from FWDNXT offer significant potential in terms of enabling us to process more data at higher speeds.”

Micron will demonstrate its high-performance memory solutions running FWDNXT’s Machine Learning SDK at SC18, November 12-15, in Dallas, Texas.