Category Archives: Metrology

BY BYRON EXARCOS, President, CLASSONE TECHNOLOGY

Historically, the major semiconductor capital equipment manufacturers have focused on supporting the bigger semiconductor companies at the expense of the smaller ones. The last decade’s round of consolidations in the manufacturing and equipment sectors has only exacerbated this trend. This approach may make good business sense for the large equipment companies, but it’s created a serious challenge for smaller IC manufacturers. Even worse, it now threatens to stifle the continuing innovation on which the high tech industry depends.

It’s hard to fault the big equipment players for their business model. It’s much more cost-effective and profitable to dedicate the bulk of your resources to those customers who want to buy multiple process tools featuring “bleeding edge” technology on highly automated, volume production platforms. In many cases, it’s simply not as profitable to engage with smaller customers.

So what choice do the manufacturers have for populating their fabs if they’re running 200mm or smaller wafers? One alternative is to buy refurbished tools, assuming they can find a tool that meets their needs, which is not always easy. Another is to buy a bigger tool with more performance capabilities than they need, which busts their equipment budget. There aren’t many other options.

Now, one could dismiss this issue by simply saying, that’s the way this market works. Continued growth in our industry has always depended on a certain path of continual innovation. “Smaller, faster, cheaper” — producing smaller, more powerful chips in ever greater volume on larger wafers was a highly successful means of turning computers and subsequent mobile computing and communication devices into household items. It’s hard to fault a business/technology model that has been successful for so many years.

On the other hand, every emerging market eventually matures. We’ve all experi- enced the boom-and-bust cycles that roil our industry and what happens when the “last big thing” plateaus or dries up. Today, the capital equipment market is at a cusp. We need to examine whether the traditional smaller-design-rules/bigger-wafers/faster-throughput approach is helping or hindering the introduction of new technologies.

Today’s emerging technologies include devices such as smart sensors, power and RF wireless devices. The fact is, many of these chips can be made quite well and quite profitably using larger design rules on 200mm or even smaller substrates. However, many of the companies developing these devices are not huge enterprises, and they’re hampered by the unavailability of tools delivering the appropriate levels of process technology, automation and throughput — at a price they can afford. Ironically, our industry is in a phase where the equipment companies that once drove significant innovations, such as the introduction of copper deposition and low-k dielectrics, have become so large and narrowly focused that they’re impeding the development of many other emerging technologies.

I have some understanding of the needs of smaller device manufacturers because one of our companies, ClassOne Equipment, has been selling refurbished equipment to them for over a decade. That is why we’ve now created a whole new company, ClassOne Technology, to provide new equipment at substantially lower prices specifically for 200mm and smaller substrates. We are introducing new electroplating systems, spin rinse dryers and spray solvent tools; and some of them are literally half the cost of high-end competitive units. We’re particularly interested in serving all those small- to mid-sized companies who are making MEMS, power devices, RF, LEDs, photonics, sensors, microfluidics and other emerging-technology devices.

However, no single company can solve the entire problem. There is a glaring need for equipment manufacturers to bring the price/performance ratio of their tools back in line with the needs of more of the equipment users, not just those at the bleeding edge. If the tool manufacturers persist in trying to only sell the equivalent of sports cars to customers who just need pickup trucks, America’s high tech industry may soon find itself trailing, rather than leading the innovation curve.

Tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. 

BY SHRINIVAS SHETTY, DAVID M. OWEN and SCOTT ZAFIROPOULO Ultratech, Inc., San Jose, CA 

Control of overlay in multi-layer devices structures has always been important in semiconductor fabrication. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. As devices shrink, the overlay require- ments become more and more stringent (FIGURE 1). The tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. The overlay budget includes contributions from the lithographic scanner, the reticle and the wafer. The wafer represents the largest source of overlay variability during high-volume manufacturing. Therefore, the development of an inspection strategy to control within-wafer and wafer-to-wafer variability may provide the key to meeting the challenges associated with future generations of devices.

Traditional wafer warpage or distortion measurements have typically used point-by-point measurements to generate low-density maps of the wafer geometry with a few hundred data points across the wafer. Depending on the specific technique, a higher density map may be possible at the expense of throughput or limiting the measurement to a small portion of the wafer. The trade-off of point density and throughput has meant that the use of wafer distortion characterization for overlay control has been limited to off-line process development and not to improve yields.

FIGURE 1. As devices shrink, the overlay requirements become more and more stringent.

FIGURE 1. As devices shrink, the overlay requirements become more and more stringent.

The Superfast system based on the Coherent Gradient Sensing (CGS) interferometer uniquely provides high-density front-side pattern wafer maps (>3,000,000 data points) with fast data acquisition (seconds per wafer). The high throughput along with small foot print leads to a low cost of ownership relative to competing technologies.

This article discusses using deformation data from the front-side of a patterned wafer on the Superfast, we are able to understand the relationships between surface displacements, stress and overlay. It also reviews a case study evaluating the role of millisecond annealing parameters on overlay and stress.

Superfast (CGS) technology description

The CGS interferometer is a type of lateral shearing interferometer. The interference is generated in a self-referencing manner using two parallel diffraction gratings. This self-referencing approach eliminates the need for an independent reference beam from, for example, a flat mirror and ensures excellent fringe contrast regardless of the reflectivity of the surface under investigation. This is a key differentiator to accurately measure patterned wafers.

The interferometer essentially compares the relative heights of two points on the surface that are separated by a fixed distance, called the shearing distance. Physically, the change in height over a fixed distance provides slope or tilt information and the fringes in a CGS interference pattern are contours of constant slope. The slope data derived from the interference patterns is integrated numerically to generate the surface shape or topography.

Application to thin film stress measurement

The Superfast inspection system is designed for semiconductor manufacturing based on the CGS interferometer. The Superfast tool features a collimated probe beam of >300mm in diameter that is expanded from a relatively low power HeNe laser. The probe beam illuminates the entire wafer at once and the wafer is supported on three lift pins, which are then subtracted from the final analysis. The beam that reflects off of the wafer surface is distorted in accordance with the local height variations of the wafer. The distorted beam is steered through the two parallel diffraction gratings to generate an interference pattern that is imaged on to a CCD array. As a result, the wafer surface is mapped with high resolution (>3,000,000 data points) with measurement times of seconds.

FIGURE 2. Typical results from the Superfast inspection system, designed for semiconductor manufacturing based on the CGS interferometer.

FIGURE 2. Typical results from the Superfast inspection system, designed for semiconductor manufacturing based on the CGS interferometer.

Data integrity on patterned wafers is further enhanced through the implementation of phase shifting. Phase shifting is achieved by moving the gratings in the direction parallel to the shearing direction. Phase shifting provides several advantages and for the measurement of patterned wafers. The most notable being that fringe contrast in the interference fringes, that modulate with phase shifting can effectively be separated from pattern contrast, which is static with phase shifting. Phase shifting along with the inherent self-referencing nature of the CGS technique results in relatively high measurement integrity on patterned wafers without the need for dedicated or distinct targets, pads or other specialized features in the layout. Typical results are shown in FIGURE 2.

Compared to other techniques, Superfast has several distinct advantages.

  • Front Side Pattern Wafer Measurement: Core CGS 3G technology has been used to measure front-side of pattern wafers for over a decade.
  • High Data Density: Superfast generates high density maps of surface displacements that feature more than 3,000,000 points of data. In this manner, detailed within-die, die-to- die and wafer-to-wafer process variations that lead to overlay errors can be characterized.
  • High Throughput/Low Cost: The Superfast data set consists of interferometric images of the full wafer. These images can be captured rapidly using CCD camera, providing system throughputs of 100-150 wafers per hour.
  • Flexible Implementation: Superfast is capable of evaluating overlay at any step in the process flow and does not rely on dedicated overlay targets. In this manner, Superfast provides the ability to catch potential overlay problems due to process excursions upstream of lithography, thereby reducing material- at-risk and the need for subsequent scrap or rework. 
FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

Case study: millisecond anneal characterization

This section describes a case study to illustrate the application of Superfast technology to characterize a millisecond anneal process. Four wafers of a full-flow 65nm device were annealed using Laser Spike Annealing (LSA). The device contained silicon germanium with 20% Ge. The four wafers were processed at peak annealing temperatures of 1235 or 1270oC and annealing times of 200 or 400 microseconds. Process-induced deformation information was collected by measure pre-anneal and post-anneal wafer topography using the Superfast system. After millisecond annealing, the wafers were processed through to contact patterning. Overlay data was collected post-lithography for all four wafers. The overlay was measured at 9 sites per shot for 28 shots. Surface displacement data was extracted at the same nominal locations on the wafer and displacement residuals were computed using linear inter-field and intra-field correction.

The displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction are shown in FIGURE 3. Inspection of Fig. 3 reveals that the vector maps for the 1235oC temperature conditions (Figs. 3a & 3b) as well as the 1270oC / 200μs condition (Fig. 3c) all exhibit similar features such that the displacement vectors are generally in the same direction at a particular location in those three vector maps with the same relative vector magnitudes within-wafer. On the other hand, the vector map for the 1270oC / 400μs anneal (Fig. 3d) shows a fundamentally different distortion characteristic, indicating perhaps a change in deformation mechanism associated with the higher thermal budgets. This data suggests that wafer distortion measurements may provide a relatively efficient way to study transitions in mechanisms that occur under different processing conditions.

The correlation between the surface displacement residuals and the overlay residuals is shown in FIGURE 4. The data in Fig. 4 is based on the |mean|+3 sigma values of both quantities as evaluated at the locations shown in the vector maps of Fig. 3. There are several features of the plot in Fig. 4 that are notable. First, the corre- lation between overlay residuals and displacement residuals is excellent with a correlation coeffi- cient, r=0.985. Second, the extrapolation of the best-fit straight line to a displacement value of zero indicates a corresponding finite and positive overlay value of ~0.2. This result is not unexpected, since it is anticipated that other factors such as pattern placement error, lens errors and wafer distortion from other processes will contribute to the total overlay error. As such the overlay axis intercept provides an estimate of those other factors. Third, the slope of overlay versus displacement line is <1. A slope of less than 1 is consistent with the concept discussed in section 3, that the non-uniform stress component of the displacement field is related to the force acting along the interface or potential for mis-alignment. In this respect, it represents perhaps the maximum expected mis-alignment and the resulting overlay error will be some fraction of the ‘potential’ (i.e. slope <1). In addition, the slope value indicates that surface displacement is a more sensitive metric than overlay in that for the same process variability, surface displacement will change more rapidly than overlay.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

Summary and conclusions

The tightening of overlay budgets at advanced technology nodes has led to a greater importance in understanding and when possible controlling wafer distortion. This paper has provided a description of a novel measurement and analysis approach to quickly and efficiently evaluate the effect of process-induced deformation on surface displacement and its relation to overlay errors. The millisecond annealing case study showed excellent correlation between the displacement residuals and overlay residuals with the correlation coefficient of 0.985. Utilizing the fundamental advantages of the CGS technology, the superfast is well suited for front- side patterned wafer topography measurement. The system allows for rapid measurement of wafer distortion and surface displacement with very high system throughputs. Data maps consisting of >3,000,000 data points can be acquired in seconds on patterned wafers without the need for special targets or dedicated structures.

Four joint laboratories, representing a commitment of S$200m between private and public sectors, were launched today between A*STAR’s Institute of Microelectronics (IME), and its 10 industry partners. The Advanced Semiconductor Joint Labs will develop and advance semiconductor technologies for future electronics markets. The industry partners involved in this international collaboration are: Applied Materials, Dai Nippon Printing, DISCO, KLA-Tencor, Mentor Graphics, Nikon, Panasonic Factory Solutions Asia Pacific, PINK, Tokyo Electron Ltd. and Tokyo Ohka Kogyo.

While expectations are for smart devices to sustain a compact form factor, consumers also expect powerful performance and low power consumption. The challenge for the semiconductor industry is to meet these needs by addressing system and integration scaling in the electronics market. The four joint labs in lithography, wafer level packaging (WLP), metrology and assembly, will provide an integrated platform for semiconductor R&D, starting with patterning, further development of 3D Integrated Circuits (IC), quality control, and finally, the assembly and high-volume manufacturing of chips.

The joint labs build upon the successful model of the IME-Applied Materials Centre of Excellence. Together, the four labs will enable the development of innovative semiconductor technologies and allow partners to undertake solutions-oriented semiconductor R&D and facilitate commercialisation that is earlier, faster and cheaper. This international partnership also bears testament to the industry relevance of IME’s deep research capabilities, and will encourage further development of solutions for global implementation.

Mr Lim Chuan Poh, Chairman of A*STAR, said, “The launch of IME’s Advanced Semiconductor Joint Labs today is an excellent example of public-private partnership under an open innovation framework. I am pleased that A*STAR IME has entered into this strategic partnership with many leading global industry players to capture new growth opportunities for Singapore and the region. The launch of the Advanced Semiconductor Joint Labs reaffirms A*STAR’s deep capabilities and strong infrastructure in the R&D ecosystem to serve the growing needs of the semiconductor industry.”

Professor Dim-Lee Kwong, Executive Director of IME said, “These joint labs further demonstrate our ability to build a global network of partnerships that stretch across the supply chain. These collaborations will encourage semiconductor R&D that is relevant for industry, and provide solutions for a rapidly evolving global electronics market. Through this integrated platform, our partners can leverage A*STAR IME’s technologies and expertise to develop innovative technologies and products to address challenges in the semiconductor industry.”

By Paula Doe, SEMI

Investors are still looking for differentiated technologies that solve high-value problems in semiconductor manufacturing, or that bring semiconductor technology to disruptive applications in other fields, particularly in the medical and environmental sectors, said the leading venture capitalists gathered at the Silicon Innovation Forum at SEMICON West 2014.

“As financial investors have moved to fund more ‘flapping bird’ apps instead of hardware, strategic investors have moved more to early-stage hardware opportunities,” noted Robert Maire, president, Semiconductor Advisors.

Tallwood Ventures general partner George Pavlov concurred that his financial investment firm was making fewer hardware investments because the technology is maturing and there are fewer opportunities, as well as the lower margins and lower exit prices. “The app maker gets $1 a shot, which is more than the chip maker,” another VC put it more bluntly. That means that semiconductor investments need creative strategies to reduce risk, such as one recent deal that involved three strategic investors all interested in helping the startup succeed, including a customer and a supplier. “It’s also important to have a capitalist at the table to assure that the company’s interest comes first,” Pavlov noted, which may involve making the difficult moves like rebalancing leadership teams or reconstituting the Board of Directors.  Financial investors can also come in early with an experienced team that can help a company find the right strategic partners they need and introduce them.

Strategic investors are getting more involved with early-stage companies to reduce risk even if it means collaborating with the competition. “More and more we are collaborating in investments, and we will see more in the future, in both big and small companies, depending on the size of the problem, when fundamental industry interests are aligned,” said Sean Doyle, director, Intel Capital. “We see greater pull from financial investors to have strategic investors involved from the beginning.” More handholding is needed even before investment. Kurt Petersen, a member of the Band of Angels, noted that three of the group’s members spent two years mentoring a company before it was ready even for angel investment. In fact, a MEMS company may need a strategic investor to even convince a foundry to take it on.

“More than half the investments we’ve made in the last year have been with other strategic investors,” concurred Eileen Tanghal, general manager of Applied Ventures, adding that investing with Intel and Samsung for customer input was especially useful.

Semiconductor startups to watch: The VCs’ current favorites

So where are these investors putting their money in the semiconductor sector these days?  Primarily it’s either towards technologies with potential to solve next-generation semiconductor manufacturing challenges, or towards extending conventional semiconductor technology to new fields, from medicine to agriculture. The strategic investors from the venture arms of Samsung, Intel and Applied Materials all cited innovative materials solutions as the investments about which they were currently most excited, particularly Inpria for its high-resolution metal oxide photoresists, SBA Materials for its liquid-phase self assembled porous ultra low-k dielectrics, and Voltaix (recently acquired by Air Liquide) for its unique precursor gases for germanium and other chemistries. “We’re making more investments in equipment and materials because it is becoming incredibly difficult to advance the technology,” said Dong-Su Kim, senior director, Samsung Ventures Investment Corp.

The VCs saw a wider range of investment opportunities in applying silicon technology to other fields, especially if time-to-market and development costs can be reduced by re-using existing technology.  Peter Moran, general partner, DCM, cited RayVio as a good example, making high power UV LEDs specifically for sterilizing surfaces, with both cost and performance that have no competition from traditional wet or heat methods.  Another of his favorites is battery maker Enovix, which leverages  existing thin-film photovoltaics technology and invovates the battery structure itself for a battery that could potentially store 3X the charge per area. The financial VC worked with strategic investor  Cypress who brought specific manufacturing and scaling expertise from its Sunpower experience, while Intel brought its experience in identifying where, globally, was best to build the manufacturing plant.  Moran also noted that DCM previously did not consider devices that sold for less than a dollar, but it is now looking at lower cost devices as long as they are differentiated and high volume, such as ingestible sensors that track if people have taken their pills.

“The most opportunity is in proliferating silicon technology into other fields, especially in the medical field,” concurred Tanghal, citing Applied Venture’s investments in Oncoscope’s optical screening for pre-cancerous cells to significantly improve the accuracy of biopsies compared to the usual random sampling, Twist Bioscience’s platform for large-scale synthetic gene manufacturing, and  MTPV Power Corp.’s chips that convert heat to electricity.  Applied Ventures is also looking at ongoing opportunities for capturing more value from the inflection point of the emerging Internet of Things, such as supplying the materials for, or the service of, making implantable or ingestible coatings.

The MEMS field continues to come up with new kinds of electromechanical structures for new tasks.  Peterson said he was particularly excited about Chirp Microsystems for its ultrasonic gesture recognition, Next Input with its force-sensitive touch screen technology, and Lumedyne Technologies for its completely new, high accuracy, inertial sensor approach.

VC panels choose Amorphyx and Aledia for best startup pitches

The panel of leading investors selected two companies offering disruptive materials/process technologies — and leveraging a collaborative infrastructure — for the best pitches from among 25 selected startups at the event. Aledia says its microwire LEDs grown on 8-inch silicon should cost 2x-3x less than conventional LEDs grown as thin films on sapphire. The ~1µm diameter pillars, with the active quantum well layers grown vertically in concentric layers, provide more light emitting surface area from less material in less time in the MOCVD reactor.  Their small area on the wafer likely helps ease the lattice and thermal mismatch issues compared to blanket GaN on silicon.  Co-founder, president and CEO Giorgio Anania said the company has figured out how to grow regular, high quality pillars through holes in a mask, though lumens/watt remains low and is not the current focus of improvement. Based on the CEA campus in Grenoble, the startup plans to grow only the pillar layer, then send the wafers out to a mainstream CMOS foundry for the rest of the processing.

The other winner, Amorphyx, offers a fast switching, low cost backplane solution for displays, using a kind of tunneling effect through a near-perfect amorphous sapphire insulating layer in a metal-insulator-metal device. The company is working at ITRI in Taiwan with a production collaborative it put together  three Asian companies, aiming at start joint production in 2015. “This should save $100 of the cost of a $400 display,” claimed CEO and President John Brewer.

Among the other interesting startups pitching to the investors at the event was MEMS microphone startup Baker-Calling, with an innovative simplified design for an AlN piezoelectric MEMS microphone, using four separate triangular plates free to expand and contract so they are less sensitive to film stess than the usual capacitive membranes. CEO Matt Crowley reported the company has sampled prototypes to its strategic investor, and is now bringing up the process at a foundry.

Okeanos Technologies showed its microfluidics desalinization technology, which CEO Tony Frudakis reported uses half the energy to remove salt from water compared to the usual reverse osmosis, because the tiny volumes react better, using an electrochemically mediated process that strips off ions as they pass through the small channel.  However, each pass removes only about 10% of the salt, so multiple cells would be needed to remove all the salt from significant volumes of water.

Inpria leverages grant money for years to take university research towards commercial

The venture arms of Applied Materials, Intel and Samsung have all recently invested in Inpria, and kept citing it as an example of semiconductor development they were excited about for its potential solution to the key problem of resolution of next generation photoresist. Replacing the long, tangled, polymer molecules of traditional photoresist with the smaller inorganic molecules enables cleaner edges and reduces collapse of 7nm and 10nm features.  CEO Andrew Grenville reported that the line-width roughness with this resist is half that of conventional polymer products (0.7nm vs 1.5nm) on 10nm lines and spaces.

Grenville told the tale of the company’s earlier years of leveraging its capital as it developed the metal oxide cluster technology from Oregon State University, starting with NSF/SBIR funding, then a grant from Oregon’s Onami, then joint development funding with potential users. Inpria first developed the material using shared equipment of the Onami university network, then the SEMATECH microexposure tool at Laurence Berkeley national lab, and then in joint development programs at imec’s consortium in projects with equipment suppliers and customers – for about five years before the technology was developed enough for angel investors and Applied Materials. This year strategic investors Intel and Samsung joined Applied in further funding, which then attracted more from the Oregon Angel Fund, with deep semiconductor experience and connections. “We expect we will be interesting for a financial investor in a couple of years,” said Grenville. “It takes leveraging, leveraging, leveraging for capital-efficient development…though the proof will come in 2015 when we go into the fabs.”

The next Silicon Innovation Forum at SEMICON West will be held on July 14, 2015. In addition, SEMICON Europa 2014 (October 7-9) will offer an Innovation Village with a Silicon Innovation Forum.

 North America-based manufacturers of semiconductor equipment posted $1.47 billion in orders worldwide in June 2014 (three-month average basis) and a book-to-bill ratio of 1.09, according to the June EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.09 means that $109 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in June 2014 was $1.47 billion. The bookings figure is 4.3 percent higher than the final May 2014 level of $1.41 billion, and is 10.0 percent higher than the June 2013 order level of $1.33 billion.

The three-month average of worldwide billings in June 2014 was $1.34 billion. The billings figure is 4.8    percent lower than the final May 2014 level of $1.41 billion, and is 10.4 percent higher than the June 2013 billings level of $1.21 billion.

“Semiconductor equipment bookings are at the highest level since May 2012,” said Denny McGuirk, president and CEO of SEMI.  “The strength of the June bookings (three-month average) substantiate the outlook for strong double-digit sales growth this year.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

 

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
January 2014

1,233.2

1,280.3

1.04
February 2014

1,288.3

1,295.4

1.01
March 2014

1,225.5

1,297.7

1.06
April 2014

1,403.2

1,443.0

1.03
May 2014 (final)

1,407.8

1,407.0

1.00
June 2014 (prelim)

1,340.4

1,467.1

1.09

Source: SEMI, July 2014 


By David W. Price and Douglas G. Sutherland

Introduction to the Series:

This is the first in a series of 10 installments which will discuss fundamental truths about process control—inspection and metrology—for the semiconductor industry. By fundamental, we imply the following:

  • Unassailable: They are self-evident, can be proven from first principles, or are supported by the dominant behavior at fabs worldwide
  • Unchanging: These concepts are equally true today for 28nm as they were 15 years ago for 0.25µm, and are expected to hold true in the future
  • Universal: They are not unique to a specific segment of process control; rather they apply to process control as a group, as well as to each individual component of process control within the fab

Each article in this series will introduce one of the 10 fundamental truths and discuss interesting applications of these truths to semiconductor IC fabs. Given the increasing complexity of advanced devices and process integration, process control is growing in importance. By understanding the fundamental nature of process control, fabs can better implement strategies to identify critical defects, find excursions, and reduce sources of variation.

The first fundamental truth of process control for the semiconductor IC industry is:

You can’t fix what you can’t find. You can’t control what you can’t measure.

While it’s true that inspection and metrology systems are not used to make IC devices—they do not add or remove materials or create patterns—they are critical for making high-yielding, reliable devices. By finding defects and measuring critical parameters, inspection and metrology systems monitor the hundreds of steps required to manufacture a device, ensuring the processes meet strict manufacturing specifications and helping fab engineers identify and troubleshoot process issues when there is an excursion.  Without inspection and metrology, it would be near impossible for fabs to pinpoint process issues that affect yield. However, it’s not enough to simply “find” and “measure”—a fab’s process control strategy needs to be capable and cost-effective.

Capable inspection and metrology strategies find and measure the defects and parameters that affect device yield. Cost-effective inspection and metrology is performed at the lowest total cost to the factory, where total cost is the sum of the cost of lost yield plus the cost of process control.

First, Make it Capable:

If you can’t find it, you can’t fix it.  At the heart of this truth is the understanding that, above all else, a fab’s inspection and metrology strategy must be capable. It must highlight the problems that are limiting baseline yield.  It must also provide actionable information that can enable fabs to quickly find and fix excursions.

Fig 1 Fig 2

 

Figure 1.  You can’t fix what you can’t find.  And you can’t control what you can’t measure. Left:  P-MOS SiGe critical dimension measurement. Right:  Fin patterning particle leading to a Fin Spire defect at post dummy gate etch. Source: KLA-Tencor 

We emphasize this need for capability first because we have observed that some fabs are too quick to sacrifice capability for cost reductions. No strategy is cost-effective if it doesn’t accomplish its fundamental objective.

Below are specific questions that can help fab management evaluate the capability of its process control strategy:

  • Are you finding all sources of your defect-limited yield? Are you finding these in-line or at end-of-line?
  • Does your defect Pareto have sufficient resolution of the top yield-limiters in each module to direct the most appropriate use of factory engineering resources?
    • Have you fully characterized all of the important measurements and defect types (size range, kill ratio, root cause, solution)?
    • Do you understand the most probable excursion scenarios?  What is the smallest excursion that you absolutely must detect at this step?  How many lots are you willing to have exposed to this excursion before it is detected?
    • Are you inspecting and measuring at all the right steps?  Can you quickly isolate the point of formation for excursions?  Can you quickly disposition potentially affected lots?
    • Does a particular defect signature become confused by defects added at subsequent process steps? Or do you need separate inspections at each step in order to partition the problem?
    • Do you have overlapping inspections to guard against the high-frequency, high-impact excursions?
      • What is the alpha risk and beta risk for each inspection or measurement?  How are these related to the capture rate, accuracy, precision, matching and more?

Then, Make it Cost-Effective:

Once a capable strategy is in place, then a fab can start the process of making it cost-effective. The best known method for optimizing total cost is usually adjusting the overall lot sampling rate.  This is generally preferred because the capability remains constant. In some cases, it may be possible to migrate to a less sensitive inspection (lower cost of ownership tool or larger pixel size); however, this is a dangerous path because it re-introduces uncertainty (alpha/beta risk) that reduces a fab’s process control capability. This concept will be discussed in more detail in our next article on sampling strategies.

Finally, it is worth pointing out that it is not enough to implement a capable strategy. The fab must ensure that what was once a capable strategy, stays a capable strategy. A fab cannot measure with a broken inspection tool or trust a poorly maintained inspection tool. Therefore, most fabs have programs in place to maintain and monitor the ongoing performance of their inspection and metrology tools.

By optimizing process control strategy to be capable and cost-effective, fabs ultimately find what needs to be fixed and measure what should be controlled—driving higher yield and better profitability.

About the Authors:

Dr. David W. Price is a senior director, and Dr. Douglas Sutherland is a principal scientist at KLA-Tencor Corp.  Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Check out other Process Watch articles: “Exploring the Dark Side,”“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

By Brian Cronquest, Vice President, Technology & IP, MonolithIC 3D Inc.

Hughes Metras, Leti’s VP of Strategic Partnerships North America, introduced the lead talk at their SemiconWest 2014 Leti Day about monolithic 3D technology as the “solution for scaling.” Hughes presented the Leti device technology roadmap which showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to well past 5nm. Here’s the important piece of that roadmap, which highlights the partnership with Qualcomm (ST and IBM helped with some of the work as well):

Fig 1

 

The lead talk was given by device scientist Olivier Faynot, Leti’s Device Department Director.  He titled his talk “M3D, a disruptive approach for further scaling,” and began with why the industry needs a solution for scaling.

Most in the industry are in agreement that scaling past the 22nm node, while still quite technically feasible, has priced itself out of most markets. Olivier discussed the what (transistor costs are no longer decreasing) and the why (litho cost escalation and connectivity inefficiencies of energy and delay). And then he made the statement: “if we just keep the current (2Xnm) technology, we can go farther in cost scaling.” [note: see the following blogs and comments for more info on this crucial topic:  Tech Design Forums summary “3D and EDA need to make up for Moore’s Law, says Qualcomm” and Zvi-Or-Bach’s EETimes blogs Qualcomm Calls for Monolithic 3D IC and  28nm – The Last Node of Moore’s Law.]

Oliver showed a summary of a DAC2014 paper and a Qualcomm/GeorgiaTech DAC2014 paper Power/Performance/Area analysis of M3D for an FPGA:

Fig 2

 

The solution is to build the stack sequentially, in a monolithic fashion. Olivier described their monolithic 3D, or sequential 3D, process flow where the lower-level (first layer) of transistors and its interconnect are conventionally made, then inter-level metal is crafted to help the vertical interconnection, and then a second layer of monocrystalline silicon is layer transferred and oxide-oxide low temperature bonded to the top of the inter-level metal dielectric. This is a blanket layer so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin (10-200nm final), so that direct alignment thru that thin layer to the lower level alignment marks can be made with conventional equipment and achieve conventional alignment tolerances (single digit nanometers).

Now upper-level transistors are formed utilizing SPER (Solid Phase Epitaxial Regrow) for junction doping at 475-600°C and other lower (<400°C) temperature processing for gate stacks, etc. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. Note that the lower level transistor Ni salicides are stabilized with platinum co-deposition and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.

Fig 3

 

Oliver also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. He called the laser (pulsed and short wavelength) option of solving the thermal challenge of monolithic 3D as the “crème brûlée” of methods and they were ‘seeing good results.’ Hopefully we will see published data soon. For more information on SPER and laser processing please see my recent blog Monolithic 3DIC: Overcoming silicon defects.

Fig 4

 

Oliver was also asked in the Q&A if stress was a big issue. He replied that stress was not an issue, rather, the biggest challenges were integration ones (how to form a low temp top transistor, stability of the local interconnect level, and the bottom transistor salicide stability). Olivier was asked in the Q&A what the observed performance differences were between the upper-level and lower-level transistors. He replied” Currently we are achieving 95% (of the lower for the upper). We believe we can make 100%.”

Leti has a 14nmPDK ready to go for those who want to design a test circuit in their monolithic 3D flow. They have ELDO, HSPICE, Virtusoso, Calibre, StarRC, etc. files available.

Fig 5

 

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December 2013, Leti signed an agreement to work with Qualcomm – Qualcomm to Evaluate Leti’s Non-TSV 3D Process. ST and IBM have also been working with Leti in various aspects, for example, IBM & Leti used COMPOSE3 to simulate a monolithic InGaAs nFET monolithically over a SiGe pFET on SOI.

CEA-Leti has been busy working on processing flows to enable monolithic 3D devices since before 2009. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper entitled, “Advances in 3D CMOS Sequential Integration,” where she showed results for a sequentially processed P over N (no metal between transistors layers) testchip Batude’s 2011 IEDM paper showed a 50nm 3D sequential structure on 10nm channel silicon:

Fig 6

 

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications, both parallel and monolithic, with an inauguration event in January 2011. As well, back in December 2013, Soitec and CEA renewed their long-standing partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. I would like to invite you to the IEEE S3S Conference: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference will be held October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

See you there!

IBM announced it is investing $3 billion over the next 5 years in two broad research and early stage development programs to push the limits of chip technology needed to meet the emerging demands of cloud computing and Big Data systems. These investments will push IBM’s semiconductor innovations from today’s breakthroughs into the advanced technology leadership required for the future.

The first research program is aimed at so-called “7 nanometer and beyond” silicon technology that will address serious physical challenges that are threatening current semiconductor scaling techniques and will impede the ability to manufacture such chips. The second is focused on developing alternative technologies for post-silicon era chips using entirely different approaches, which IBM scientists and other experts say are required because of the physical limitations of silicon based semiconductors.

Cloud and big data applications are placing new challenges on systems, just as the underlying chip technology is facing numerous significant physical scaling limits.  Bandwidth to memory, high speed communication and device power consumption are becoming increasingly challenging and critical.

The teams will comprise IBM Research scientists and engineers from Albany and Yorktown, New York; Almaden, California; and Europe. In particular, IBM will be investing significantly in emerging areas of research that are already underway at IBM such as carbon nanoelectronics, silicon photonics, new memory technologies, and architectures that support quantum and cognitive computing.

These teams will focus on providing orders of magnitude improvement in system level performance and energy efficient computing. In addition, IBM will continue to invest in the nanosciences and quantum computing–two areas of fundamental science where IBM has remained a pioneer for over three decades.

7 nanometer technology and beyond
IBM Researchers and other semiconductor experts predict that while challenging, semiconductors show promise to scale from today’s 22 nanometers down to 14 and then 10 nanometers in the next several years.  However, scaling to 7 nanometers and perhaps below, by the end of the decade will require significant investment and innovation in semiconductor architectures as well as invention of new tools and techniques for manufacturing.

“The question is not if we will introduce 7 nanometer technology into manufacturing, but rather how, when, and at what cost?” said John Kelly, senior vice president, IBM Research. “IBM engineers and scientists, along with our partners, are well suited for this challenge and are already working on the materials science and device engineering required to meet the demands of the emerging system requirements for cloud, big data, and cognitive systems. This new investment will ensure that we produce the necessary innovations to meet these challenges.”

“Scaling to 7nm and below is a terrific challenge, calling for deep physics competencies in processing nano materials affinities and characteristics. IBM is one of a very few companies who has repeatedly demonstrated this level of science and engineering expertise,” said Richard Doherty, technology research director, The Envisioneering Group.

Bridge to a “Post-Silicon” Era
Silicon transistors, tiny switches that carry information on a chip, have been made smaller year after year, but they are approaching a point of physical limitation. Their increasingly small dimensions, now reaching the nanoscale, will prohibit any gains in performance due to the nature of silicon and the laws of physics. Within a few more generations, classical scaling and shrinkage will no longer yield the sizable benefits of lower power, lower cost and higher speed processors that the industry has become accustomed to.

With virtually all electronic equipment today built on complementary metal–oxide–semiconductor (CMOS) technology, there is an urgent need for new materials and circuit architecture designs compatible with this engineering process as the technology industry nears physical scalability limits of the silicon transistor.

Beyond 7 nanometers, the challenges dramatically increase, requiring a new kind of material to power systems of the future, and new computing platforms to solve problems that are unsolvable or difficult to solve today. Potential alternatives include new materials such as carbon nanotubes, and non-traditional computational approaches such as neuromorphic computing, cognitive computing, machine learning techniques, and the science behind quantum computing.

As the leader in advanced schemes that point beyond traditional silicon-based computing, IBM holds over 500 patents for technologies that will drive advancements at 7nm and beyond silicon — more than twice the nearest competitor. These continued investments will accelerate the invention and introduction into product development for IBM’s highly differentiated computing systems for cloud, and big data analytics.

Several exploratory research breakthroughs that could lead to major advancements in delivering dramatically smaller, faster and more powerful computer chips, include quantum computing, neurosynaptic computing, silicon photonics, carbon nanotubes, III-V technologies, low power transistors and graphene:

Quantum Computing
The most basic piece of information that a typical computer understands is a bit. Much like a light that can be switched on or off, a bit can have only one of two values: “1” or “0.” Described as superposition, this special property of qubits enables quantum computers to weed through millions of solutions all at once, while desktop PCs would have to consider them one at a time.

IBM is a world leader in superconducting qubit-based quantum computing science and is a pioneer in the field of experimental and theoretical quantum information, fields that are still in the category of fundamental science – but one that, in the long term, may allow the solution of problems that are today either impossible or impractical to solve using conventional machines. The team recently demonstrated the first experimental realization of parity check with three superconducting qubits, an essential building block for one type of quantum computer.

Neurosynaptic Computing
Bringing together nanoscience, neuroscience, and supercomputing, IBM and university partners have developed an end-to-end ecosystem including a novel non-von Neumann architecture, a new programming language, as well as applications. This novel technology allows for computing systems that emulate the brain’s computing efficiency, size and power usage. IBM’s long-term goal is to build a neurosynaptic system with ten billion neurons and a hundred trillion synapses, all while consuming only one kilowatt of power and occupying less than two liters of volume.

Silicon Photonics
IBM has been a pioneer in the area of CMOS integrated silicon photonics for over 12 years, a technology that integrates functions for optical communications on a silicon chip, and the IBM team has recently designed and fabricated the world’s first monolithic silicon photonics based transceiver with wavelength division multiplexing.  Such transceivers will use light to transmit data between different components in a computing system at high data rates, low cost, and in an energetically efficient manner.

Silicon nanophotonics takes advantage of pulses of light for communication rather than traditional copper wiring and provides a super highway for large volumes of data to move at rapid speeds between computer chips in servers, large datacenters, and supercomputers, thus alleviating the limitations of congested data traffic and high-cost traditional interconnects.

Businesses are entering a new era of computing that requires systems to process and analyze, in real-time, huge volumes of information known as Big Data. Silicon nanophotonics technology provides answers to Big Data challenges by seamlessly connecting various parts of large systems, whether few centimeters or few kilometers apart from each other, and move terabytes of data via pulses of light through optical fibers.

III-V technologies
IBM researchers have demonstrated the world’s highest transconductance on a self-aligned III-V channel metal-oxide semiconductor (MOS) field-effect transistors (FETs) device structure that is compatible with CMOS scaling. These materials and structural innovation are expected to pave path for technology scaling at 7nm and beyond.  With more than an order of magnitude higher electron mobility than silicon, integrating III-V materials into CMOS enables higher performance at lower power density, allowing for an extension to power/performance scaling to meet the demands of cloud computing and big data systems.

Carbon Nanotubes
IBM Researchers are working in the area of carbon nanotube (CNT) electronics and exploring whether CNTs can replace silicon beyond the 7 nm node.  As part of its activities for developing carbon nanotube based CMOS VLSI circuits, IBM recently demonstrated — for the first time in the world — 2-way CMOS NAND gates using 50 nm gate length carbon nanotube transistors.

IBM also has demonstrated the capability for purifying carbon nanotubes to 99.99 percent, the highest (verified) purities demonstrated to date, and transistors at 10 nm channel length that show no degradation due to scaling–this is unmatched by any other material system to date.

Carbon nanotubes are single atomic sheets of carbon rolled up into a tube. The carbon nanotubes form the core of a transistor device that will work in a fashion similar to the current silicon transistor, but will be better performing. They could be used to replace the transistors in chips that power data-crunching servers, high performing computers and ultra fast smart phones.

Carbon nanotube transistors can operate as excellent switches at molecular dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of the leading silicon technology. Comprehensive modeling of the electronic circuits suggests that about a five to ten times improvement in performance compared to silicon circuits is possible.

Graphene
Graphene is pure carbon in the form of a one atomic layer thick sheet.  It is an excellent conductor of heat and electricity, and it is also remarkably strong and flexible.  Electrons can move in graphene about ten times faster than in commonly used semiconductor materials such as silicon and silicon germanium. Its characteristics offer the possibility to build faster switching transistors than are possible with conventional semiconductors, particularly for applications in the handheld wireless communications business where it will be a more efficient switch than those currently used.

Recently in 2013, IBM demonstrated the world’s first graphene based integrated circuit receiver front end for wireless communications. The circuit consisted of a 2-stage amplifier and a down converter operating at 4.3 GHz.

Next Generation Low Power Transistors
In addition to new materials like CNTs, new architectures and innovative device concepts are required to boost future system performance. Power dissipation is a fundamental challenge for nanoelectronic circuits. To explain the challenge, consider a leaky water faucet — even after closing the valve as far as possible water continues to drip — this is similar to today’s transistor, in that energy is constantly “leaking” or being lost or wasted in the off-state.

A potential alternative to today’s power hungry silicon field effect transistors are so-called steep slope devices. They could operate at much lower voltage and thus dissipate significantly less power. IBM scientists are researching tunnel field effect transistors (TFETs). In this special type of transistors the quantum-mechanical effect of band-to-band tunneling is used to drive the current flow through the transistor. TFETs could achieve a 100-fold power reduction over complementary CMOS transistors, so integrating TFETs with CMOS technology could improve low-power integrated circuits.

Recently, IBM has developed a novel method to integrate III-V nanowires and heterostructures directly on standard silicon substrates and built the first ever InAs/Si tunnel diodes and TFETs using InAs as source and Si as channel with wrap-around gate as steep slope device for low power consumption applications.

“In the next ten years computing hardware systems will be fundamentally different as our scientists and engineers push the limits of semiconductor innovations to explore the post-silicon future,” said Tom Rosamilia, senior vice president, IBM Systems and Technology Group. “IBM Research and Development teams are creating breakthrough innovations that will fuel the next era of computing systems.”

IBM’s contributions to silicon and semiconductor innovation include the invention and/or first implementation of: the single cell DRAM, the “Dennard scaling laws” underpinning “Moore’s Law”, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed silicon germanium (SiGe), High-k gate dielectrics, embedded DRAM, 3D chip stacking, and Air gap insulators.

IBM researchers also are credited with initiating the era of nano devices following the Nobel prize winning invention of the scanning tunneling microscope which enabled nano and atomic scale invention and innovation.

IBM will also continue to fund and collaborate with university researchers to explore and develop the future technologies for the semiconductor industry. In particular, IBM will continue to support and fund university research through private-public partnerships such as the NanoElectornics Research Initiative (NRI), and the Semiconductor Advanced Research Network (STARnet), and the Global Research Consortium (GRC) of the Semiconductor Research Corporation.

By Zvi Or-Bach, President & CEO of MonolithIC 3D Inc.

Our blog Paradigm shift: Semi equipment tells the future, was focused on the quote: “Now more money is spent on upgrading existing facilities, while new capacity additions are occurring at a lower pace.” And now, just prior to Semicon West, we have the conclusion of the recent SEMI’s World Fab Forecast — Technology Node Transitions Slowing Below 32 nm. The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. The following chart illustrates this new paradigm:

1

 

The report states: “The cost per wafer has become an increasing concern below the 32nm node.   The expected cost reduction benefit of production at smaller nodes is diminishing and is not keeping pace with the scaling benefits in many cases.  This has widespread and fundamental implications for an industry long following the cadences of Moore’s Law… These may be contributing factors as to why some volume fabs are exhibiting a lag in beginning production of new technology node.  Now evident quantitatively for the first time, there is evidence of a clear slowdown in volume production scaling of leading technology node transitions.” (emphasis added)

It is fitting to point to the comment made to EE Times coverage on Semicon West – 13 Things I Heard at Semicon West: “No matter what Intel says, Moore’s Law is slowing down,” said Bob Johnson, a semiconductor analyst for Gartner. “Only a few high-volume, high-performance apps can justify 20 nm and beyond.” He sees problems ahead for logic chips in general,” and to follow with quotes from another EE Times article – Silicon Highway Narrows, Twists: “Most foundries have yet to start buying the capital equipment needed for the 14/16 nm node, which for many will be the first to support FinFETs, says Trafas of KLA-Tencor. Gear companies hope the orders start coming in the fall…Indeed, he says, one of the big questions many capital equipment execs will bring to this year’s Semicon West event on July 7 is, “When will the 16/14 nm investments begin?”

Since the 65 nm node, escalating costs of fab and process technology development and design, as illustrated in the chart below, put a huge pressure on the industry.

2

 

These escalating costs drove consolidation in the industry, cutting down to a handful the vendors who are still pursuing the leading edge.

At the recent (2014) SST ConFab in Las Vegas Bill McClean shared his annual report on Major trends shaping the future IC Industry. Bill reports: “Over the last two decades, the percentage of capex being spent by the top 5 has steadily increased to its current 70% with the big three of Samsung, Intel and TSMC being responsible for over 50%.” This is illustrated by the following chart.

3

 

Clearly the escalating costs drove out most but the largest vendor, but now we are facing the ”second punch” – the diminishing returns.

In the recent ITC conference Harry J. Levinson of GlobalFoundries in his talk: Lithography Issues for High Volume Manufacturing” presented the following chart:

4

 

The dramatic increase of lithography cost eats away the historical transistor cost reduction resulting from reduced dimensions, as we reported in our blog Qualcomm: Scaling down is not cost-economic anymore – so we are looking at true monolithic 3D. Quoting Qualcomm “One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down it’s not cost-economic anymore. It’s creating a big problem for us.” Accordingly we detailed in our blog that Moore’s Law has stopped at 28nm and following nodes would not provide lower transistor cost, and for most application will result in higher SoC costs.

We should not be surprised that the production ramp up below 28 nm is extremely slow. There is too much money involved to put it into the wrong place.

Going back to the SEMI World Fab Forecast, the authors ask “What’s next?” and respond: “Many in our industry are grappling with what to do as they have perceived the coming slowdown in technology node transitions.  IC manufacturers are now increasingly looking outside of conventional lithography and wafer size scaling approaches to pick up the pace of cost reduction while increasing transistor density and performance. Using memory as an example, to cope with increasing challenges in continuing to scale 2D, memory companies are looking into 3D.”

So the memory vendors already started shifting their Capex budget to scaling up with 3D NAND, instead of scaling to smaller dimension. Recently Qualcomm announced their collaboration with SMIC – China’s SMIC-Qualcomm 28-nm Deal: Why Now? – indicating more capacity build-up for 28 nm with looking forward to scaling up with monolithic 3D for logic as well. Quoting: “Going forward, SMIC will also extend its technology offerings on 3DIC and RF front-end wafer manufacturing in support of Qualcomm”.

It is clear now that we are seeing a paradigm shift in the semiconductor equipment industry. After many decades of relentless dimensional scaling every two years, there is a change coming and we see a lower rate of dimensional scaling and exploration of other paths, to keep industry’s march on. We do believe that the next few decades will be about scaling with 3D Integration and we are pleased to see many others thinking the same.

The 2014 S3S Conference is scheduled for October 6-9, 2014, at the Westin San Francisco Airport, and would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

By Jeff Dorsch

The worldwide semiconductor capital equipment market is forecast to increase 20.8 percent this year to $38.44 billion, compared with 2013’s $31.82 billion, and another 10.8 percent in 2015 to $42.6 billion, according to Semiconductor Equipment and Materials International.

Also on Monday, the Semiconductor Industry Association reported that global sales of semiconductors were $26.86 billion in May, an 8.8 percent increase from a year earlier and a 2 percent improvement from April of this year.

Jonathan Davis, SEMI’s global vice president of advocacy, said Monday that the semiconductor industry is seen growing 5 percent to 10 percent in 2014, and noted that all world regions posted growth in sales during May, a statistical factor not recorded since August 2010.

Discussing expenditures on capital equipment, Davis said, “The nature of the spending is changing.” The number of new wafer fabs has dwindled in recent years, and more spending is directed these days to upgrading existing fabs.

2015 promises to be the biggest year for semiconductor equipment spending since 2000, Davis said. While the equipment market is growing more than 20 percent this year, the semiconductor materials market will see more modest growth in 2014, at 6 percent, he added.

Karen Savala, the president of SEMI Americas, reviewed economic and technology trends in the equipment and materials business during Monday’s SEMI press conference. The industry has gone through “one of the largest consolidation periods in our history,” including the pending blockbuster merger between Applied Materials and Tokyo Electron Ltd. (TEL), she noted.

The longstanding economics of Moore’s Law is being challenged, she added. The Internet of Things is a tremendous opportunity for the chip-making business, yet it doesn’t involve leading-edge technology, Savala said. “Traditional node scaling seems to be slowing,” she observed. Scaling is apparently decelerating below the 32-nanometer process node, according to Savala, but it may be advanced with the introduction of new materials, new substrates, and 2.5D/3D packaging.

“The ecosystem is changing,” Savala said.

SEMI now forecasts that wafer processing equipment will grow 22.7 percent in 2014 to $31.12 billion, from $25.36 billion in 2013, and advance 11.9 percent more in 2015 to $34.81 billion. Test equipment is expected to see a 12.5 percent increase this year to $3.06 billion and pick up by 1.6 percent next year to $3.11 billion. Assembly and packaging equipment is forecast to reach $2.52 billion in 2014, an 8.6 percent improvement from last year, and growing 1.2% in 2015 to $2.55 billion. Other equipment categories will be up 22.5 percent this year to $1.74 billion and up 21.8 percent next year to $2.12 billion.

All global regions except one, the rest of the world, are forecast to post increased sales in 2014, according to SEMI. Taiwan will remain the largest region with $11.57 billion in equipment sales this year, up 11.57 percent from 2013, while higher growth rates will be seen in China, North America, South Korea, Japan, and Europe. All regions are expected to show growth in 2015, ranging from 1.6 percent in China up to 47.8 percent in Europe.

SEMI 2014 mid-year equipment forecast.

SEMI 2014 mid-year equipment forecast.