Category Archives: Metrology

Test professionals who want to learn, forecast and debate the future of semiconductor test will attend the 7th annual IEEE Test Vision 2020 Workshop, held in conjunction with SEMICON West 2014 (July 8-10) in San Francisco. The event will feature speakers from Qualcomm, Gartner, AMD, GLOBALFOUNDRIES, and Mentor Graphics, along with speakers from key semiconductor test industry suppliers. Organized by SEMI and sponsored by the IEEE Instrumentation and Measurement Society, Test Vision 2020 (July 9-10), is a two-time winner of the ATE Test Technology Technical Council’s “Most Successful Event” Award. Test Vision 2020 serves as a valuable platform where foundries, IDMs and fabless companies discuss their critical test requirements with leading test equipment and solution providers.  Attendees include semiconductor test engineers, product engineers, test managers, product managers, test equipment users, developers, and industry analysts. Registration for Test Vision 2020 is now open.

Test Vision 2020 (July 9-10) will convene a first-class gathering of thought leaders, users, and suppliers of test IP and equipment. The Internet of Things (IoT) will dominate the discussion, as the mainstreaming of “connected devices” creates challenges unique to test and test assumptions. The Test Vision 2020 workshop will feature industry speakers, poster sessions, presentations and participation from semiconductor test industry leaders, including:

  • Key presentations: Michael Campbell, senior VP at Qualcomm Technology, on “Testing the THINGS of the Internet of Things” and Dean Freeman, Research VP at Gartner Research, on “How the IoT will Impact the Semiconductor Industry”
  • Panel:  “The Pros and Cons of DiY Tester Development” with Ken Lanier from Teradyne moderating panelists from Advantest, Altera, Amkor, KYEC, National Instruments, and Texas Instruments
  • “IoT Test & Quality” session with presenters from AMD, Mentor Graphics, and Teradyne
  • “2.5D / 3D Probe & Test” session with speakers from GLOBALFOUNDRIES and FormFactor
  • “Big Data” session with presenters from Roos Instruments, Galaxy Semiconductor, and AMD
  • “Distinguished Guest Lecturers on IoT-related Topics” with speakers from Asset InterTech, Xcerra, and Cascade Microtech
  • Reception with Poster Session

Platinum sponsors of Test Vision 2020 include Advantest, FormFactor, and Teradyne.

For more information, visit Test Vision 2020. Register by June 6 for “early bird” prices. SEMICON West 2014 also offers additional Test programs — please visit www.semiconwest.org/SessionsEvents/Test.

By Debra Vogler, SEMI

The semiconductor industry never lacks for challenges and/or controversy as it forges ahead from one technology node to the next. “Lithography is always a challenge,” observes Dick James, senior technology analyst at Chipworks. While there may be a non-EUV roadmap to 7nm, what will happen by 5nm is not so clear, except “by the time the industry gets to 5nm, silicon will have run out of steam,” said James. His recitation of the coming mountains to climb is extensive: integration of new materials, contact resistance of ever-smaller contacts, pitch quartering, contact etch and self-aligned vias, shrinking the gate stack, and modifying work function materials. And that’s just the front-end!

“The big divide at the moment is FDSOI vs FinFET,” James told SEMI. “If IBM survives, I could see them following the FDSOI route, but the rest of the industry seems to be going FinFET. By the time we get to 7nm and 5nm it will likely be moot, we’ll have to do something else such as nanowires…in the end, it all boils down to performance vs. cost.”

With respect to performance and scaling, Soitec’s SVP of Digital Electronics Division and FDSOI guru Christophe Maleville, a clear proponent of SOI-based technology, told SEMI that a key challenge is delivering a worthwhile performance increase while allowing very low energy consumption. “In the PC era, performance was king,” observed Maleville, who will speak at SEMICON West 2014. “Although power consumption was obviously a concern, it was okay to trade GHz for high leakage current. With the advent of the mobile, always-on device era, the weights of priorities have shifted.” With mobile applications driving the industry, performance must also take into account low heat dissipation and battery life. “Delivering high drive current is one thing – and FinFET appears to be pretty good at that – but this has to be weighed against the other parameters that affect the actual in-application performance of the chip.”

Medium-term, i.e., down to the 10nm node, Maleville said that while there is a choice in transistor technology between FDSOI and FinFET, the latter has its challenges (Figure 1). At 14nm and below, particularly for bulk silicon, Maleville cites issues such as controlling substrate leakage and maintaining good variability. “In addition, because of its 3D architecture, parasitic capacitance of the FinFET device is relatively high and scaling means reducing the pitch into which FinFET transistors need to fit, which does not go in the direction of limiting (fringe) parasitic capacitance” said Maleville. “Beyond 14nm, these challenges will become even more pressing.” Doing FinFET on SOI can help alleviate some of these challenges because it offers intrinsic isolation under the fin, thereby removing the need for a complex-to-optimize punch-through stopper junction. “It also eliminates some variability associated with the doping this junction requires.” FinFET on SOI also aids in the manufacture of fins with well-defined height, “therefore, ensuring no excessive variability from fin geometry fluctuations.”

Fig. 1

Fig. 1

FDSOI technology is not without its own set of challenges. “The electrostatic control of an FDSOI transistor is, in principle, not as good as that of a multi-gate device,” Maleville explained. “On the other hand, FDSOI is less subject to some of the pains associated with scaling FinFETs, such as keeping parasitic capacitance low enough, or keeping variability (including that originating from transistor geometry variations) under control.” Figure 2 illustrates the value that using SOI brings (for FD-2D technology) in terms of silicon geometry control and uniformity.

Fig. 2

Fig. 2

With respect to scaling FDSOI technology to 14nm, Maleville noted that excellent results were reported at IEDM 2013 and that both Leti and STMicroelectronics are showing roadmaps to scale FDSOI down to 10nm, with introduction of Ge in the channel, along with further source/drain optimization and the option to use strained SOI. With respect to starting SOI wafers, the key areas of work already underway according to Maleville are: 1) ensuring excellent thickness uniformity of the thin silicon layer, which needs to be improved from one node to the next; 2) reducing the thickness of the buried oxide from one node to the next, and 3) continuing to provide ultra-thin layers of top silicon with state-of-the-art defectivity required at each node.

Industry experts interviewed on the topic of scaling are in agreement about new device architectures (e.g., gate-all-around, nanowires, tunnel FET, etc.) along with new materials (e.g., Ge and III-V compound semiconductors). Regarding the introduction of new materials, Maleville notes that the following will have to be considered: 1) demonstrating at the device level that there is a CMOS solution based on the new materials that deliver better results than silicon in the power supply and geometrical dimension ranges envisaged for the 7nm-5nm nodes, and 2) finding a way to implement Ge or a III-V material of suitable quality for good transistor behavior. “The Smart Cut layer transfer technology employed to fabricate SOI wafers has a role to play here,” said Maleville. “In particular, transferring germanium or III-V materials onto an oxidized silicon base (i.e., doing GeOI or III-V.OI) can be an interesting alternative to epitaxial growth of these materials on a bulk substrate.”

Because of lattice mismatch, Maleville further explained that epitaxial growth of Ge or III-V on silicon is challenging and achieving decent material quality is difficult. Though the alternative approach of Smart Cut-based layer transfer comes with its own set of challenges (defectivity, etc.), “it has the advantage of allowing the slice of a high-quality layer from a donor that can have defects outside the transferred layer, and the ability for this donor to be recycled multiple times.”

Enter CNTs

While the industry winds its way through the myriad choices of lithography technologies, transistor architectures, and materials choices, experts note that once the industry gets to 5nm, something new will have to happen. One technology getting close scrutiny is carbon nanotube (CNT) logic transistors. H.S. Philip Wong, the Willard R. and Inez Kerr Bell Professor in the School of Engineering and Professor of Electrical Engineering at Stanford University, told SEMI that transistors made with carbon nanotubes as the channel material hold special promise. The promise is due to the ultra-thin body of the carbon nanotube being only about one nanometer, while at the same time retaining excellent carrier transport properties. “No other bulk semiconductor has this unique advantage that allows the carbon nanotube transistor to scale to the shortest possible gate length,” said Wong (Figure 3).

Fig. 3

Fig. 3

The key issues in bringing CNT logic transistors to the forefront, noted Wong, include: 1) contact resistance (reducing the transfer length of the contact); 2) maintaining good carrier transport while meeting electrostatic requirements; 3) having a coordinated effort in industry (as exemplified by how the semiconductor industry solved the high-k/metal gate problem); and 4) taking a practical approach and recognizing that exotic, non-FET-based devices will not meet the time line of the industry for the 5nm node.

Recent developments of CNT transistor technology for digital logic include the synthesis of fully aligned carbon nanotubes on a wafer scale, device fabrication of high-performance carbon nanotube transistors, 3D integrated carbon nanotube circuits, low voltage (0.2 V) operation of carbon nanotube transistors, and compact models for circuit simulation. Performance benchmarking of carbon nanotube transistors with conventional CMOS at the device and the full-chip processor level have also been accomplished, along with the demonstration of circuits and complete systems.

Interested in learning more about the industry getting down to the 5nm node? Come hear from Soitec, imec, Intermolecular, GLOBALFOUNDRIES, SEMATECH, Stanford University, and G450C at the SEMICON West 2014 Semiconductor Technology Symposium (STS)  session titled “Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and Beyond.”  For information about this program, the agenda or pricing, please visit www.semiconwest.org/sts. SEMICON West 2014 will be held July 8-10 at the Moscone Center in San Francisco.

Today, KLA-Tencor Corporation announced the Teron SL650, a new reticle quality control solution for IC fabs that supports 20nm design nodes and beyond. With 193nm illumination and multiple STARlight optical technologies, the Teron SL650 provides the sensitivity and flexibility required to assess incoming reticle quality, monitor reticle degradation and detect yield- critical reticle defects, such as haze growth or contamination in patterned and open areas. In addition, the Teron SL650’s industry-leading production throughput supports the fast cycle times required to qualify the increased number of reticles associated with advanced multi- patterning techniques.

“For IC manufacturers, understanding the reticle state is a central component of patterning process control as changes in reticle quality can have a devastating impact on every wafer printed,” said Yalin Xiong, Ph.D., vice president and general manager of the Reticle Products Division (RAPID) at KLA-Tencor. “With the Teron SL650, our team has incorporated state-of-the-art reticle inspection technologies on a compact platform suitable for the IC fab, producing a reticle quality control system with advanced sensitivity, high productivity and extendibility for future nodes. By monitoring incoming reticles for critical defects and identifying progressive defects and changes to the mask pattern during production, our Teron SL650 can help chipmakers protect device yield, performance and cycle time.”

The Teron SL650 supports a mix of reticle types within the fab by using STARlightSD and STARlightMD to produce superior defect capture and comprehensive inspection coverage on single- and multi-die reticles, respectively. Chipmakers can also use the innovative STARlightMaps technology to track reticle degradation over time and identify CD, film thickness, anti-reflective coating and other variations across the reticle—changes in reticle quality that can affect the lithographic process window or pattern printing. Moreover, the Teron SL650 is EUV-compatible, enabling early collaboration with IC manufacturers on in- fab EUV reticle inspection requirements.

Multiple Teron SL650 reticle inspection systems have been installed at foundry, logic, and memory manufacturers worldwide where they are being used for incoming quality check and re-qualification of reticles used in advanced IC manufacturing. To maintain the high performance and productivity demanded by leading-edge production, the Teron SL650 systems are backed by KLA-Tencor’s global comprehensive service network.

North America-based manufacturers of semiconductor equipment posted $1.44 billion in orders worldwide in April 2014 (three-month average basis) and a book-to-bill ratio of 1.03, according to the April EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.03 means that $103 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in April 2014 was $1.44 billion. The bookings figure is 10.8 percent higher than the final March 2014 level of $1.30 billion, and is 22.5 percent higher than the April 2013 order level of $1.17 billion.

The three-month average of worldwide billings in April 2014 was $1.40 billion. The billings figure is 14.1  percent higher than the final March 2014 level of $1.23 billion, and is 28.7 percent higher than the April 2013 billings level of $1.09 billion.

“Sales of semiconductor manufacturing equipment from North American producers continue to demonstrate strong sequential and year-over-year growth,” said Denny McGuirk, president and CEO of SEMI.  “The data through the first quarter reflects momentum in memory, foundry, and back-end spending.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
November 2013

1,113.9

1,238.0

1.11
December 2013

1,349.7

1,380.8

1.02
January 2014

1,233.2

1,280.3

1.04
February 2014

1,288.3

1,295.4

1.01
March 2014 (final)

1,225.5

1,297.7

1.06
April 2014 (prelim)

1,398.5

1,438.2

1.03

Source: SEMI, May 2014
The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

Only a direct measurement of SRAM structures can represent true variations of metal gate height due to CMP process and is strongly affected by the design and layout of pattern, including pattern density, dummy design, and spacing.

By CHUN WEI HSU, United Microelectronics Corp., Tainan City, Taiwan; JOHNNY DAI,Rudolph Technologies, Inc., Budd Lake, New Jersey, USA

The pursuit of Moore’s law has dictated the scaling of semiconductor devices and has led to successful shrink of device form structures while delivering significant transistor performance improve- ments. In order to keep pace with the need for improved performance, new materials and new process integration schemes have been developed. High-K/ metal gate technology, introduced by Intel to replace the conventional oxide gate dielectric and polysilicon gate, has truly revolutionized transistor technology more than any other change over the last 40 years. First introduced at the 45nm node, this complex process has now been adopted for advanced nodes as the primary approach to address gate leakage and the reduction in gate capacitance due to poly Si gate electrode depletion issues [1].

FIGURE 1. (a) Schematic representation of the PULSE set up and (b) position sensitive detection (PSD) method.

FIGURE 1. (a) Schematic representation of the PULSE set up and (b) position sensitive detection (PSD) method.

Two main integration schemes have been adopted by device manufacturers. The gate first approach (also known as Metal-Inserted Poly Si-MIPS) is similar to the oxynitride/poly process flow and is the preferred method for applications that require lower power that do not need the aggressive scaling of gate thickness [2,3]. The gate last approach (also known as Replacement Metal-Gate or RMG) takes advantage of strain enhancement techniques, such as e-SiGe, and a poly Si removal step and significantly improves hole mobility, making RMG an attractive option for high performance applications. The replacement metal gate approach includes two chemical mechanical polishing (CMP) steps. One is the poly opening polish (POP) process before dummy poly removal and the second is the aluminum CMP (AlCMP) process after work function metal deposition. Known concerns with this AlCMP process are Al dishing/erosion, gate height uniformity control and introduction of various types of defects that affect the performance and yield of the final device [4]. Control of gate height and uniformity is critical to transistor performance and precisely controlling this height is the primary challenge for the replacement metal gate AlCMP process. Non-uniform gate height can cause gate resistance variation, which results in parametric issues for the device. Thinner gate heights can result in over etched contacts [5]. The dimensional tolerance of the AlCMP process is much more challenging (10 times tighter) than the conventional CMP process because the metal gate height is only several hundred Angstroms [6]. Hence, in-line gate height monitoring is necessary for RMG to control gate resistance and avoid over etched contacts.

In this article we evaluate the capability of picosecond ultrasonic sonar measurements for in-line monitoring of high-/metal gate structures and demonstrate the benefits of this technology for measuring various structures, including SRAM, pad array, and line array key, with excellent correlation to cross sectional trans- mission electron microscopy (TEM). We have shown that only a direct measurement of SRAM structures can represent true variations of the metal gate height due to CMP process and is strongly
affected by the design and layout of
pattern, including pattern density,
 dummy design, and spacing. The small
spot, non-contact, and non-destructive
nature of this technology allows for
in-line measurements directly on these
structures with excellent repeatability
at a very high throughput.

Picosecond ultrasonic measurements


The Picosecond ultrasonic technology (PULSE) is a unique way of measuring opaque film thickness using an ultra-short pulsed laser. Because the technique is non-contact and non-destructive, it can be used directly on product wafers. In addition to thickness measurements, it can measure parameters such as roughness, density, phase and modulus to provide additional information about the reflected acoustic wave reaches the wafer surface, it is detected by a probe laser pulse, which was diverted from the pump pulse by a beam splitter and routed through a servo- controlled delay circuit to introduce a known variable delay process.

FIGURE 1a shows the optics layout of this technology. The system uses a pump-probe measurement technique. A 0.1ps pump laser pulse focused into a 5_7_m2 spot on the wafer surface induces a sharp acoustic wave that travels away from the surface through the film at the speed of sound. At each interface between layers a portion of the acoustic energy is reflected back toward the surface while the rest is transmitted. When the reflected acoustic wave reaches the wafer surface, it is detected by a probe laser pulse, which was diverted from the pump pulse by a beam splitter and routed through a servo-controlled delay circuit to introduce a known variable delay.

FIGURE 2. TEM cross-section of product wafers generated for characterization using picosecond ultrasonic measurements.


FIGURE 2. TEM cross-section of product wafers generated for characterization using picosecond ultrasonic measurements.

There are two different methods of
 detecting the arrival of the reflected acoustic
 wave at the surface. The first method is to
 detect the change of optical reflectivity caused
by the strain of acoustic wave. The second method is to detect the deflection of the reflected probe beam that is caused by the deformation of surface due to the acoustic wave. The second method requires a position sensitive detector (PSD) as shown in FIGURE 1b.

FIGURE 3. Schematic representations of measurement sites (a) SRAM, (b) Pad array (c) Line array key.

FIGURE 3. Schematic representations of measurement sites (a) SRAM, (b) Pad array (c) Line array key.

The PSD method shows better sensitivity and signal-to-noise for measuring thick copper and line array structures. Data reported in this article takes advantage of both measurement methods. The servo-delay controls the time difference between pump and probe, allowing accurate measurement of the round trip travel time of the acoustic wave within the film. Multiplying the one-way travel time (half of the roundtrip time) by the speed of sound in the material yields the layer thickness (equation 1). The thicknesses of component layers of a multi-layer film stack can be calculated similarly from the analysis of multiple return echoes from a single measurement.

(1) d=(v)(t)/2

where d is the film thickness in Å, v is the speed of sound in the material in Å/ps and t is the transit time in ps. Thickness is calculated from first principles and does not require calibration standards or reference wafers. Calibration of the system relies primarily on the positional accuracy of the delay stage. This is calibrated using optical encoders and corresponds to 1-1.5Å of the film thickness. This level of intrinsic matching allows for easy system-to-system matching across wafer fabs.

FIGURE 4. Raw data showing change in deflection versus time. The measurements are from DOE skew wafers of varying thickness from the SRAM structure. The large zero peak is the pump laser pulse and the next peak to the left is the first returning echo. The time elapsed to the first echo is seen to increase for the three wafers, corresponding to known increases in thickness.

FIGURE 4. Raw data showing change in deflection versus time. The measurements are from DOE skew wafers of varying thickness from the SRAM structure. The large zero peak is the pump laser pulse and the next peak to the left is the first returning echo. The time elapsed to the first echo is seen to increase for the three wafers, corresponding to known increases in thickness.

Experimental

Product wafers including a nominal stack of PVD Al film/ CVD Al seed layer/ PVD Ti wetting layer/ N or P MOSFET work function metals/ TaN etch stop layer/ CVD oxide film/ Si-substrate were prepared (FIGURE 2) to systematically study the effects of CMP processes on the stack, specifically, characterization of metal gate height loss and Al metal dishing followed by defect analysis. The AlCMP process was carried out on a rotary type polisher with three polishing platens. Multiple sets of wafers (different products) with varying thickness skew were generated to test the capability of the picosecond ultra- sonic technique to measure a wide variety of structures: SRAM, pad array, and line array key (commonly measured by CD metrology tools). The arrays are shown schematically in FIGURE 3. The SRAM structure, although challenging with only 40% metal density, was selected to provide information on true process variation. Pad arrays (75% metal density) and line array keys (50% metal density) were also chosen to provide a comparison with the SRAM structure and to help determine the extent of pattern dependent variations in CMP rates. Structures for both N well and P well stacks of varying array widths were investigated.

FIGURE 5. Correlation of PULSE vs TEM measurements of (a) SRAM (b) Pad array and (c) Line array.

FIGURE 5. Correlation of PULSE vs TEM measurements of (a) SRAM (b) Pad array and (c) Line array.

FIGURE 6. Resistivity measurements vs picosecond ultrasonic gate height measurements showing excellent correlation on both (a) NMOS and (b) PMOS devices.

FIGURE 6. Resistivity measurements vs picosecond ultrasonic gate height measurements showing excellent correlation on both (a) NMOS and (b) PMOS devices.

Results and discussion

FIGURE 4 shows the raw timing
data of a PULSE measurement from
a center die on three thickness skew
wafers. The time elapsed between
the pump pulse and the returning
echoes, 7.3ps, 8.0ps, and 8.3ps, can
be used to calculate the thickness of
the layers (Al gate+work function).
 Longer times indicate thicker
films. Unlike other spectroscopic 
metrology technologies, which 
require sophisticated modeling and
 calibration, picosecond ultra sonic
technology provides a simple, direct measurement of thickness.

The accuracy of PULSE measurements for a wide thickness range of all three different structures was verified by comparison
to measurements made on the cross sectional TEM images. FIGURE 5 (a), (b) and (c) show the correlation between picosecond ultrasonic measurements and TEM on SRAM, pad array and line array keys, respectively. Correlation with TEM is excellent for all three structures (R2> 0.9).

PULSE measurements were also compared to resistivity (Rs) measurements to verify accuracy. FIGURE 6 shows Rs measurement for both NMOS and PMOS structures. Rs and PULSE measurements of gate height were conducted at Metal 3, and the AlCMP process step, respectively. The correlation between PULSE and Rs for both structures is ~ 0.90. The high correlation made it possible to predict Rs performance of the device at AlCMP.

In-line Monitoring Strategy: SRAM vs. Pad Array and Line Array Keys Pad arrays, nominally grids of pads with NMOS structure, or line array keys of varying metal density, are typically used for metrology thickness measurements but provide only an indirect indication of gate height. This study was specifically designed to evaluate picosecond ultrasonic technology’s capability to measure SRAM structures as a direct monitor of gate height, and, if successful, to adopt this strategy for in-line monitoring.

Direct measurement of gate heights in SRAM is complicated by the multilayer structure of the NMOS and PMOS devices, which have different work function metals and cross single trench isolation areas that introduce gate height variations. Given the complexity of the stack, concerns also exist regarding the accuracy and reliability of the measurement for in-line use. Measurements on pad and line array keys can only serve as an indirect measurement due to well-known pattern dependent variations in polishing rates. CMP rates are known to be affected by variations in design and layout of the pattern, differences in surrounding areas between grid pads and SRAM, pattern density differences, and effects of a dummy design, all of which can impact thickness measurement on the pads and arrays but does not represent the behavior on the SRAM structure.

Direct picosecond ultra- sonic measurements of gate height within the SRAM are feasible and show excellent correlation with TEM and resistivity measurements. Moreover, since the measurements are fast (<2 seconds), PULSE technology allows for sampling of more structures and die on the wafer to better characterize uniformity across wafer. The wafers show very similar profiles and the measurements can help process engineers better understand sources of within wafer variation. These measurements provide useful information for process optimization especially during development.

FIGURE 7. Correlation between SRAM gate height vs. PULSE for various structures.

FIGURE 7. Correlation between SRAM gate height vs. PULSE for various structures.

FIGURE 7 shows the correlation between the SRAM gate heights as measured by TEM and PULSE thickness measurements for the various structures. PULSE measurements made directly on SRAM structures show excellent correlation (R2 = 0.94) with SRAM gate height. Additionally, high resolution scans were performed across the SRAM structures to characterize dishing/erosion profiles. FIGURE 8 charts the measurements on center, mid and edge die showing the thickness profiles and variations. In general, the wafers showed identical profiles on the three die. Thickness variation was ~20Å within the structure. FIGURE 9 provides details full wafer maps for both NMOS and PMOS devices. The data collected on these structures was used to better understand the within wafer profiles and guide process optimization.

FIGURE 8. High resolution line scan profiles from center, mid and edge die on an SRAM structure.

FIGURE 8. High resolution line scan profiles from center, mid and edge die on an SRAM structure.

FIGURE 9. Full wafer maps of both NMOS and PMOS devices.

FIGURE 9. Full wafer maps of both NMOS and PMOS devices.

 

Finally, measurement repeatability and stability were evaluated. TABLE 1 summarizes the results of dynamic (wafer load/unload) repeatability testing performed on SRAM structures across nine sites on a test wafer. The standard deviation is < 0.5% at each site and < 0.2% for the wafer average. FIGURE 10 shows results of measurement stability over a 10-day period when measuring daily production monitor wafers.

TABLE 1

TABLE 1

FIGURE 10. Long term stability monitored on daily QC wafers.

FIGURE 10. Long term stability monitored on daily QC wafers.

Conclusion

PULSE technology is uniquely qualified
to provide the information needed
for tight process control for the High-K/
metal gate applications. Its small spot,
 non-contact, non-destructive nature
permits direct, in-line measurements
on product wafers. The measurements
provide accurate information to the process area on true thickness variations
that can be correlated with device 
performance. Excellent correlation
between PULSE, TEM and resistivity 
methods has validated the accuracy of the
technique. Direct PULSE measurements
on SRAM structures provide a means
of monitoring gate height that is clearly
superior to indirect measurements
using pad and line arrays, which are negatively affected by pattern dependent variations. In addition, the picosecond ultrasonic measurement system has demonstrated the repeatability and long term stability required for in-line metrology. Its capability has been proven for both pre-and post-CMP processes. Characterization of work function barrier layer measurement provides an additional benefit for the use of picosecond ultrasonic technology for HKMG process monitoring.

References

1. Bohr, M., Chau, R., Ghani, T. and K. Mistry, “The high k solution”, IEEE Spectrum, (10), 30-35 (2007).

2. Misra. V, Lucovsky, G., & Parsons G, “Issues in High-k Gate Stack Interfaces”, MRS Bull., 27 (3), 212–216 (2001).

3. Hoffman T. Y. “Integrating high-k /metal gates: gate-first or gate-last?”, Solid State Technology Review, (2010).

4. Hsien, Y.H., Hsu, H.K., Tsai, T.C., Lin, W., Huang, R.P., Chen C.H, Yang, C.L., Wu, J.Y., “Process development of high-k metal gate aluminum CMP at 28 nm technology node”, Microelectronic Engineering,92(4),19–23(2012).

5. Steigerwald, J. M., “Chemical mechanical polish: The enabling technology”, IEDM, 1-4 (2008).

6. Xu, K., Chen, Y., Iravani H., Wang Y., Swedek, B., Yu, M., Wang, Y., Tu, W., Xia, S., Karuppiah, L., “High k metal gate CMP challenges and solutions”, 218th ECS meeting, ECS (2010).

SEMATECH, the global consortium of semiconductor manufacturers, today announced the appointment of Satyavolu Papa Rao as Director of Process Technology. In this key role, Papa Rao will serve as the operational lead, overseeing the strategic development of SEMATECH’s manufacturing, process, materials and ESH-related activities.

SEMATECH’s Process Technology division addresses the capability gaps in current semiconductor manufacturing processes and identifies areas where research is needed to develop new processing technologies.

“SEMATECH is developing a comprehensive set of high-value activities that will be integrated with our core technology programs. Growth of the manufacturing effort is essential for future success,” said Ron Goldblatt, president and CEO, SEMATECH. “This latest hire brings additional expertise to SEMATECH, and, in turn, will raise the level of our manufacturing efforts, enhance our relationships with our partners, and further strengthen SEMATECH’s commitment to solving future manufacturing challenges.”

“We are fortunate to add someone with Pops’ wealth of expertise to lead our semiconductor process technology team which will help us in refining, growing, and expanding our integrated manufacturing activities at SEMATECH,” he added.

Papa Rao, who assumes his new role as director of Process Technology on May 21, brings more than 15 years of industry experience in process technology development. He joins SEMATECH from IBM Corporation, where he was a research staff member and manager of Advanced Films and Cleans Technologies for the Unit Process Development group. He previously held various technical positions at Texas Instruments.

Papa Rao holds a doctorate in materials science and engineering from the Massachusetts Institute of Technology and a bachelor of technology degree in Metallurgical Engineering from the Indian Institute of Technology, Madras. He holds over 35 U.S. patents and is the author of more than 36 publications.

The Semiconductor Industry Association (SIA) today announced that worldwide sales of semiconductors reached $78.47 billion during the first quarter of 2014, marking the industry’s highest-ever first quarter sales. Global sales reached $26.16 billion for the month of March 2014, an increase of 11.4 percent from March 2013 when sales were $23.48 billion and a slight uptick of 0.4 percent compared to last month’s total of $26.04 billion. Regionally, sales in the Americas increased by 16.1 percent compared to last March, and year-to-year sales increased across all regions. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market has demonstrated consistent momentum in recent months, and sales are well ahead of last year’s pace through the first quarter of 2014,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “Perhaps most impressively, sales in March increased across all regions and every semiconductor product category compared to last year, demonstrating the market’s broad and diverse strength.”

Regionally, year-to-year sales increased in the Americas (16.1 percent), Asia Pacific (12.9 percent), Europe (8 percent), and Japan (0.4 percent), marking the first time in more than three years that year-to-year sales increased across all regions. Sales were up compared to the previous month in Europe (3.9 percent), Asia Pacific (1.4 percent), and Japan (0.3 percent), but down slightly in the Americas (-4.3 percent).

“Although recent semiconductor sales are encouraging, one threat to the semiconductor market’s continued growth and America’s overall economic strength is the innovation deficit – the gap between needed and actual federal investments in research and higher education,” Toohey continued. “Policymakers should act swiftly to close the innovation deficit by committing to robust and sustained investments in basic scientific research and higher education.”

March 2014
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 5.32 5.09 -4.3%
Europe 2.96 3.07 3.9%
Japan 2.81 2.81 0.3%
Asia Pacific 14.96 15.18 1.4%
Total 26.04 26.16 0.4%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 4.39 5.09 16.1%
Europe 2.85 3.07 8.0%
Japan 2.80 2.81 0.4%
Asia Pacific 13.45 15.18 12.9%
Total 23.48 26.16 11.4%
Three-Month-Moving Average Sales
Market Oct/Nov/Dec Jan/Feb/Mar % Change
Americas 5.80 5.09 -12.2%
Europe 2.96 3.07 3.9%
Japan 2.93 2.81 -3.8%
Asia Pacific 14.96 15.18 1.4%
Total 26.65 26.16 -1.8%

 

By Debra Vogler, SEMI

Previous semiconductor technology generations developed more clearly defined “winners” in terms of process technologies and materials choices. As the industry goes below 14nm, however, it appears that there will be multiple technologies used along the way. For lithography, that includes the further extension of 193i, plus the inclusion of EUVL, directed self-assembly (DSA), maskless lithography (ML2), and more. For transistor scaling, it could be some combination of nonplanar device structures and non-silicon materials (e.g., III-V), but it could also mean that, depending on the application, a company might want to choose a nontraditional scaling path such as 3D integration.

Lithography: keeping all options open

Immersion lithography at 193nm is still very much alive — and while the industry works to ready EUVL for high-volume manufacturing (HVM), Nikon’s position has been to maintain the 193 infrastructure and keep improving 193 tools to support multiple patterning and other technologies that are coming into play. “It was premature to declare 193i dead,” according to Stephen Renwick, senior research scientist at Nikon Research Corporation of America. “It’s still very much alive and a viable option as we go into 10nm and 7nm (Figures 1, 2).” As part of its immersion lithography extension pipeline, the company’s model S622D is shipping now and is being used at 14nm, with end users looking to extend it to the 10nm logic node. “The S630D is coming soon and is intended to be used at 10nm and extended to the 7nm logic node,” said Renwick, who will present at the “Readiness of Advanced Lithography Technologies for HVM” session (part of the new Semiconductor Technology Symposium) at SEMICON West 2014 (www.semiconwest.org).

Figure 1

Figure 1. Lithography technology trends. Source: Nikon

 

Screen Shot 2014-04-28 at 7.16.37 PM

Figure 2. Options for different nodes. Source: Nikon

One next-generation lithography (NGL) technology that Nikon has been evaluating is directed self-assembly (DSA). It is the scanners that make the guide patterns used to guide the block copolymers that self-assemble, so the company was interested in anticipating what might be needed in terms of additional performance requirements on 193 immersion scanners (e.g., overlay, CD uniformity) to make the guide patterns. Rathsack, et al., (Adv. Litho. 2012, Proc. SPIE, #8323) have achieved 12.5nm lines/spaces using 100nm guide patterns, which are approximately the 7nm node requirements. According to Renwick, to meet these DSA requirements at 7nm, a 193i scanner needs an overlay ≤2nm and single-digit CDU — requirements the company can fulfill. The company’s S630D is already able to meet the requirements and the S622D is coming along, noted Renwick.

Also working to extend 193i lithography with complementary solutions such as DSA and maskless lithography (ML2) is CEA-Leti, with its IMAGINE (for ML2) and IDEAL (for DSA) programs. The IMAGINE Program is charged with developing and industrializing electron beam high-throughput maskless lithography developed by MAPPER Lithography. Members include: MAPPER, TSMC, STMicroelectronics, Nissan Chemical, TOK, JSR Micro, Sokudo, TEL, Mentor Graphics, and Aselta Nanographics. According to Serge Tedesco, lithography program manager at CEA-Leti, ML2 offers a production price reduction for low- and mid-volume applications. “This technique appears quite attractive for coping with the increasing difficulties relative to the patterning of critical levels, such as contact layers, and the cut level in the case of complementary lithography,” Tedesco told SEMI.

At the present time, the IMAGINE program’s pre-production Matrix 1.1 platform is making steady progress. The installation at Leti began in July 2013 and the first exposure is scheduled for June 2014. The Matrix 1.1 comprises 1300 x 49 beams to reach a throughput target of 1wph. The specifications on this pre-production platform are identical to the production version (i.e., 32nm L/S, 10nm overlay). To build up the infrastructure to support the platform, Leti has interfaced the tool with the Sokudo DUO track. Work is on-going with resist suppliers and the data base infrastructure for e-beam proximity correction (EPC) is being handled by Aselta — a Leti start-up. Additionally, Mentor Graphics and Mapper announced a partnership to support the Matrix data format.

The next phase of the pre-production IMAGINE program is getting the platform to 10wph (Matrix 10.1) using 13000 beams. The Matrix platform roadmap places the 10.1 phase starting at about Q4/14 and going until Q1/15. After that comes development of an HVM tool — the Matrix 10.10 — that will have 10 clustered 10wph/module modules for a throughput of 100wph (Figure 3).

Figure 3. IMAGINE roadmap. Source: CEA-Leti

Figure 3. IMAGINE roadmap. Source: CEA-Leti

Regarding Leti’s DSA activities, Tedesco reports that its IDEAL program is making progress on both the materials and process integration fronts. “Resolution, CD control and defectivity are in the range of what will be needed for implementation of the technology,” said Tedesco. He added that the addition of partners such as TOK, ASML, and Mentor Graphics will ensure the infrastructure will be ready. Tedesco will also present at the “Readiness of Advanced Lithography Technologies for HVM” session.

Also on the DSA front, another European project called PLACYD was launched earlier this year by Arkema, Leti, and 9 other European partners. The project will set up a dedicated materials pilot line at Arkema (in Lacq, France) to supply block copolymers for DSA lithography. The objective is to provide such materials that are precisely defined, with high purity, and that are highly reproducible on an industrial scale.

Regarding ML2 and DSA, Tedesco is rather upbeat about the future. “Complementary and cost-effective solutions, such as DSA and ML2 could help extend 193i much further than originally anticipated,” he said.

Scaling transistors: a matter of function

It may be less clear what will be sorted out for transistor scaling as the industry gets closer to the 5nm node. There are many choices that will need to be made just for materials, i.e., substrate, channel, and gate. Add in the different types of device architectures — FinFET, gate-all-around, and even unconventional choices such as tunnel FETs and nanowires — and you have a toss-up delimited by device application. An Chen, senior member of the technical staff at GLOBALFOUNDRIES and Chair of the ITRS Emerging Research Devices Working Group, told SEMI that there is no consensus on the device/material choices. Will building a consensus even make sense? It seems unlikely. “Companies may run into different challenges and reach different conclusions on the same technology,” said Chen. “The maturity level of technology development among different companies will also affect their opinions on technology options.” Adding to the mix is the fact that different applications require different device characteristics, so a particular company’s focus could affect its preferences on technology options, he observed. Chen will present at the “Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and Beyond” STS session at SEMICON West.

The plethora of directions and choices is not the only wrench in the works. “The increasing cost of R&D and decreasing return in the semiconductor industry do not appear to be sustainable,” stated Chen. Still, he doesn’t think that development will slow down because of funding challenges, though he does believe that fewer and fewer companies will be able to afford the high cost of R&D for scaling. Indeed, even some consortia are collaborating with each other and more companies may start looking for alternatives, he observed. “There is a lot of research on beyond-CMOS technologies, but they seem to be more suitable to augment CMOS rather than to replace CMOS. And low power has been a common feature of many beyond-CMOS devices, which could become increasingly useful because of applications driven more and more by portability and mobility.” Chen further observed that functional diversification or enhancement — e.g., 3D integration — may enable better system functionalities without relying on scaling.

The term “functional diversification” has been used by ITRS participants when they started to look into the “More than Moore” (MtM) directions the industry could take, explained Chen.  “Instead of being driven by scaling (or nodes), MtM focuses more on functionalities that may be enabled by technologies beyond digital computing,” said Chen. Examples of such functionalities are analog, sensing, and energy harvesting.

Regarding funding sources and possible disruptive technologies, Chen noted that a few years ago, the industry was talking about what technology can be found to extend scaling substantially beyond extreme CMOS. Research funded by programs such as DARPA, SRC, etc., might not be the most appropriate uses for such technologies. “Many of them may be better used — together with a CMOS platform — to create new functions or improve efficiency,” said Chen. But such programs might not necessarily help with physical scaling.

Hear from the experts — live!   This year, SEMI announced the new Semiconductor Technology Symposium (STS), to be held July 8-10 as part of the SEMICON West 2014 technical and business program agenda. The new paid program addresses the most important and critical issues facing the future of semiconductor manufacturing in a new and more technical conference format. More information and pricing for the STS sessions available here: www.semiconwest.org/sts.

Learn more about the new Semiconductor Technology Symposium sessions and other front-end programs at SEMICON West 2014 (www.semiconwest.org).

Free registration for SEMICON West is available — includes free access to the exhibition hall plus all TechXPOT sessions, keynotes and executive panels.  Register for SEMICON West 2014: www.semiconwest.org/register.

SEMATECH, the global consortium of semiconductor manufacturers, today announced the appointment of Edward Barth as director of Strategic Growth Initiatives. Dr. Barth will join SEMATECH’s executive management team and will be responsible for cultivating effective alliance relationships and driving key strategic partnerships that align with the company’s core business objectives and long-term value creation and growth.

“As we continue to refine and implement our strategies, which are designed to maximize both SEMATECH’s partnership opportunities and technical operations, it is very important for us to have the right people on board to enhance our capabilities and accelerate our aggressive goals,” said Ron Goldblatt, SEMATECH’s president and CEO. “Ed’s knowledge of the semiconductor industry, with specific experience in R&D strategy, coupled with his strong track record in coordinating and executing complex agreement structures provides us with the experience needed to strategically manage the direction and growth of SEMATECH’s very valuable partnerships and alliances.”

Barth brings more than 20 years’ industry experience, most recently in leading the development of technology alliances and research collaborations, and negotiating complex deals involving intellectual property licensing. Previously, he held various engineering and management positions with IBM Corporation and Digital Equipment Corporation, where he led development of advanced copper and low-k interconnect technologies. In his new role, Barth will focus on strengthening existing relationships, building new alliances, and ensuring their value and effectiveness toward SEMATECH’s growth.

Prior to joining SEMATECH, Barth served as a business development executive in the Technology Alliances and Intellectual Property group at IBM Corporation, where he played a leadership role in driving key partnership growth of the IBM-led semiconductor development alliance. During that time, he fostered relationships with a broad network of domestic and international technology clients and was the primary architect of the contract structure that has been used by the alliance since 2007.

Barth received his bachelor’s and master’s degrees in Metallurgical Engineering from Columbia University, and later received a doctorate in Materials Science from The University of Texas at Austin. Barth served as a postdoctoral research fellow in Materials Science at Harvard University, where he led industry-funded research into the deformation behavior of amorphous metals and alloys. He holds six U.S. patents and is the author of more than 15 peer-reviewed publications.

By Vidhya Ramachandran

The recent years have seen considerable contention in the semiconductor industry on whether Moore’s Law is alive and well [1], [2], [3]. The impact of on-chip interconnect cost on advanced node technology products, in particular, has generated much discussion [4] and, some would say, discontent [5]. Beyond 28nm, BEoL cost and complexity projections (Figure 1) show an explosion and at the upcoming 10nm node, on-chip interconnect costs are projected to exceed 50 percent of the SoC cost [4]. Technologists from multiple functions in the semiconductor industry have to come together to address this issue, as will be evident at the Workshop “Manufacturing of Interconnect Technologies: Where Are We Now And Where Do We Go From Here?” to be held prior to the International Interconnect Technology and Advanced Metallization Conference (IITC/AMC) on May 20 in San Jose.

Figure 1. From [4], BEOL cost and mask count estimates for advanced nodes. Note the sharp rise beyond 28nm, driven by multiple patterning.

Figure 1. From [4], BEOL cost and mask count estimates for advanced nodes. Note the sharp rise beyond 28nm, driven by multiple patterning.

Particularly challenging at the 10nm and 7nm nodes is lithography. The incumbent is 193i technology, which is now being used to print significantly sub-wavelength features [1]. At the 20nm node this has been accomplished by double patterning, but approaching 7nm this will require triple patterning, a new wavelength (e.g. EUV), or some other disruptive technology. This, in addition to a steep rise in the number of metal layers in order to route a higher density of transistors and more complex circuitry, influence mask count, process complexity and cycle-time, directly hitting at the heart of cost and yield. Photolithography researchers from GLOBALFOUNDRIES will review advancements in lithography that enable solutions for these issues at the IITC/AMC Workshop.

Many new materials are being introduced to meet RC requirements, such as lower K insulators and thinner and self-formed metal barrier layers [7]. These implementations are not stand-alone changes, but come hand-in-hand with their respective versions of etch, CMP, cleans and so on, moving into new process condition regimes [8], [9]. While these modules pose challenges in development, in manufacturing, where thousands of wafers could be at risk from a single process going out of control, new materials can be particularly problematic. These challenges are driving development of innovations in the methodology for introduction of new materials and processes, process control and yield management for advanced technologies at several industry leaders. New defects and failure mechanisms are being discovered and solved; new metrology methods are enabling more robust process control; and pervasive implementation of automated process control (APC) prevents process excursions.

As we are well-aware, aspects of semiconductor manufacturing that could act independently in the past such as design and process now have to work closer together throughout the entire life-cycle of a product, from conception to manufacturing ramp [11]. We increasingly find that successful manufacturing is driven by “yield-aware” design, with robust follow-up between designers and manufacturers during the fabrication phase [12]. Designers from ARM highlight the interconnect-related challenges of implementing their high performance cores in SoCs at 16 nm and beyond.

The transition to 450mm wafers is often touted as a significant cost breakthrough; however any significant cost savings from the transition to 450mm wafers will be strongly dependent on manufacturability readiness [13]. Reports from researchers at the Global 450mm Consortium (G450C) on the status of this readiness underscore joint industry initiatives, standards and equipment supplier engagement.

With the acute focus on challenges in interconnect manufacturing with meeting Moore’s Law projections, interconnect technologists have their work cut out for them. However, the upside is that there is plenty of opportunity for innovation across the board. Some of this will be in evidence at the Panel Discussion to follow the IITC/AMC Workshop, where industry leaders will share their perspectives on how the industry will meet these challenges while remaining cost competitive. As we know, semiconductor engineers are a resourceful lot, and we look forward to all the exciting developments in store for us!

Vidhya Ramachandran is an Advanced Interconnect Technology Engineer at Qualcomm Technologies, Inc. and a co-organizer of the IITC/AMC 2014 Workshop titled ““Manufacturing of Interconnect Technologies: Where Are We Now And Where Do We Go From Here?”. Deepak Sekar, a Director at Rambus Labs, and General Co-Chair of IITC/AMC 2014 also contributed to the article.

References:

[1]    http://www.eetimes.com/author.asp?doc_id=1321536

[2]    http://www.eetimes.com/document.asp?doc_id=1263256

[3]    http://www.eetimes.com/author.asp?section_id=36&doc_id=1321784&page_number=1

[4]    “Smart Mobile SoCs Driving the Semiconductor Industry: Technology Trend, Challenges and Opportunities”, Geoffrey Yeap, IEDM 2013.

[5]    http://semiengineering.com/executive-viewpoint-qualcomm-on-process-technology/

[6]    “Scope and Limit of Lithography to the End of Moore’s Law”, Burn Lin, ISPD 2012.

[7]    ITRS Interconnect Workgroup 2012 Winter Update

[8]    http://www.evaluationengineering.com/news/imec-addresses-3-d-ics-interconnects-cryogenic-etching-and-solar-cells.php

[9]    “Materials Challenges in Planarization and Interconnect Technologies”, Mansour Moinpur, International Conference on Planarization/CMP Technology 2007

[10] http://www.techdesignforums.com/practice/technique/euv-options-sub-20nm/

[11] http://edn.com/design/integrated-circuit-design/4412868/Design-for-manufacturing-and-yield

[12] http://www.semiwiki.com/forum/content/1054-tsmc-28nm-yield.html

[13] http://electroiq.com/blog/2013/06/450mm-_-it_s-bigger-than-you-think/