Category Archives: Metrology

North America-based manufacturers of semiconductor equipment posted $1.29 billion in orders worldwide in February 2014 (three-month average basis) and a book-to-bill ratio of 1.00, according to the February EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.00 means that $100 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in February 2014 was $1.29 billion. The bookings figure is 0.7 percent higher than the final January 2014 level of $1.28 billion, and is 20.1 percent higher than the February 2013 order level of $1.07 billion.

The three-month average of worldwide billings in February 2014 was $1.29 billion. The billings figure is 4.5 percent higher than the final January 2014 level of $1.23 billion, and is 32.2 percent higher than the February 2013 billings level of $974.7 million.

“Equipment bookings and billings continue along a steady trend in the first quarter,” said Denny McGuirk, president and CEO of SEMI.  “The book-to-bill ratio remains at or above parity for the fifth consecutive month, and the booking and billing values remain well above the figures reported one year ago.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
September 2013

 

1,020.9

992.8

0.97
October 2013

 

1,071.0

1,124.5

1.05
November 2013

 

1,113.9

1,238.0

1.11
December 2013

1,349.7

1,380.8

1.02
January 2014 (final)

1,233.2

1,280.3

1.04
February 2014 (prelim)

1,288.6

1,288.9

1.00

Source: SEMI, March 2014

Related news:

 North American semiconductor equipment industry posts January 2014 book-to-bill ratio of 1.04

Book-to-bill ratio continues to improve

Dr. Tzu-Yin Chiu, Chief Executive Officer & Executive Director of SMIC presented the SEMICON China 2014 opening keynote yesterday and was given a SEMI Outstanding EHS Achievement Award.

Dr. Tzu-Yin Chiu’s keynote address, entitled “Building China’s Advanced and Value-added IC Ecosystem by Innovation, Quality, and Services,” introduced SMIC’s significant progress in 2013, showed the corporation’s development results of advanced, mature and value-added technologies and products, and shared the success stories of SMIC building China’s IC Ecosystem with customers.

“I am delighted to present the opening keynote at SEMICON China and am honored to receive SEMI’s Outstanding EHS Achievement Award for SMIC. This award is of great significance to us as the industry recognizes SMIC’s huge efforts in EHS,” said Dr. Chiu, “2013 was a year with outstanding development and breakthrough for SMIC. Our sales revenue reached a new record high, and technology research and development had remarkable achievements with the successful launch of 28nm advanced technology process. Going forward in 2014, SMIC will continue capturing growth opportunities and work with our customers to develop the IC market and the whole semiconductor industry.”

In addition, Mr. William Yan, SMIC’s ESH Director, will give a presentation on “Perspectives from a Fab Owner” in EHS seminar on March 19th. Dr. David Shih, SMIC’s Marketing Director, will also present “Serving Advanced and Value-added Technology Platforms for Your Vision” on March 20th at the show’s IC Design and Technology Forum.

Scientists from the Institut Català de Nanociència i Nanotecnologia (Catalan Institute for Nanoscience and Nanotechnology – ICN2) announced pioneering software for line pattern image analysis at the SPIE Advanced Lithography (San Jose, CA; 23 – 27 February 2014). The presented methodology is a unique tool developed to address the gap existent in dimensional metrology of sub-10nm line patterns. This is a methodology to quantify the critical dimensions and defect density of line arrays in regimes where optical inspection cannot reach. The software has been developed by the ICN2 Phononic and Photonic Nanostructures Group, led by ICREA Professor C. M. Sotomayor Torres, in collaboration with University College Cork (Ireland), led by Professor A. Amann.

Directed self-assembly (DSA) of block copolymers (BCPs), a method already compatible with existing electronic technologies, has gained the attention of the lithography community as a most promising avenue to advance miniaturization. First-generation DSA is on the verge of entering high-volume manufacturing by successfully increasing sub-20nm contact hole resolution in a cost-effective manner. DSA for reproducible sub-10nm pitch sizes is a hot research topic in Asia, Europe, and the Americas.

One of the main challenges for R&D, material suppliers, or manufacturers is specialized metrology for DSA-based lithography. It is here where the method invented by ICN2/UCC is expected to bring decisive advantages in the characterization of nanometer line patterns, one of the key elements in circuit manufacturing. The presented methodology is user-friendly and customizable software successfully addressing this issue, complimentary to conventional optical inspection tools.

This R&D project is in validation stage and is available for development in joint ventures with partners interested in materials, metrology, manufacturing, and applications involving DSA.

The 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014) will be held May 19-21 in Saratoga Springs, New York. The conference will feature 37 hours of technical presentations and 90+ speakers covering all aspects of advanced semiconductor manufacturing. This year’s event features a panel discussion on “25 Years of Semiconductor Manufacturing: Accomplishments, Current Challenges, Future Directions — From the Internet to the Internet of Things,” with panelists from SEMATECH, Rochester Institute of Technology, GLOBALFOUNDRIES, Qualcomm, and Applied Materials.  A tutorial on directed self-assembly taught by Michael A. Guillorn, Ph.D., from the Nanofabrication and Electron Beam Lithography department at the IBM T.J. Watson Research Center, and a second tutorial, on Silicon Photonics, taught by Dr. Haisheng Rong, Intel Corporation.

Celebrating 25 years of manufacturing excellence in 2014, the SEMI Advanced Semiconductor Manufacturing Conference continues to fill a critical need in our industry.  The conference provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.  The 2014 conference is co-chaired by Israel Ne’eman, Applied Materials, and Oliver Patterson, IBM Microelectronics.  ASMC 2014 offers keynote talks by Dr. Been-Jon Woo from TSMC, and Dean Freeman from Gartner.

The topical areas ASMC 2014 speakers and poster presenters will address include:

  • 3D/TSV
  • Advanced Equipment and Materials
  • Advanced Metrology
  • Advanced Patterning/Design for Manufacturing
  • Advanced Process Control (APC)
  • Contamination Free Manufacturing (CFM)
  • Data and Yield Management; Defect Inspection
  • Equipment Reliability and Productivity Enhancement
  • Factory Optimization
  • Yield Enhancement

ASMC also holds an interactive poster session and reception, which provides an ideal opportunity for networking between authors and conference attendees. During this session, participants can engage authors in in-depth discussion of a wide range of issues.

ASMC 2014 is presented by SEMI with technical sponsors: Institute of Electrical & Electronics Engineers (IEEE), IEEE Electron Devices Society (EDS), and IEEE Components, Packaging and Manufacturing Technology Society (CPMT).  Corporate sponsors include: Applied Materials; ASML; ChemTrace; CNW Courier Network; Edwards Vacuum; Greene,Tweed;  KLA-Tencor; Lam Research; Marcy NanoCenter; NY Loves Nanotech; and Saratoga Convention and Tourism Bureau.

Registration for ASMC 2014 is available at www.semi.org/asmc2014.  For more information contact Margaret Kindling at [email protected] or phone 1.202.393.5552. Qualified members of the media should contact Deborah Geiger (SEMI Public Relations) at [email protected] for media registration information.

SEMI, the global industry association for companies that supply manufacturing technology and materials to the world’s chip makers, today reported that worldwide sales of semiconductor manufacturing equipment totaled $31.58 billion in 2013, representing a year-over-year decrease of 14 percent. The data is available in the Worldwide Semiconductor Equipment Market Statistics (SEMS) Report, now available from SEMI.

Compiled from data submitted by members of SEMI and the Semiconductor Equipment Association of Japan (SEAJ), the Worldwide SEMS Report is a summary of the monthly billings and bookings figures for the global semiconductor equipment industry. The report, which includes data for seven major semiconductor producing regions and 24 product categories, shows worldwide billings totaled $31.58 billion in 2013, compared to $36.93 billion in sales posted in 2012. Categories cover wafer processing, assembly and packaging, test, and other front-end equipment. Other front-end includes mask/reticle manufacturing, wafer manufacturing, and fab facilities equipment.

Spending rates declined for all the regions tracked in the WWSEMS report, except for China and Taiwan. For the second year in a row Taiwan remained the region with the highest amount of spending with $10.57 billion in equipment sales. The North American market surpassed South Korea to claim the second place with $5.26 billion in sales; South Korea fell to the third position with a regional decrease of 41 percent.

The global other front end equipment segment decreased 34 percent; the assembly and packaging segment decreased 26 percent;  total test equipment sales decreased 24 percent; and the wafer processing equipment market segment decreased 11 percent.

Semiconductor Capital Equipment Market by World Region (2012-2013)

(Dollar in U.S. billions; Percentage Year-over-Year)

 

2013

2012

% Change
Taiwan

10.57

9.53

11%
North America

5.26

8.15

-36%
South Korea

5.13

8.67

-41%
Japan

3.38

3.42

-1%
China

3.27

2.50

30%
Rest of World

2.07

2.10

-2%
Europe

1.91

2.55

-25%
Total 31.58 36.93

-14%

 

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market.

Cadence Design Systems, Inc. announced today that GLOBALFOUNDRIES certified the Cadence Physical Verification System (PVS) for custom/analog, digital and mixed-signal design physical signoff for 65nm to 14nm FinFET process technologies. The certification covers Cadence-qualified PVS rule decks for physical verification used in Cadence Virtuoso Integrated Physical Verification System, Cadence Encounter Digital Implementation System and full-chip signoff. Certified Cadence PVS rule decks are essential for mutual customers to fully leverage in-design physical verification in Cadence analog and digital flows, and to complete full-chip physical signoff.

“As innovators move to these smaller geometries, they are looking for tools that can keep up with their ever-changing needs,” said Dr. Richard Trihy, Director of Design Methodology, Design Solutions, GLOBALFOUNDRIES.  “By ensuring Cadence’s Physical Verification System support for 65nm to 14nm technology nodes, our mutual customers can now benefit from the in-design physical verification in Virtuoso and Encounter flows.”

Customers can now standardize on PVS for in-design signoff via the seamless integration with Cadence Virtuoso custom IC design platform and Encounter Digital Implementation System, and for full-chip signoff. In-design PVS enables customers to instantaneously detect errors, generate fixing guidelines, incrementally verify the fix, and prevent any new errors while in either the Virtuoso or Encounter platforms. The Virtuoso Integrated Physical Verification System integrates signoff PVS technology into Virtuoso Layout Suite and verifies the design as it is drawn in an interactive “real-time” mode. Timing-aware PVS incremental metal fill in Encounter Digital Implementation System dramatically reduces signoff ECO (engineering change order) turnaround time compared to traditional flows. The certified PVS physical signoff ensures that designs conform to complex rules and matches the desired chip functionality, without compromising on accuracy.

Related news: High cost per wafer, long design cycles may delay 20nm and beyond

“Physical signoff rules and checks continue to grow exponentially due to the growing lithography equipment gap in manufacturing. Through our close collaboration with GLOBALFOUNDRIES and our customers, we continue to deliver the technologies needed to design and sign off complex designs at today’s most advanced geometries,” said Dr. Anirudh Devgan, senior vice president, Digital and Signoff Group at Cadence. “Through the certification of our PVS rule decks for physical signoff, our customers can leverage the best in-design integration with Cadence platforms to enable the fastest time to tapeout.”

Semtech Corporation, a supplier of analog and mixed-signal semiconductors, today announced the appointment of Charles B. Ammann as Executive Vice President, General Counsel and Corporate Secretary. Mr. Ammann succeeds Randall H. Holliday, who has announced his retirement.

“I am pleased to have a seasoned executive and legal professional of Chuck’s caliber join Semtech’s management team. His business acumen and unique breadth of legal expertise are a great complement for Semtech’s diverse business and growth agenda as we continue on our journey to become a billion dollar company,” said Mohan Maheswaran, President and Chief Executive Officer of Semtech Corporation. Maheswaran added, “I also would like to thank Randy for his 5 years of outstanding service at Semtech. During this time, Randy built an exceptional legal organization and helped transform our company to the multinational business it is today. We wish Randy the best in his retirement.”

Mr. Ammann comes to Semtech with more than 30 years of corporate and legal experience, most recently as the Executive Vice President, General Counsel and Secretary of United Online, Inc. Before joining United Online, Inc., he held senior executive positions and served as the General Counsel at TV Guide, Inc., United Video Satellite Group and Flint Industries. Mr. Ammann also served as a Partner for the prestigious law firm Gable & Gotwals.

Mr. Ammann received his B.B.A. from the University of Notre Dame with a double major in Finance and Management and was the recipient of the prestigious Hamilton Award for Management. He obtained his J.D. from the University of Oklahoma where he served as Editor of the Oklahoma Law Review, and his M.B.A. from The University of Tulsa.

The release today of the SEMI World Fab Forecast update reveals a 20 to 30 percent projected increase in semiconductor fab equipment spending in 2014. The uptick to 30 percent depends on specific fab projects in the Europe/Mideast and Asia regions, as detailed in the report. Figure 1 shows Total Fab Equipment Spending versus Installed Capacity without Discretes. For 2014, the report identified over 190 fab projects in 2014 spending on construction and/or equipment and over such 250 projects in 2015 (including Discretes, LED, Analog and Logic fabs).

fab graph

According to the SEMI data, double-digit fab equipment spending growth will occur in almost all industry segments.  The segment showing the largest increase is expected to be MPU, followed by Memory.  Analog, Logic and MEMS will share third place with about 30 percent growth each — off of a small spending base in 2013.  The Foundry segment spending is expected to grow by 15 percent.

The SEMI World Fab Forecast report shows an increase in DRAM related projects equipping, thus an increase in DRAM related equipment spending from about 7 percent growth in 2013 to 30 percent in 2014. Overall DRAM installed capacity is expected to remain flat (0 percent) in 2014, following a contraction in 2013.

Equipment spending is also expected to stabilize for both the Opto and the LED fab segments, from -16 percent spending declines in 2013 to -1 percent in 2014.  Equipment spending in the LED segment will decline -9 percent in 2014 following the -21 percent decline in 2013.  Construction spending for all Opto/LED facilities will increase by over 60 percent in 2014.  These investments will increase installed capacity for LED by 12 percent in 2014 and about 14 percent in 2015.

Using a bottom up approach, SEMI closely monitors the installed capacity of more 1,100 facilities.  Across the entire industry, installed capacity (without Discretes) grew by only 2 percent in 2013; this is expected to creep up to 3 percent growth in 2014 and in the 3-5 percent range in 2015.

The SEMI World Fab Forecast tracks over 190 fab projects in 2014 that are spending for construction projects and equipping facilities and over 250 such projects in 2015, including Discretes, LED, Analog and Logic fabs.  The report details that in 2013 seven new fabs and four R&D/Pilots facilities began construction. In 2014, six new fabs and one R&D fab are forecasted (with various probabilities) to begin construction.  Robust growth presents itself differently across segments of the industry; learn more about SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase

The SEMI World Fab Forecast lists over 1,160 facilities.  There are 56 future facilities with various probabilities which have started or will start volume production in 2014 or later.  The report lists major investments (construction projects and equipping) in 196 facilities and lines in 2014, and a large number in 2015. Since the last fab database publication at the end November 2013, the SEMI has made 282 updates to 253 facilities (including over 250 Opto/LED fabs) in the database. There were 17 facilities added and 10 facilities closed.

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter. These tools are invaluable for understanding how the semiconductor manufacturing will look in 2013 and 2014, and learning more about capex for construction projects, fab equipping, technology levels, and products.

Samsung Electronics, Co., Ltd. today announced that it has expanded its 28nm technology offerings with the addition of RF capabilities. As the Internet of Things quickly becomes a reality, Samsung’s foundry business offers chip designers the ability to integrate advanced RF functionality into their designs, making connectivity applications such as the connected home appliances, auto infotainment systems and heating/cooling systems possible.

“With only a handful of companies offering advanced process technology, the options to manufacture RF capabilities into chip designs are greatly reduced,” said Shawn Han, vice president of Foundry Marketing, Samsung Electronics. “As we enter the Internet of Things era, smaller, power-efficient RF solutions provide the critical functionality for the SoC solution as smart connected devices becomes more prevalent. Samsung Foundry is collaborating with our ecosystem partners and customers to provide the most advanced, low cost, lowest power RF technology possible.”

Samsung’s foundry business has already released its 28RF process design kit (PDK) and verification method to several customers, which has been proven by simulation and silicon results in real design. Samsung’s 28RF process is built on top of the high-volume manufacturing proven 28LPP HKMG process. Silicon results have shown 280GHz of Ft and 400GHz of Fmax with normal condition.

Through the collaboration with EDA partners, 28RF PDK includes design manual, accurate SPICE models, DRC/LVS, PEX and ESD decks, along with RF specific module verification and extraction rules. Samsung Foundry will start mass production of the 28RF process technology in early 2015.

Samsung is currently manufacturing foundry customers’ 28nm designs on its 28LPS (pSION), 28LPP (HKMG) and 28LPH (HKMG) process nodes. Multiple customer designs have been silicon-validated, and many more products are being manufactured at Samsung’s logic fabs, the S1 Line and S2 Line in Korea and USA, respectively.

The Semiconductor Industry Association this week presented its University Research Award – in consultation with Semiconductor Research Corporation (SRC) – to University of Minnesota professor Sachin Sapatnekar in recognition of his outstanding contributions to semiconductor research.

“We are pleased to recognize Dr. Sapatnekar for his trailblazing work in the field of semiconductor research,” said Dr. John E. Kelly III, IBM senior vice president, director of IBM Research, and 2014 SIA chairman. “Research is critical to sustaining the pipeline of discoveries that drive growth in the semiconductor industry and our economy. We commend Dr. Sapatnekar for his outstanding achievements.”

SIA

Dr. Sapatnekar holds the Distinguished McKnight University Professorship and the Robert and Marjorie Henle Chair in Electrical and Computer Engineering at the University of Minnesota. He was chosen for the award because of his work in developing computer-aided techniques for the analysis and optimization of integrated circuits, with his most recent work covering CMOS technologies as well as spintronics. Specifically, Professor Sapatnekar’s research has made significant impact in verifying and optimizing the power delivery networks of central processing units (CPUs) and other system on chips (SoCs). Analysis techniques developed by Professor Sapatnekar and his research group have dramatically advanced this capability in the design community.

He has authored nine books and numerous papers in this area and has received six conference Best Paper Awards and a Best Poster Award, as well as the ICCAD Ten-Year Retrospective Most Influential Paper Award, an award that recognizes a paper that has had a significant impact ten years after its publication.

“Our mission at SRC is to seed innovation and help provide the people and ideas to keep the U.S. semiconductor industry competitive, and Dr. Sapatnekar is an ideal example of this collective effort,” said SRC President Larry Sumney. “We salute Dr. Sapatnekar for the role he has played in our university research engine that has made the U.S. the cradle of discovery and technology development.”

Dr. Sapatnekar has served as the Editor-in-Chief of the IEEE Transactions on Computer-Aided Design and as General Chair for the ACM/IEEE Design Automation Conference, the two top publication venues in his research area, as well as leadership roles (General Chair and/or Technical Program Chair) in the ACM International Symposium on Physical Design, the IEEE/ACM Tau Workshop, and the International Conference on VLSI Design. He was conferred with a Fulbright award as a Senior Researcher in Spain in the Fall of 2013, and held the D.J. Gandhi Visiting Professorship at IIT Bombay in early 2014. He has received the NSF Career Award and the Semiconductor Research Corporation Technical Excellence Award, and he is a Fellow of the IEEE.