Rich Rogoff, Lithography Systems Group, Rudolph Technologies, Inc., Wilmington, MA

Moving from round wafers to rectangular panels saves corner space, delivering a roughly 10% improvement in surface utilization.

We’ve been doing it for years‒square die on round wafers. As the old adage suggests, we can make it work, but it is not always pretty. Now, as advanced packaging processes continue to develop‒often adopting and adapting processes and equipment from front-end manufacturing‒we need to be sure that we do not needlessly carry over baggage that impedes the optimization of these processes for their new applications. Front-end processes are designed to work on wafers, which are necessarily round and difficult to make larger. In the early days of advanced packaging, these wafer-level processes were extended to the back-end. Fan-in wafer-level chip-scale packaging (WLCSP) and wafer bumping are two prominent examples. However, as advanced packaging processes evolve further into the 2.5D and 3D space, opportunities present themselves to move away from round wafers and onto larger, square or rectangular substrates. Specifically, the manufacturing of fan-out packages on re-constituted substrates populated with KGD (known good die) and the use of high density interposer substrates for so-called 2.5D integration of advanced multi-die packages are experiencing above average growth. For these applications, the substrates can be rectangular and large. In fact, whole industries already exist, such as flat panel displays and solar panels, which use similar manufacturing processes on large rectangular substrates.

In front-end photolithography processes, where square die first met round wafers, there is an inherent inefficiency near the wafer’s edge, where squeezing as many die as possible onto the wafer inevitably results in part of the exposure field falling uselessly in the exclusion zone or off the wafer entirely. With an appropriately-sized rectangular substrate the rectangular pattern from the mask could fit perfectly, ultimately increasing the average number of die per exposure and thereby, the throughput of the exposure process. Likewise, using a larger substrate also increases throughput by reducing the nonproductive time spent exchanging substrates. Moreover, the same considerations that have historically driven increases in wafer size should also apply to non-round, non-wafer substrates, potentially providing substantial gains from using large panels throughout the manufacturing process. The flat panel display industry has increased its panel sizes over the years from 400 mm x 500 mm (Gen 2) to 2400mm x 2800mm (Gen 9) and beyond.

In an effort to understand the potential economic benefits, we constructed a model to compare the throughput of a 650 mm X 550 mm panel-based lithography process with a 300 mm wafer-based lithography process. The model considered 8 mm square die with 100 µm streets and a 5 mm wafer edge exclusion. We looked at two different mask (reticle) configurations containing 48 die (8 X 6) and 49 die (7 X 7) that could be exposed using the 84 mm diameter field of the 2x reduction JetStep™ Panel Lithography System (Rudolph Technologies). Both mask configurations resulted in 947 die per wafer. Since the square exposure field (7 X 7) required only 23 exposures, 6 less than the 29 exposures required by the rectangular field (8 X 6), all subsequent comparisons use the square field. The panel required 120 exposures resulting in 5214 die. It should be noted that either exposure field configuration was implemented on a standard 6-inch square, .25-inch thick reticle.

The most obvious advantage in the panel process accrues from the more than 5X greater number of substrate exchanges required by the wafer process, resulting primarily from the larger size of the panel substrate. Less obvious, but also important, are two different “square peg in a round hole” effects. The first is the decrease in the number of exposures required that results from the better fit of the rectangular field and the rectangular panel. The second is the increase in surface utilization that results from the better fit between the rectangular die and the rectangular substrate: 947 8 mm die cover 86% of the surface of a 300 mm wafer, whereas 5214 8mm die fill 94% of the surface of a 650 mm X 550 mm panel. A potential disadvantage of the panel process is the requirement for more alignment because of the increased substrate size.

For a more precise comparison, we calculated throughput in die per hour, assuming each wafer exchange took 15 seconds (including WEP) and each panel exchange took 13 seconds. FIGURE 1 compares the results for 8 mm X 8 mm die, including evaluation at two different doses (600 mj and 800 mj) and four different numbers of alignment points (4, 9, 16, and 18 points). In all cases, the panel process demonstrated approximately 2X (die per hour) throughput advantage over the wafer process. Predictably, increasing the dosage or the number of alignment points reduced the throughput for both wafer and panel processes. The decrease in throughput associated with increase in number of alignment points had an impact, for example, going from 9 to 16 points at the 600 mj dose reduced throughput by 8.8%.

Next, we estimated the cost-of-ownership for wafer and panel lithography processes, comparing three different wafer exposure systems (1X stepper, Rudolph 2X JetStep System for wafers, and Rudolph 2X JetStep System for panels). Table 1 shows the parameters used for the comparison. FIGURE 2 shows the relative cost per 100 die calculated for 8 mm X 8 mm die using 9 alignment points at 600 mj and 800 mj doses. At the 600 mj dose, cost per die decreased by approximately 18% for the JetStep wafer system and nearly 40% for the JetStep panel system, when compared to the 1X stepper. Similarly, at the 800 mj dose, cost per die decreased approximately 13% and 35%. We saw estimated cost savings of similar magnitude for smaller (3 mm X 3 mm) and larger (16 mm X 16 mm) die.

Summary

To summarize, moving from round wafers to rectangular panels (“panel-ization”) saves corner space, delivering a roughly 10% improvement in surface utilization. The larger size of the substrate and the improved fit between the mask and substrate reduce the transfer overhead by a factor of 5. The potential reduction in throughput resulting from an increase in the number of alignment points is more than offset by the improvements in throughput. Compared to a 1X stepper on wafers, panel-based processes can reduce lithography cost per die by as much as 40%.

Clearly, there are many aspects of “panel-ization” that must be addressed before these processes gain broad acceptance. It is worth noting that panel lithography is not new. It is widely used in related industries, such as the manufacturing of flat panel displays and photovoltaic solar panels. The JetStep Panel System is built on technology that has over 40 lithography systems currently installed in these and similar applications. As this analysis demonstrates, the potential economic benefits of panel-based lithography are significant. The model discussed here evaluates relatively modest sized panels. Larger panels may offer even greater benefits. Clearly, the transition to panel-based processes for advanced packaging applications bears serious consideration.

Semiconductor Manufacturing International Corporation, China’s largest and most advanced semiconductor foundry, announced today that its 28nm technology has been process frozen and the company has successfully entered Multi Project Wafer (MPW) stage to support customer’s requirements on both 28nm PolySiON (PS) and 28nm high-k dielectrics metal gate (HKMG) processes. Over 100 IPs from multiple third party IP partners as well as SMIC’s internal IP team are prepared to serve various projects from worldwide design houses that have been showing interest in SMIC 28nm processes.

28nm process technologies primarily target mobile computing and consumer electronics related applications, such as Smartphone, Tablets, TV, Set-top Boxes and networking. It provides customers high performance application processors, cellular baseband, wireless connectivity etc. According to IHS’ forecasts, the pure-play foundry revenue potential for 28nm will continue to rise with a CAGR of 19.4% from 2012 to 2017.

“I am pleased to announce the successful 28nm process milestone, which enables SMIC to better position itself in engaging and serving mobile computing related customers,” said Dr. Tzu-Yin Chiu, Chief Executive Officer & Executive Director of SMIC. “As the first foundry in mainland China to offer 28nm process technologies, this significant milestone demonstrates SMIC’s continuous growing capabilities in offering leading foundry technologies to worldwide IC designers.”

“The first SMIC 28nm MPW shuttle included both 28PS and 28HKMG related customer products for verification, which was already launched at the end of 2013 as planned,” said Dr. Shiuh-Wuu Lee, Executive Vice President of Technology Development of SMIC. “By taking more MPW shuttles in 2014, we will continue to take more positive steps to strengthen and diversify our technology offerings and meet customers’ growing demands on both advanced and differentiated technologies.”

At the SEMI Industry Strategy Symposium Europe (ISS Europe 2014) on February 23-25 in Salzburg, semiconductor industry executives will examine the conditions required to achieve the EU’s 10/100/20 strategy — 20 percent market share of global semiconductor manufacturing by 2020.  Presenters from ASML, ASMI, Deutsche Bank, GlobalFoundries, Infineon, Nomura Research, NXP, STM, and more will lead a discussion of the strategic measures needed to strengthen Europe’s competitiveness and sustainability and determine the boundary conditions to achieve the EC’s ambitious goal.

The recently published market analysis by IC Insights forecasts capital spending of US$ 62 billion up 7 percent year-over-year and materials increasing 5 percent to reach US$ 53 billion in 2014. For Europe, SEMI forecasts that total spending on semiconductor equipment and materials will exceed $5 billion for the year.

Change and challenges in the semiconductor and related industries will continue in 2014.  In Europe, consolidation of our industry could continue while technological investment in EUV, the 450mm transition, and 3D-TSV are expected to continue, supported by the KET (Key Enabling Technologies) and the EU10/100/20 initiative pushed forward by both the EU and national governments.

Prominent industry experts and forecasters at ISS Europe will share their views on what advancements and conditions are necessary to help Europe reach this goal of 20 percent share of worldwide semiconductor manufacturing. Major focus will be on macro-economics, mega-trends, global and regional market development, 450mm transition, and EUV status.

The speaker line-up at ISS Europe includes the following two keynote speakers:

· Richard Koo, Chief Economist, Nomura Research, on “Understanding Eurozone Crisis with Lessons from Japan”

· Aart de Geus, Chairman and co-Chief Executive Officer, Synopsys, on “Bridging the Digital Agenda”

The market data and technical discussions will be complemented by a panel discussion “Will Europe Win with the EU10/100/20 Strategy?” with a diverse group of manufacturers and stakeholders, focusing on the issues for successful device manufacturing in Europe. The panel discussion will include representatives from the European Commission, ASM, AENEAS, GLOBALFOUNDRIES, Infineon, and STMicroelectronics. The panel will be moderated by Malcolm Penn, CEO of Future Horizons.

SEMI ISS Europe has presented the annual planning data for Europe for nearly three decades. It offers a unique opportunity to interact with high-level representatives from the entire semiconductor supply chain and to network with customers, partners and peers.