KEREN J. KANARIK, SAMANTHA TAN, JOHN HOLLAND, AARON EPPLER, VAHID VAHEDI, JEFF MARKS, and RICHARD A. GOTTSCHO, Lam Research Corporation, Fremont, CA USA.

A new plasma-enhanced atomic layer etch method delivers atomic-level etch precision with process times that are practical for use in a manufacturing environment.

Extending Moore’s Law will rely increasingly on high-precision processes to form minuscule device features with high-quality film surfaces. At the sub-14nm technology node, transistor performance will be highly sensitive to process variations, which can significantly impact current leakage and battery power loss. To give some perspective on the reality of the challenges, within the next 10 years, transistor gate dimensions are expected to be less than 50 atoms wide, and feature size variations will be measured in atoms, including contributions from surface roughness. Atomic layer processes are the most promising path for delivering the precision needed at this scale. Atomic layer deposition (ALD) has been in production for over a decade in the semiconductor manufacturing industry. However, it has been difficult making the etch counterpart — atomic layer etch (ALE) — productive enough for cost-effective manufacturing, and a commercially viable system has not been available. Here, we report on a plasma-enhanced ALE method using a commercial plasma reactor that provides atomic-level precision with process times that are suitable for high-volume device manufacturing.

Promise of atomic-layer processes
Although used in the semiconductor industry for nearly 40 years, continuous deposition and etch processes are inherently imprecise due to how they are executed. Typically, all of the reactants are introduced into the process chamber simultaneously, where they interact concurrently and continuously with the exposed film surfaces. As a result, the film thickness is often strongly dependent upon parameters such as reactant flux, which can vary locally as well as across the wafer. While continuous processes can be optimized to be more precise, for example in terms of uniformity and film smoothness, it is often difficult to compensate for all factors simultaneously.

FIGURE 1. Illustration of the process steps in a plasma-enhanced ALE cycle for a silicon film etched by chlorine and argon.

FIGURE 2. High-resolution TEM images of blanket epitaxial silicon after removal of ~400 atomic layers by continuous and ALE methods under comparable process conditions.

FIGURE 3. AFM data of blanket epitaxial silicon surfaces showing surface roughness before etch, after a continuous etch, and after ALE.

In contrast, atomic layer processes introduce the reactants sequentially through a set of repeated self-limiting cycles. In this case, the amount of film added or removed is controlled by the number of these cycles. The reactions stop when the limited reactants are consumed, and the film surface “resets” to a common state after each cycle. This results in an inherently smooth surface and uniform film.

The challenge in implementing atomic layer processes in high-volume semiconductor manufacturing is that their rates tend to be very slow, up to several orders of magnitude less than continuous processes. In the case of ALD, fab adoption came after nearly half a century of laboratory work and commercial applications in other industries such as flat panel display. Today, ALD is a mainstream technique used for depositing both metals and dielectrics in production. Although rates are still slower than some chemical vapor deposition (CVD) continuous processes, the associated benefits from ALD are attractive, especially for very thin films or when alternative processes fail to meet requirements. With ongoing improvements in productivity, ALD is expected to be used on an increasing number of emerging films.

Making ALE faster
Lagging behind its deposition counterpart, ALE was first demonstrated in the laboratory in the early 1990s and has remained a subject of ongoing important research ever since [1]. Unfortunately, achieving productivity levels sufficient for high-volume manufacturing has been challenging. To give a sense of the process times involved, consider the most studied ALE case of etching a silicon (Si) film. Reported cycle times typically vary from ~1 minute to over 5 minutes with corresponding etch rates of ~0.1 to 0.01 nm/min. These long process times are largely due to using thermal adsorption methods and specialized equipment such as ion beam systems for desorption, which are also undesirable from a cost perspective. An attractive alternative is to use a conventional etch reactor and enhance the ALE rate through specific plasma techniques.

To understand how plasma enhancement improves process cycle times, it is useful to consider the individual steps involved in a single ALE cycle. FIGURE 1 illustrates these steps for the case study of etching silicon with chlorine (CI₂) and argon (Ar). First, chlorine reactants are adsorbed onto the silicon film surface, and then excess reactants are purged. Next, argon ions are introduced to desorb the silicon chloride byproduct via directional ion bombardment, followed by purging the excess gas. This cycle is then repeated until the desired amount of film has been removed.

The adsorption step has historically been done using thermal methods, in which adsorption occurs spontaneously at room temperature and follows Langmuir kinetics. The time needed to completely saturate the surface has been reported to take ~30 seconds. The speed of this step is limited by the time needed for the Cl₂ molecules to dissociate, which must occur before chlorine can react with a dangling silicon bond at the film surface. With the plasma-enhanced ALE method, chlorine gas is ignited into a plasma, which readily dissociates Cl₂ to produce radicals that quickly react with the silicon surface. It is worth pointing out that the plasma needs to operate in a regime that minimizes ions and photons with energies above the etch threshold in order to prevent premature, uncontrolled etching.

For the desorption step, bombarding particles are used to provide enough energy to break the Si–Si bonds that have been weakened by adsorbed chlorine. However, bombarding the surface to remove material is somewhat inefficient, and calculations have indicated that it takes ~10 particles to remove just one silicon chloride molecular byproduct [2]. This step can be accelerated by applying a high flux of bombarding ions, generated by the same plasma reactor used for the adsorption step. By combining these adsorption/desorption improvements with fast gas-switching capabilities, significantly faster cycle times can be achieved.

Application of plasma-enhanced ALE
This ALE technique was evaluated on blanket epitaxial silicon wafers along with a continuous plasma process under comparable conditions. The etch rate of the ALE process is found to be significantly faster than has been typically demonstrated. To verify that the ALE process is not simply the sum of physical sputtering and spontaneous chemical surface reactions, these rates were measured and found to contribute insignificantly to the overall etch rate. It was also confirmed that the plasma-enhanced ALE process is self-limiting, with the reactive layer reaching a self-limiting thickness of a few atomic layers. Note that analogous with ALD, the ALE process benefits occur not because each cycle removes exactly one atomic layer, but because each cycle is self-limiting.

To evaluate the surface conditions after etch, blanket wafers were processed by continuous or ALE methods to remove ~400 atomic silicon layers (~50 nm) and evaluated with high-resolution transmission electron microscopy (TEM) (FIGURE 2). The continuous process produces a rough surface, while the ALE process leaves the surface smooth. Quantitative analysis of surface roughness was determined in terms of root mean squared (RMS) using atomic force microscopy (AFM). Prior to etching, the surface roughness was 2 atomic layers (FIGURE 3). The data show that the continuous process added 15 atomic layers of roughness due to accumulative effects. In contrast, the ALE process contributed only 1 additional atomic layer of roughness, thus preserving the atomic smoothness of the film. This is attributed to the self-limiting nature of ALE, where the film’s surface state resets after each cycle.

FIGURE 4. Uniformity across a blanket silicon wafer before and after the ALE process.

FIGURE 5. SEM images of polysilicon trenches etched under comparable process conditions.

The ALE process is also found to be precise on the macroscopic scale. The amount of silicon removed by ALE was measured across the full diameter of a 300mm wafer (FIGURE 4). Even though the ALE process was not optimized, the process demonstrates excellent uniformity, indicating relative insensitivity to variations in neutrals and ions across the wafer. This implies relatively high process stability and repeatability, which is an important requirement for high-volume manufacturing.

To characterize performance on patterned features, polysilicon trenches were used to examine etch profiles. As shown by the scanning electron microscope (SEM) images in FIGURE 5, the etch front for the continuous process is micro-trenched, which is a well-known phenomenon that occurs in chlorine/argon plasma chemistries. This effect is attributed to ion scattering from the feature sidewalls, causing the trench side corners to be etched faster than the center [3]. In contrast, the ALE process shows a flat etch front. This is attributed to the self-limiting nature of the process: once the adsorbed reactants are exhausted, the argon sputter rate is too slow to be significant. The overall result is the desired flat etch front with an atomically smooth surface that is uniformly repeated across the wafer.

Conclusion
A plasma-enhanced ALE method has been presented that delivers atomic-level etch precision with process times that are practical for use in a manufacturing environment. Addressing historical productivity barriers while maintaining self-limiting behavior was achieved by enhancing the adsorption and desorption steps with plasma using a commercially available etch reactor. With this new capability, production-ready ALE is becoming a reality, and this is a significant and exciting milestone for extending Moore’s Law.

Acknowledgments
The authors would like to thank Saravanapriyan Sriraman, Joydeep Guha, Jun Belen, and Elizabeth Pavel for their contributions. We gratefully acknowledge the use of facilities within the LeRoy Eyring Center for Solid State Science at Arizona State University.

1. V. Donnelly and A. Kornblit, “Plasma etching: Yesterday, today, and tomorrow,” J. Vac. Sci. Technol. A, Vol. 31(5) (2013).

2. D. Athavale and D. J. Economou, “Molecular dynamics simulation of atomic layer etching of silicon,” J. Vac. Sci. Technol. A, Vol. 13 (1995).

3. S. A. Vitale, H. Chae, and H. H. Sawin, “Silicon etching yields in F₂, Cl₂, Br₂, and HBr high density plasmas,” J. Vac. Sci. Technol. A, Vol. 19 (2001).

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KEREN J. KANARIK is a technical marketing director at Lam Research Corp., 4650 Cushing Pkwy, Fremont, CA 94538 USA; email: [email protected]

ANTHONY BARKER, KEVIN RIDDELL, HUMA ASHRAF and DAVE THOMAS, SPTS Technologies, Newport, UK. CHIA-HAO CHEN, YI-FENG WEI, I-TE CHO and WALTER WOHLMUTH, WIN Semiconductors Corp, Hwaya Technology Park, Taiwan.

The development of an 85µm diameter, 100µm deep SiC back-side via etch process for production is described.

The high breakdown voltage and high electron mobility of GaN make it an attractive material for high power device applications [1]. GaN is typically grown on SiC substrate wafers. Therefore the implementation of back-side vias involves the deep etching of SiC to form conducting pathways to the front-side circuitry [2,3].

Compared to GaAs the material properties of SiC and GaN make them much more challenging to plasma etch. Energetic plasma processes are required to deliver productive SiC etch rates whilst maintaining high enough selectivity to the masking layer and low enough wafer temperature to preserve the bonding and prevent de-lamination. This requires metal masks and careful attention to the method of wafer clamping and temperature control. Due to the ground finish of the pre-etched SiC surface descum break-through steps are essential in minimising defects within the vias to maximise device yields. In such an energetic plasma environment it is challenging to maintain smooth enough SiC walls for subsequent seed metal deposition/electro-plating and to preserve selectivity to the GaN. The build up of relatively low volatility etch by-products within the via and upon the surfaces of the plasma reactor requires effective wet cleans to be developed for both the wafer and the reactor.

Figure 1

Figure 2

Experimental

Substrates for etching were prepared by WIN Semiconductors. The 100mm diameter GaN/SiC wafers were temporarily bonded face down to a 100mm carrier. After SiC grinding to ~100µm thickness an electro-plated Ni mask was patterned ready for the SiC via etch. Following via etching the wafers were wet cleaned to strip the mask and clean the via of polymer. The GaN layer was then etched, using the SiC via as the mask, stopping on the front-side Au metal. All etching was carried out in an SPTS APS process module. A schematic of the module is shown in FIGURE 1.

The reactor is designed with a doughnut-shaped source RF coupling ceramic (13.56MHz at up to 2.2kW), and a heated chamber (set to 50-60°C) with multi-polar magnetic confinement. This arrangement delivers plasma densities in the range 1012-1013cm-3, typically 10x higher than conventional ICPs. The etch processes used SF₆/O₂/He and Cl₂/BCl₃ chemistries for the SiC and GaN, respectively. A propietary descum process was developed as part of the SiC via etch in order to reduce/eliminate the formation of pillar defects. Mechanical clamping was used to ensure reliable temperature control during the SiC and GaN etch steps. The platen temperature was set to 10°C. Optical emission spectroscopy (OES) was used to end-point the GaN etch. Wet chemical via cleaning was also investigated. Processed wafers were analysed using optical microscopy, cross-sectional SEM, profilometry and temperature label measurement.

Results

Wafer temperature was assessed using ‘4 level micro-strips’ (RS Components). These temperature stickers record the peak temperature. Table I summarises the peak temperatures for various wafer types for a 5 minute etch time when the platen is set to 10°C. These temperatures are safely below the the maximum allowable (dictated by the temporary bonding layer) which is 130°C in this case.

Table 1: Water temperatures for silicon carbide via etching

Table 2: Process trends for silicon carbide via etching

Due to the wet chemical etches of the metal seed layers and the SiC grinding that take place prior to the SiC via etch it is necessary to introduce a descum step as part of the via etch process. Optical images of SiC vias are shown in FIGURE 2 after partial etching with a range of descum conditions. Standard descums are ineffective, resulting in defectivity levels of 50-100%. A proprietary approach has been developed that substantially reduces pillar defectivity to <1%.

FIGURE 3 shows the SiC etch rate and the Ni mask selectivity for the main etch conditions as a function of bias power. The wafers were run with the optimized descum but the impact of the descum on the etch rate and selectivity has been subtracted.

The data clearly shows that there is a balance required between maximizing the etch rate and conserving sufficient Ni mask by optimizing the selectivity.

FIGURE 4 shows selectivity to the GaN underlayer across a similar bias power range. The improvement in selectivity with reducing bias power makes a 2 step (soft landing) approach appropriate for this application.

Having investigated the etch rate and selectivity trends it was necessary to focus on improvements to the sidewall roughness of the via. FIGURE 5 shows the impact of chemical dilution on the SiC etch rate and mask selectivity. Here the He flow was increased so as to be the primary process gas. There is a corresponding reduction in the slopes of the graphs. Lower etch rates result under these conditions but the selectivity becomes a softer function of bias power which can help in tuning the process. Dilution was found to improve sidewall quality and improve within wafer etch rate uniformity. The next stages of the development saw a move to higher pressure to drive the SiC etch rate and selectivity up whilst maintaining sidewall quality. FIGURE 6 shows the SiC etch rate and selectivity trends with process pressure.

Table 2 summarises the process trends for the SiC Via etch tuning.

SEM cross sections for a 100µm deep SiC via etched using a two step optimized process stopping on the GaN underlayer are shown in FIGURE 7. The GaN loss has been measured to be <0.35µm for this process.

FIGURE 8 shows the via base following GaN etching using a Cl₂/BCl₃ chemistry in the same APS module. This process takes place after the Ni mask has been stripped and the via wet cleaned of polymer. Selective etching of the GaN to the Au metallisation is achieved.

End-point traces for the GaN etch are shown in FIGURE 9. The intensities of the Ga* emissions at 417nm for 2 consecutive wafers show that the total etch times agree within 3 seconds.

The ability to clean the via of etch polymer using a 20% HNO3 solution at room temperature for 15 minutes is shown in FIGURE 10. The trenching observed at the base of these partially etched vias is typical for an energetic process of this type. The trenching disappears when etching is continued to the GaN layer.

The substrate vias were then coated with a sputtered metal seed layer and electro-plated with Au metal resulting in a nominal via resistanace slightly below 6E-3Ω.

Conclusions

A manufacturable SiC back-side via process has been developed for high power device applications. Etch rates >1.3µm/min with cross-wafer uniformities of <±5% have been achieved along with Ni mask selectivity in the range 30-40:1. The use of a unique descum process has resulted in pillar defect levels <1% and the vias are easily cleaned of polymer using HNO3 solutions. The same module hardware has been used to etch the GaN stopping on Au metal with automated end-point detection control. Via resistances <6E-3Ω have been achieved.

Acknowledgements

The authors would like to thank Tony Barrass and Brian Kiernan at SPTS for their help in designing and implementing the weighted clamp hardware for the APS module and all of the staff at WIN Semiconductors who supported the GaN technology development.

References

1. wV. Bougrov, et al., Properties of advanced semiconductor materials GaN, AlN, InN, BN, SiC, SiGe. Eds. M.E. Levinshtein et al., Wiley & Sons, New York pp. 1-30, 2011.

2. H. Stieglauer, et al., Evaluation of through wafer via holes in SiC for GaN HEMT technology, 2012 CS MANTECH Technical Digest, pp. 211-214, April 2012.

3. J-A. Ruan, et al., Backside via process of GaN device fabrication, 2012 CS MANTECH Technical Digest, pp. 215-217, April 2012. •

DAVE THOMAS is etch marketing director at SPTS Technologies, Ringland Way, Newport NP18 2TA, UK, e-mail: [email protected].