Category Archives: Metrology

Later this month, IC Insights’ November Update to the 2013 McClean Report will show a preliminary ranking of the top 25 semiconductor suppliers in 2013.  A preview of the top 20 companies is listed in Figure 1.  The top 20 worldwide semiconductor (IC and O-S-D—optoelectronic, discrete, and sensor) sales leaders forecast for 2013 include nine suppliers headquartered in the U.S., three in Japan, three in Europe, three in Taiwan, and two in South Korea.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and five fabless companies.  IC foundries are included in the top-20 semiconductor supplier ranking because IC Insights has always viewed the ranking as a top supplier list, not as a marketshare ranking, and realizes that in some cases semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  Overall, the list shown in Figure 1 provides a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries. Excluding the foundries of TSMC, GlobalFoundries, and UMC, from the top-20 ranking would bring Fujitsu ($3,524 million), Marvell ($3,205 million), and Sharp ($3,078 million) into the 18th, 19th, and 20th positions, respectively.

There are numerous changes expected within the top-20 semiconductor ranking in 2013 as compared to the top 20 ranking of 2012.  Some of the companies forecast to rise in the ranking include SK Hynix, which, despite a significant fire and production set-back at its largest memory fab in China, is taking full advantage of the surge in the DRAM market this year and is expected to move up three places and into the top 5.  Also, Broadcom is forecast to edge into the top 10, Micron is expected to move up two spots, spurred by its acquisition of Elpida in 3Q13, and MediaTek is forecast to jump up six positions to 16th place and into the top-20 ranking for the first time.  MediaTek is experiencing extremely strong demand for its devices in the booming low-end smartphone business in China and other Asia-Pacific locations.  In fact, MediaTek expects its application processor shipments for smartphones to reach over 200 million units this year, about double the 108 million units the company shipped in 2012.

In contrast to the companies moving up in the ranking, Fujitsu is expected to drop five places to fall out of the top-20 ranking in 2013, going from being ranked 16th in 2012 to 21st this year (the company sold its analog and MCU business to Spansion in August of this year).  Renesas is another “casualty” expected in the top-20 ranking and is forecast to fall to 11th place in 2013 from the 7th position it held in 2012.

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Figure 1

In total, the top 20 semiconductor companies’ sales are forecast to increase by seven percent in 2013 as compared to 2012, which would be two points better than the five percent forecast for the total worldwide semiconductor market this year.  It is expected to take total semiconductor sales of over $3.7 billion to make the top-20 ranking in 2013.

As shown in Figure 2, there is expected to be a 60-percentage-point range of growth rates among the worldwide top 20 semiconductor suppliers in 2013 (from +44 percent for SK Hynix to -16 percent for Sony).  The continued success of the fabless/foundry business model and the strong growth of the memory market (especially the 29 percent DRAM market surge) this year is evident when examining the nine top-20 semiconductor suppliers that are forecast to log higher growth than the total worldwide semiconductor market (five percent).  As shown, the top nine performers in 2013 are forecast to include three memory companies (SK Hynix, Micron, and Toshiba), two fabless companies (MediaTek and Qualcomm), and two pure-play foundries (TSMC and GlobalFoundries).

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Figure 2

Figure 2 illustrates that the two top-20 ranked companies that are forecast to register double-digit sales declines in 2013 are headquartered in Japan (Renesas and Sony).  As previously mentioned, Japan-based Fujitsu is also expected to register a double-digit decline (-15 percent) in 2013 and drop out of the top 20 ranking this year.  However, it should be noted that the conversion of Japanese company semiconductor sales from yen to U.S. dollars, at 96.96 yen per dollar forecast for 2013 versus the 79.70 yen per dollar rate in 2012, is expected to have a significant impact on the sales figures for the Japanese companies.  Using a constant 2012 U.S. dollar versus Japanese yen exchange rate for 2013, the forecasted 2013 semiconductor sales increases of Sony, Fujitsu, and Renesas would be four percent, three percent, and two percent, respectively.

More details on the forecasted 2013 top 25 semiconductor suppliers, as well as IC Insights’ latest detailed forecast for the 2014 semiconductor market, will be provided in the November Update to The McClean Report.

Rubicon Technology announced the launch of the first commercial line of large diameter patterned sapphire substrates (PSS) in four-inch through eight-inch diameters.  This new product line provides LED chip manufacturers with a ready-made source of large diameter PSS to serve the needs of the rapidly growing LED general lighting industry.

This news is very important as growth of the LED general lighting market is expected to expand from nearly 300 million lamps shipped in 2012 to 3 billion by 2020 according to IMS Research.  Technology innovation is helping the LED supply chain prepare for this dramatic growth.  Most high-brightness LED manufacturers etch a pattern into the sapphire wafers in order to both improve epitaxial growth and extract more light from each chip. Patterned sapphire substrates have been available for purchase in smaller diameters, but Rubicon is the first to offer highly customizable 6” and 8” PSS. The larger substrates increase chipmakers’ throughput and efficiency.

KEIBOCK LEE, Park Systems, Santa Clara, CA.

3D atomic force microscopes can measure critical dimensions, line edge roughness and sidewall roughness in a way that is highly accurate, non-destructive and cost-effective.

One of the most challenging features in the semiconductor industry is the continuous research and the subsequent fabrication of integrated circuits with enduringly smaller critical dimensions (CDs). As shown in FIGURE 1, CDs must be measured at the top, middle and bottom of features, as well as various parameters such as line edge roughness (LER), the line width roughness (LWR) and the sidewall roughness (SWR).

The characterization of such factors that determine the shape and the roughness of the device patterns for device manufacturers is of utmost importance due to the fact that they directly affect the device performance. Optical measurement techniques, which are limited in terms of resolution. Therefore, the existing prevalent method for measuring these factors prior was primarily the scanning electron microscopy (SEM) with its image analysis software. Despite the fact that this technique offers substantial advantages such as automation and compatibility with standard critical dimension SEM tools, it cannot provide the user with high resolution LER data due to the fact that SEM resolution is reaching its limits, therefore 3D AFM offers a highly desirable solution. Leading manufacturers have implemented AFM that can measure resist profile, LER and SWR in a way that is highly accurate, non-destructive and cost-effective. The precise and full characterization of such features is extremely essential during the pattern transfer process as it offers the possibility of imaging all surfaces of the pattern.

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FIGURE 1. LER, LWR and SWR are the limiting factors of resolution in optical lithography.

What is non–contact 3D AFM?
The basic principle of non-contact 3D-AFM is that a cantilevered beam rapidly oscillates just above the surface of the imaging sample. This offers several advantages, as compared to the traditional contact and intermittent modes. One of the advantages is that there is no physical contact between the tip and the surface of the sample. Moreover, as depicted in FIGURE 2, the Z-scanner, which moves the tip, is decoupled from the XY scanner, which solely moves the sample, thus, offering flat scanning and an additional benefit of improved Z-scan bandwidth. Furthermore, by tilting the Z-scanner, the sidewall of the nanostructures can be accessed and roughness measurements performed along the sidewall of photoresist lines. At the same time, measurements of the critical dimensions of top, middle, and bottom lines can be made.

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FIGURE 2. The independent tilted Z-scanner enables measurements of the sidewalls of features.
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FIGURE 3. Combination of the three acquired images for 3D AFM pattern reconstruction.

Data acquisition is performed by a conical tip in predefined tilted angles, typically 0º, a, and -aº. Consequently, and by combining these three scans (a method called image stitching), the 3D pattern can be constructed, as shown in FIGURE 3. This provides an excellent and extremely accurate method that takes advantage of the interference pattern of the standing waves in order to measure features such as the total height, the top, middle, and bottom width. 3D AFM is capable of advanced three-dimensional imaging of both isolated, and dense line profiles. It is less costly than the alternative techniques (CD-SEM and focused ion beam (FIB)) for imaging and measuring parameters of line profiles since the preparation of the sample is by far simpler.

Noise levels in 3D-AFM
A critical requirement when dealing with metrology tools is associated with constraining the level of noise in the manufacturing environment. A study of noise levels on a 300 mm wafer (FIGURE 4) shows the overall 3D AFM system noise at levels are lower than 0.05 nm (0.5 angstrom).

Roughness measurements
Roughness can be transferred into the final etched profile, thus, roughness measurements can describe and determine the quality of the patterns. The tilted Z scanner in combination with the low noise levels that are prevalent during the AFM process can provide accurate results in terms of sidewall roughness measurements. FIGURE 5 depicts the 3D AFM imaging of a photoresist semi-dense line pattern and the respective grainy structure of its sidewall. The precision with which the SWR was measured is validated by the high repeatability (0.08nm 1 sigma for 5 sites wafer mean) for the sidewall roughness of about 6.0 nm.

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FIGURE 4. 3D AFM noise levels on a 300 mm wafer. The system noise level is less than 0.05 nm at every position and typically 0.02~0.03 nm RMS.
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FIGURE 5. 3D AFM image of a photoresist semi-dense line pattern imaged with Z-scanner tilt. The bottom figure clearly depicts the grainy structure of the sidewall.

It needs to be noted that roughness depends, amongst others, on the aerial image contrast (AIC) or in other words the physics of exposure. AIC is determined as the quotient between the subtraction and the addition of the maximum and minimum image intensities.

Several consequent series of images with variable exposure reveal that LER significantly increases when the AIC is decreased, a fact that underlines that AIC is a controlling factor for LER. Moreover, and as depicted in FIGURE 6, reduced levels of AIC produced line profile images of the resist that were more blunted, and also smaller sidewall angles (SWA).

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FIGURE 6. Park 3D AFM line profiles at different AIC levels reveal the proportionate relationship between SWA and AIC.
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FIGURE 7. A 3D AFM image of a 300 nm photoresist line pattern yields full information regarding the morphology of the sidewall (top) Side-wall Roughness is different at different AIC levels, a fact that indicates the connection between LER and SWR (bottom).

FIGURE 7 illustrates the capability of Park 3D AFM to image all surfaces of the pattern, in contrast to the conventional AFM or the SEM, which cannot fully characterize the surface data, and obtain information such as base, top and both sidewall roughness from sidewall characterization. A 300 nm photoresist line pattern was imaged and the respective line profiles were obtained that clearly showed a substantial difference in terms of SWR between 97% and 40% AIC. More specifically, the lower the value of AIC, the more increased was the measured roughness. This intense decrease of roughness is underlying the fact that LER and the measured sidewall roughness are clearly correlated.

Finally, it needs to be emphasized the role of non-contact 3D AFM in terms of preserving the tip sharpness of the cantilever. In an independent study, researchers performed 150 consecutive measurements using the same tip and the tip wearing proved to be minimal. This is a prominent feature of AFM that prevents the continuous costly replacement of the tip but also ensures that the sample will be viable and not damaged by the AFM cantilever. The preservation of the tip sharpness allows for continual measurements of high resolution roughness data.

Conclusions
The potentialities of the innovative, non-destructive imaging technique of 3D AFM has several advantages compared to conventional SEM systems. An independent and tilted Z-scanner overcomes the disadvantages of alternative metrology tools and measure parameters such as detailed sidewall morphology and roughness, and sidewall angle characterization that render the optimization and evaluation process easier and far more detailed. •


KEIBOCK LEE is president and general manager of Park Systems, Santa Clara, CA.

Senior executives from Semiconductor Industry Association (SIA) member companies and other multi-national semiconductor companies around the globe sent a letter to Chinese Vice Premiers Wang Yang and Ma Kai on October 16, encouraging China to support duty-free coverage for semiconductor products in an expanded Information Technology Agreement (ITA). The ITA promotes fair and open trade by providing for duty-free treatment of certain information technology products, including semiconductors, but the list of covered products has not been updated since the ITA’s inception in 1996.

Signed by 34 senior executives of semiconductor companies that enable integrated circuit (IC) design and production worldwide, the letter demonstrates the solidarity of global semiconductor industry leaders in support for ITA coverage of multi-component integrated circuits (MCOs), multi-chip integrated circuits (MCPs), and semiconductor equipment and materials.

“The inclusion of MCOs in an expanded ITA is very important to the global semiconductor industry, and is well-aligned with China’s IC sector development goals outlined in its 12th Five Year Plan,” said Ian Steff, SIA’s Vice President of Global Policy and Technology Partnerships. “Tariff-free treatment for all MCOs, regardless of end-application, as well as for other products that comprise the semiconductor supply chain, will fuel semiconductor design and manufacturing investments, reduce costs for consumers, promote exports, and strengthen overall IC sector development and growth worldwide.”

Global semiconductor executives seek for China to use this unique opportunity to support duty-free treatment for MCOs and other semiconductor priorities for the benefit of semiconductor designers, manufacturers, and customers around the globe. The intent of the original negotiators of the ITA was to provide for duty-free treatment for all types of semiconductors and other products supporting the semiconductor supply chain. Global semiconductor leaders urge all ITA parties to continue to embrace this fundamental ITA principle in any expansion of the agreement in order to fully realize the benefits that chip technology provides to downstream information communication technology (ICT) advancement.

The global CEO letter comes on the heels of a recent joint WTO-OECD-UNCTAD report, which found that countries that are signatories to the ITA have seen a significant increase in ICT economic activity, while growth in non-member nations has not kept pace. These findings highlight the importance of expanding the ITA in continuing global ICT growth and spurring continued innovation and technological growth in the sector. For the semiconductor industry, this means ensuring that MCOs are included in an expanded ITA agreement.

“A successfully expanded ITA would be among the most commercially meaningful World Trade Organization (WTO) trade agreements for the semiconductor industry in decades,” Steff said. “We look forward to working with Chinese officials to reach a prompt, impactful deal on ITA expansion.”

North America-based manufacturers of semiconductor equipment posted $975.3 million in orders worldwide in September 2013 (three-month average basis) and a book-to-bill ratio of 0.97, according to the September EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 0.97 means that $97 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in September 2013 was $975.3 million. The bookings figure is 8.3 percent lower than the final August 2013 level of $1.06 billion, and is 6.8   percent higher than the September 2012 order level of $912.8 million.

The three-month average of worldwide billings in September 2013 was $1.01 billion. The billings figure is 7.1 percent lower than the final August 2013 level of $1.08 billion, and is 13.6 percent lower than the September 2012 billings level of $1.16 billion.

“The book-to-bill ratio reflects seasonal softening and near-term deferral in capital spending in some segments of the industry,” said Denny McGuirk, president and CEO of SEMI.  “We expect that market demand for semiconductors will drive continued capacity investment in 2014.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill

April 2013

1,086.3

1,173.9

1.08

May 2013

1,223.4

1,321.3

1.08

June 2013

1,213.7

1,334.2

1.10

July 2013

1,204.0

1,207.2

1.00

August 2013 (final)

1,081.9

1,063.9

0.98

September 2013 (prelim)

1,005.6

975.3

0.97

Source: SEMI, October 2013
The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the Equipment Market Data Subscription (EMDS).

Zygo Corporation today announced that Dr. Chris L. Koliopoulos is stepping down as the Chairman of the Board, President and Chief Executive Officer effective immediately, following the mutual decision of Dr. Koliopoulos and Zygo’s board of directors. The Board has appointed director Gary K. Willis as interim Chief Executive Officer and Michael A. Kaufman as Chairman of the Board.

Mr. Willis has played a leadership role at Zygo in several capacities over the past three decades. He served as a director of Zygo from 1992 to 2000 and from 2009 to present, as Zygo’s Chairman of the Board from 1998 to 2000, as President in 1992 and as Chief Executive Officer of the Company from 1993 through 1999.

“The Board appreciates Dr. Koliopoulos’ service to Zygo and we wish him the best in his future endeavors,” said Carol Wallace, Chair of the Company’s Corporate Governance & Nominating Committee. “The Board of Directors is focused on achieving Zygo’s full potential for the benefit of our shareholders, and continuing to enhance Zygo’s leadership position in its markets. We believe that Mr. Willis has the requisite experience and leadership qualities to lead the company forward.

“It has been a privilege for me to work with many fine colleagues at Zygo” said Dr. Koliopoulos. “I am proud of Zygo’s many accomplishments, and look forward to its continued success.”

Zygo Corporation is a worldwide supplier of optical metrology instruments, precision optics and electro-optical design and manufacturing services serving customers in the semiconductor capital equipment, bio-medical, scientific and industrial markets.

Jordan Valley Semiconductors Ltd., a supplier of X-ray based metrology tools for advanced semiconductor manufacturing lines, received another order for its recently introduced JVX7300LMI scanning X-ray in-line metrology tool for patterned and blanket wafers.  The system has been purchased for advanced process development and production ramp-up for 14nm and 10nm nodes.

The tool provides fully automated advanced metrology for epitaxial materials such as SiGe, Si:C/P and III-V on silicon FinFET structures, as well as high-k and metal gate stacks and other critical layers.

Isaac Mazor, JV CEO, said: “We are pleased to have been selected by key customers to support their FEOL (Front-End-Of-Line) process metrology.  This selection represents the customers’ confidence in Jordan Valley’s ability to provide valuable metrology solutions for their most demanding advanced applications, trusting first principle X-ray based metrology to provide unique process control solutions.”

Mazor added, “Advanced logic devices set new metrology challenges and requirements for key transistor level structure such as FinFET, Ge and III/V materials on silicon, as well as high-k and metal gate stacks used to enhance the transistor performance. Jordan Valley was able to meet the customers’ stringent process requirements in a short period of development time.”

“In choosing the JVX7300LMI platform, the customers acknowledged the significant contribution of the product in shortening the process development cycle, coupled with enabling process performance and extendibility to future technology nodes.” Mazor concluded, “We believe that the JVX7300LMI can be a strong contributor to assure high yield in the current and next generation process nodes.”

The JVX7300LMI is an X-ray metrology system for 14nm and 10nm nodes R&D and production ramp for FEOL applications such as SiGe, Si:C/P, FinFETs, high-k/metal gate and replacement channel materials such as Ge and III-V layers on Si. It is also used for the development and production of the emerging GaN on Si market.

JVX7300LMI


This tool enables scanning HRXRD, XRR and (GI)XRD measurements. HRXRD is capable of measuring epitaxial layer composition, thickness, density, strain and relaxation of single and multi-layer stacks. Additionally, with XRR and (GI)XRD channels, the tool provides information on the thickness, density, phase and crystallinity of ultra-thin layers typically used in the FEOL process. Unlike optical or spectroscopic tools, the HRXRD and XRR are first principle techniques that deliver accurate and precise results without calibration.

 Dow Electronic Materials, a business unit of The Dow Chemical Company, today announced availability of its SOLDERON BP TS 6000 Tin-Silver Plating Chemistry for use in lead-free solder bump plating applications. This next-generation formulation features enhanced plating performance, bath stability and ease-of-use, thereby enabling the industry’s widest process window with the most robust process flexibility and a competitive cost of ownership.

“As flip chip packages become mainstream and the industry continues to move toward 2.5D and 3D packaging technologies, there is a clear market requirement for high-performance lead-free alternatives for plating applications,” said Dr. Robert Kavanagh, global business director, Advanced Packaging Metallization, for Dow Electronic Materials. “Customers need materials optimized for today’s finer bump geometries. This new chemistry achieves significant performance improvements, delivering even faster plating speeds, better uniformity and smoother surface morphology in addition to a smooth, void-free interface when used together with Dow’s and other leading copper (Cu) pillar formulations.”

In Cu pillar capping applications, SOLDERON™ BP TS 6000 Tin-Silver forms a smooth,micro-void free interface post reflow.

In Cu pillar capping applications, SOLDERON™ BP TS 6000 Tin-Silver forms a smooth,micro-void free interface post reflow.

With a single formulation, SOLDERON BP TS 6000 Tin-Silver (SnAg) is capable of plating speeds ranging from 2 to 9 um/min., which creates a significantly wider operating window when compared with other solutions in the marketplace. The tunable nature of the Ag composition in this formulation makes it suitable for a number of applications and eliminates the need to change the chemistry to address different processing requirements. The new chemistry has proven to be robust enough for both bumping and capping of a wide range of patterned wafers and it is not restricted for use with specific photoresists. It exhibits with-in die (WID) uniformity after reflow of <5% over a wide range of wafer types, which demonstrates its suitability for high-volume manufacturing. Additionally, it is macro- and micro-void free after reflow for improved yields and reliability.

“One of the most compelling strengths of SOLDERON BP TS 6000 Tin-Silver is the product’s enormous flexibility, which allows it to perform exceptionally well in a variety of applications from in-via and mushroom bumping to Cu and micro-Cu pillar capping,” added Kavanagh.

SOLDERON BP TS 6000 Tin-Silver plating bath has proven to be both electrolytically and thermally stable, which contributes to the chemistry’s competitive COO. Offering an electrolytic bathlife of >100 Ah/L and a ≥6-month pot life, it is compatible with in-line metrology processes, for superior ease-of-use.

Semiconductor capital spending has increased significantly among pure-play foundries as more IDMs shift to a fabless/fab-lite business model and as new foundry participants intensify competition among the old guard. The total capital outlays by the Big 4 pure-play foundries are forecast to be $16.6 billion in 2013, which would represent 53 percent of their combined sales (Figure 1).  This far exceeds the industry average of 18 percent capital-spending-to-sales ratio.  The Big 4’s capital spending as a percent of “final sales” is forecast to be 24 percent in 2013, still well above industry average.

Figure 1

Figure 1

A few years ago, TSMC stated that it planned to keep its capital spending at about 20% of its sales, but that was before GlobalFoundries and Samsung brought competitive pressure to the market and started chipping away at TSMC’s business. TSMC spent $5.9 billion in capital spending in 2010 (a budget that was increased twice in the first half of the year), an all-time record amount of capital spending for the company at that time. TSMC spent $8.3 billion in capital expenditures in 2012 and plans to further increase its capex spending to $10.0 billion in 2013. It appears that TSMC will be aggressive in its marketshare fight with GlobalFoundries and Samsung and is likely to greatly exceed its 20% of sales goal for capital spending outlays over the next few years.

The question with regard to the expected combined 2011-2013 IC foundry spending by the Big 4 pure-play suppliers ($46.3 billion) is whether it is too much.  As shown in Figure 1, the “final sales” capital-spending-to-sales ratio of the major foundries was a relatively low 14-15 percent in 2005-2007 before falling to only nine percent in 2008 and 12 percent in 2009.  In 2010, this figure rose to 23 percent, a level not seen since the boom year of 2004.  Spurred by the surge in capital spending by TSMC and GlobalFoundries, this figure rose to 30 percent in 2011.  For 2012, the capital spending as a percent of sales figure for the Big 4 foundries dropped back to a more “reasonable” 24 percent, with the same percentage expected for 2013.  Given the major foundries high capacity utilization levels for leading-edge device production, it appears that current spending levels are warranted and should not lead to significant overcapacity issues.

With demand for IC foundry services from fabless and fab-lite IDM companies expected to be high over the next five years, there is little doubt that demand for IC foundry production will remain strong.  Overall, IC Insights believes that the pure-play foundry market will further divide into the leading-edge IC foundries like TSMC, GlobalFoundries, UMC, and Samsung, and the specialty foundries like TowerJazz, X-Fab, etc.  Thus, the vast majority of future foundry capital spending can still be expected to come from the small group of major foundries targeting leading-edge IC production.

Today, ASML and imec announced the next major step in their extensive collaboration, with the launch of the Advanced Patterning Center. Together they plan to tackle upcoming scaling challenges due to the chip industry’s move towards single digit nanometer dimensions. The Center will be located at the imec campus in Leuven and is expected to grow to close to 100 engineers over the next couple of years.

To guarantee critical dimension uniformity and overlay control, soon to be measured in fractions of one nanometer, imec and ASML will collaborate to investigate the practical interaction between all the different steps in the chip patterning process. The Advanced Patterning Center will use actual devices to analyse and optimize process steps as well as materials and device architecture choices, while applying integrated metrology.

The Advanced Patterning Center combines imec’s and ASML’s complementary expertise, engineering capabilities and patterning infrastructure to tackle these challenges, the infrastructure investments and the patterning knowledge requirements.

Imec will bring to the partnership its world leading clean room infrastructure (full 300mm pilot line with extension to 450mm) through which it supports a unique partner network of material and equipment suppliers, IDMs, foundries and fabless companies.

ASML will support the Advanced Patterning Center by making available its most advanced scanners, metrology systems and holistic lithography solutions, and by using the Center’s resources to optimize its offerings for the fab environment.

“ASML and imec have been partners for almost as long as both organizations exist, and while we have both benefited from this relationship, I believe the biggest beneficiary has been the chip industry which has gained faster access to breakthrough technology. I’m extremely confident that this continued investment in our joint capabilities will further accelerate technology development and new device introductions,” said Martin van den Brink, President and Chief Technology Officer at ASML.

“In order to stay ahead in today’s fast-evolving and equipment-intensive semiconductor business, it is critical that the entire semiconductor eco system has insight and access to state-of-the-art technology,” said Luc Van den hove, President and CEO at imec. “By bringing our collaboration to the next level, we will be able to expand our knowledge base more quickly and drive lithography advancements. In this way the global partner network of both companies will have access to the most advanced patterning processes for sub-10 nanometer technologies. This is crucial to better address future scaling and infrastructure challenges.”

As a result of the intensified collaboration between imec and ASML, the global semiconductor ecosystem will gain access to best-in-class patterning solutions for next-generation chip manufacturing, paving the way to future technology leadership and commercial success.