Category Archives: Metrology

At SEMICON West 2013, Boston Semi Equipment (BSE), LLC announced the expansion of its semiconductor front end and back end equipment businesses in Tempe, Ariz. into a new and larger facility. The new location provides space for the company’s increasing workforce, a test floor for the reconfiguration of current generation semiconductor test equipment and customer test cell optimization, a temperature controlled environment for front end fab tool inspections and increased storage space for the company’s inventory of ready-to-ship semiconductor manufacturing equipment.

 “Our company has continued on a steady growth path since its founding in 2010,” stated Bryan Banish, Boston Semi Equipment CEO. “Our new location increases the company’s capacity to reconfigure and refurbish equipment to support our expanding business. We are able to configure and work on more systems in parallel, reducing our already short lead times and increasing our ability to quickly deliver large orders to meet our customers’ capacity requirements.”

 “Semiconductor manufacturers have come to rely on Boston Semi Equipment when they need to add capacity,” added Colin Scholefield, EVP Boston Semi Equipment. “We have established a reputation for quick response to their capacity needs. Whether they need equipment from OEMs or reconfigured equipment from the secondary market, BSE has the solution. This new facility will definitely aid us in keeping up with the increasing demand for our equipment solutions.”

Boston Semi Equipment currently has operations in Burlington, Mass., Tempe, Ariz., the Philippines, Japan, Taiwan and Singapore, providing products and services for both front and back end semiconductor processes.

SEMICON West 2013 included a robust set of technical and marketing presentations on the general theme of developing new semiconductor devices in the session “Lab to Fab: From R&D to High Volume Manufacturing” held 1:30-3:30PM on July 9. Ably moderated by Paula Doe, the session included presentations on modeling, experimenting, and prototyping new materials and structures such that they can profitably moved into high-volume manufacturing (HVM). Two of the presentations that described not just technologies but new fundamental methodologies for R&D came from Coventor and Intermolecular, small innovative companies based in Silicon Valley.

Dr. David Fried, CTO of Coventor, presented how the company’s “SEMulator3D” software modeling product based on “voxels” allows for advanced physics-based modeling of unit-processes, integrated-processes, device structures, and even device electrical parameters. The modeling starts with unit-processes such as depositions, etches, and epitaxial growth at the nanometer-scale. However, unlike TCAD and other device models, this software can also extend across length scales to provide full-wafer maps of physical parameters.

Fried explained how the model is built on data extracted from publicly available leading device information, such as the cross-section SEMs in Intel’s seminal IEDM paper on 22nm finFETs. The model is “behavioral” since it can predict the effects of changes in dynamic process conditions, and can therefore be used to do “virtual fabrication” of targeted devices. “You can do some interesting explorations,” explained Fried, “like what if you had a defect on a fin that was used to grow an epi-layer?” He showed how the complex interactions of different growth rates in different crystalline directions on 3D structures could be predicted by the software, and that the predicted structural shifts  appear to match the SEM cross-sections shown in the literature.

This modeling software can thus be used as a “virtual metrology” tool that can mimic real in-fab metrology. It can replace slow out-of-fab destructive characterization, and can provide local virtual measurements of structural parameters. It can be used to study the effects of incoming geometric parameters as well as process variations on the final structure. For example, the Cu cross-section area of a BEOL interconnect layer can be predicted, in contrast to unit-process models/controls that merely create wafer-uniformity-maps of  Etch, Cu-barrier/seed PVD, Cu-ECD, Cu-CMP, and other process steps.

Combinatorial R&D

Dr. Raj Jammy, Sr. VP & GM Semiconductor Group, Intermolecular, Inc.—most recently a SEMATECH VP—discussed the need for new ways of doing R&D now that the integration of new materials dominates device enhancements. As semiconductor technology has evolved to smaller and smaller device geometries, the number of new materials used on CMOS chips continues to increase. Consequently, the cost of discovering and integrating new materials into complex devices structures continues to increase.

New materials are needed for 3D FinFETs (alternate-channel materials), 3D Flash Memories and ReRAM (storage cells), and 3D packaging (through-silicon vias and through-mold vias), and all  use complex processes with unpredictable interactions. Developing and optimizing these new materials leads to high costs for R&D and even higher costs to integrate into HVM.

Intermolecular has created High Productivity Combinatorial (HPC™) tools for PVD, CVD, ALD, and wet-processing steps that allow for multiple site-isolated experiments to be done on a single 300mm wafer. When combined with throughput-match characterization tools using an automated database into what the company terms an application-specific “HPC workflow,” everything from an initial design-of-experiments (DOE) to full HVM integration can be done in 3-6 months instead of the 3-5 years needed by conventional R&D approaches.

HPC workflows can accelerate R&D in the early stages of materials exploration such that an entire cycle-of-learning can occur in just 4 hours. HPC workflows can also be used with short-loop flows through a customer’s fab to allow for a 3-4 week cycle-of-learning.

As an example of this methodology’s ability to accelerate learning, Jammy showed how hundreds of experimental parameters had to be explored in developing a germanium (Ge) MOS cap for CMOS integration. Variations in the substrate, surface cleaning, High-K stack, metal electrode, and post-treatment all play significant roles in determining the final device parameters. All these factors had to be co-optimized iteratively, and the project was accomplished in <3 months.

IMI started in 2004 with SanDisk and ATMI, and has since added Guardian Corp., Toshiba, IBM, First Solar, GlobalFoundries, Epistar, Micron as customers.

 

Toshiba Corporation today announced that it will expand its No. 5 semiconductor fabrication facility (Fab 5) at Yokkaichi Operations in Mie, Japan, to secure manufacturing space for NAND flash memories fabricated with next generation process technology and for future 3D memories. Fab 5 second phase construction will start at the end of August this year and be completed in summer next year. Decisions on equipment investment and production will reflect market trends.

Yokkaichi Operations currently has three Fabs mass producing NAND flash memory, including Fab 5 phase 1. Fab 5’s construction was planned around two phases, the first of which went into operation in July 2011. After giving careful consideration to the balance of product supply and demand, and noting a recovery driven by growing demand for smartphones, tablets, SSD for enterprise servers and other new applications, Toshiba now anticipates further medium- to long-term market expansion and recognizes that the time is right to expand Fab 5.

In addition to securing capacity for future generations of NAND Flash memory fabricated with the company’s latest process technology, Toshiba will also use Fab 5 phase 2 for production of 3D memories that are expected to find growing application in coming years. The extension will allow the company to boost competitiveness and enhance its responsiveness to technology advances and market demands.

Fab 5 phase 2 will have an automated product transportation system and quake-absorbing structure and will be designed to minimize environmental loads. Deployment of LED lighting and up-to-date energy-saving production facilities, along with full and effective use of waste heat, are expected to cut CO2 emissions by 13 percent compared with Fab 4.

Going forward, Toshiba will expand its memory business and boost competitiveness by timely investments, leadership in advanced process technology and the development of new generation memories that answer market needs.

North America-based manufacturers of semiconductor equipment posted $1.32 billion in orders worldwide in May 2013 (three-month average basis) and a book-to-bill ratio of 1.08, according to the May EMDS Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.08 means that $108 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in May 2013 was $1.32 billion. The bookings figure is 12.5 percent higher than the final April 2013 level of $1.17 billion, and is 18.1 percent lower than the May 2012 order level of $1.61 billion.

The three-month average of worldwide billings in May 2013 was $1.22 billion. The billings figure is 12.6 percent higher than the final April 2013 level of $1.09 billion, and is 20.5 percent lower than the May 2012 billings level of $1.54 billion.

“The SEMI Book-to-Bill continues to show steady improvement as the ratio remains at or above parity for the fifth consecutive month,” said Daniel P. Tracy, senior director of Industry Research and Statistics at SEMI.  “The spending outlook for the year is improving as foundries continue to invest in advanced technologies and NAND manufacturers plan to increase spending on equipment.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings 
(3-mo. avg)

Bookings
 (3-mo. avg)

Book-to-Bill

December 2012

1,006.1

927.4

0.92

January 2013

968.0

1,076.0

1.11

February 2013

974.7

1,073.5

1.10

March 2013

991.0

1,103.3

1.11

April 2013 (final)

1,086.3

1,173.9

1.08

May 2013 (prelim)

1,223.3

1,321.2

1.08

Source: SEMI, June 2013

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the Equipment Market Data Subscription (EMDS).

 

Worldwide semiconductor manufacturing equipment spending is projected to total $35.8 billion in 2013, a 5.5 percent decline from 2012 spending of $37.8 billion, according to Gartner, Inc. Gartner said that capital spending will decrease 3.5 percent in 2013, as major producers remain cautious in the face of market weakness.

"Weak semiconductor market conditions, which continued into the first quarter of 2013, generated downward pressure on new equipment purchases," said Bob Johnson, research vice president at Gartner. "However, semiconductor equipment quarterly revenues are beginning to improve and positive movement in the book-to-bill ratio indicates that spending for equipment will pick up later in the year. Looking beyond 2013, we expect that the current economic malaise will have worked its way through the industry and spending will follow a generally increasing pattern in all sectors throughout the rest of the forecast period."

Gartner predicts that 2014 semiconductor capital spending will increase 14.2 percent, followed by 10.1 percent growth in 2015. The next cyclical decline will be a mild drop of 3.5 percent in 2016, followed by a return to growth in 2017.

Table 1

Worldwide Semiconductor Manufacturing Equipment Spending Forecast, 2012-2017 (Millions of Dollars)

 

2012

2013

2014

2015

2016

 

 

 

2017

Semiconductor Capital Spending ($M)

58,742.8

56,704.5

64,745.6

71,305.9

68,790.4

72,399.6

Growth

-11.9%

-3.5%

14.2%

10.1%

-3.5%

5.2%

Capital Equipment ($M)

37,833.2

35,761.6

42,591.0

47,488.8

44,712.0

48,580.9

Growth

-16.1%

-5.5%

19.1%

11.5%

-5.8%

8.7%

Wafer-Level Manufacturing Equipment ($M)

31,445.8

29,900.7

35,293.4

40,400.0

38,867.7

42,179.1

Growth

-17.8%

-4.9%

18.0%

14.5%

-3.8%

8.5%

Wafer Fab Equipment ($M)

29,644.2

27,957.3

32,831.5

37,750.5

36,344.4

39,215.4

Growth

-18.5%

-5.7%

17.4%

15.0%

-3.7%

7.9%

Wafer-Level Packaging and Assembly Equipment ($M)

1,801.6

1,943.4

2,461.9

2,649.5

2,523.3

2,963.7 

Growth

-3.1%

7.9%

26.7%

7.6%

-4.8%

17.5%

Die-Level Packaging and Assembly Equipment ($M)

3,867.3

3,503.7

4,258.9

3,922.5

3,232.1

3,548.2

Growth

-10.5%

-9.4%

21.6%

-7.9%

-17.6%

9.8%

Automated Test Equipment ($M)

2,520.0

2,357.2

3,038.7

3,166.3

2,612.2

2,853.5

Growth

0.4%

-6.5%

28.9%

4.2%

-17.5%

9.2%

Other Spending ($M)

20,909.6

20,943.0

22,143.3

23,815.1

24,401.2

24,067.9

Growth

-3.1%

0.2%

5.7%

7.6%

2.5%

-1.4%

Source: Gartner (June 2013)

Although capital spending for all products will decline in 2013, logic spending will be the strongest segment, declining only 2 percent compared with a 3.5 percent decline for the total market. This is driven by aggressive investment of the few top players, which are ramping up production at the sub-30-nanometer (nm) nodes. Memory will continue to be weak through 2013, with maintenance-level investments for DRAM and a slightly down NAND market until supply and demand balance returns. For 2014, Gartner sees capital expenditure (capex) returning to growth with an increase of 14.2 percent over 2013. The foundry segment will see an increase in spending of about 14.3 percent this year, while both integrated device manufacturers (IDMs), and semiconductor assembly and test services (SATS) providers will show spending declines. Beyond 2013, memory surges in 2014 and 2015 and a cyclical decline in 2016, while logic returns to a steady growth pattern.

The wafer fab equipment (WFE) market is seeing continuous quarter-over-quarter growth in 2013, as major manufacturers come out of a period of high inventories and a generally weak semiconductor market. Early in the year the book-to-bill ratio passed 1:1 for the first time in months, signaling that the need for new equipment is strengthening as demand for leading-edge devices is improving. Looking beyond 2013, Gartner sees growth returning to the WFE market with double-digit growth in 2014 and 2015, before a modest cyclical downturn in 2016.

The capital spending forecast estimates total capital spending from all forms of semiconductor manufacturers, including foundries and back-end assembly and test services companies. This is based on the industry’s requirements for new and upgraded facilities to meet the forecast demand for semiconductor production. Capital spending represents the total amount spent by the industry for equipment and new facilities.

More detailed analysis is available in the report "Forecast: Semiconductor Capital Spending, Worldwide, 2Q13 Update."

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends.

 

Total inventory held by semiconductor suppliers declined significantly in the first quarter as excess stockpiles created during the global economic malaise of 2012 were cleared away, done in anticipation of a resurgence in consumer demand for electronic products expected by the second half of 2013.

Semiconductor makers’ inventory in the first quarter declined to $37.6 billion, down 4.6 percent from $38.4 billion in the fourth quarter of 2012, according to a Supply Chain Inventory Brief from information and analytics provider IHS (NYSE: IHS). The figure below presents the IHS estimate of inventory held by semiconductor suppliers in terms of revenue.

The decline in inventory paralleled the contraction in semiconductor revenues, which fell 5.1 percent sequentially, following the normal seasonal demand pattern.

“While overall chip revenue declined in the first quarter, falling inventories among chip suppliers—combined with expanding stockpiles at distributors, contract manufacturers and original equipment manufacturers (OEM)—indicate that consumer demand for electronics rose during the period,” said Sharon Stiefel, analyst for semiconductor market intelligence for IHS. “This contributed to a decline in chip inventories. At the same time, semiconductor companies maintained tight control over their manufacturing capacity, contributing to the decline in inventory.”

Signs of strength from PC and cellphone OEMs

Throughout the electronics supply chain, the largest increases in inventory were posted by cellphone and PC OEMs. Cellphone makers expanded their inventories—including finished smartphones—by 7.2 percent during the quarter. For their part, PC OEMs expanded their stockpiles of items including notebook and desktop computers by 6 percent.

The increase in OEM, contract manufacturing and distributor inventories during the first three months of the year contrasted sharply with the fourth quarter of 2012 when these segments trimmed their stockpiles.

“The rise in inventories among the various segments of the supply chain indicates the electronics industry is preparing for an increase in demand during the second half of 2013,” Stiefel said.

It’s the economy

Overall global economic indicators point to growth during the coming quarters, mainly in the developing nations. This is incentivizing semiconductor companies and their customers to load factories in the second quarter to keep up with the demand for second-half shipments.

Semiconductor inventory levels are expected to rise in the second quarter in response to the positive order rates from electronics equipment manufacturers, whereas stockpiles for consumers of semiconductors likely will remain fairly flat.

SEMATECH, the global consortium of semiconductor manufacturers, today announced that William R. Rozich has assumed the role of chairman of the board of directors. Rozich, who previously was a member of the company’s board, succeeds Michael R. Polcari, who served as chairman since November 2009.

“The strength and commitment of our board is a great advantage for SEMATECH and we welcome Bill to his role as chairman. His extensive industry experience, familiarity with the progressive developments of our industry in Albany, NY and his leadership and insights are valuable to SEMATECH and our members,” said Dan Armbrust, SEMATECH’s president and CEO.

“I am honored to serve as chairman of SEMATECH’s board,” said Rozich. “SEMATECH has been setting global direction through the facilitation of precompetitive collaboration among its members for over 25 years, and I look forward to building on that history and collaborating with our board to address the complex, ever-changing technology landscape and the unique needs of our members.”

Rozich, who begins his new role July 1, most recently served as the director of semiconductor operations of IBM Corporation at the College of Nanoscale Science and Engineering in Albany, New York. He has more than 30 years of semiconductor fabrication operations experience and extensive interactions with equipment and materials suppliers, as well as leading complex alliances.

Rozich began his career at IBM in 1974 and progressed through a variety of assignments in equipment engineering, manufacturing technology and alliance management. He previously served on SEMATECH’s Executive Technical Advisory Board from 1994 through July 2006, the I300I Executive Steering Committee from 1995 until December 2000, and as a SEMATECH board member from 2006 to 2010.

Rozich received his bachelor’s degree in biology and chemistry from Fordham University and Marist College, as well as a Master of Arts degree in chemistry from State University of New York at New Paltz.

Through a series of lectures and workshops, SEMATECH will address R&D challenges and closing key infrastructure technology gaps from July 8–12 at SEMICON West in San Francisco, CA.

SEMATECH experts will discuss the challenges which are affecting progress in next-generation lithography techniques, new materials and processes for sub-20nm manufacturing as well as present a variety of advances in new materials and device structures and lithography.

“In order to prepare for major industry transitions that will stress the industry’s resources over the next decade, we must evolve our infrastructure collaborations to address rapidly evolving technical and business model challenges,” said Dan Armbrust, president and CEO of SEMATECH.

On July 10, Armbrust will be participating in SEMI’s executive R&D panel, “A Conversation on the Future of Semiconductor Technology.” Collaborative research experts will address the technological and financial challenges in semiconductor design, process technology and manufacturing, and share how technical contributions and synergies from all sectors of the industry are required to achieve industry-wide goals.

SEMATECH experts who are scheduled to speak on the SEMICON West TechXPOT stage, in the North and South Halls of the Moscone Center include:

  • Paul Kirsch, SEMATECH’s director of Front End Processes, “Non-Silicon R&D Challenges and Opportunities,” July 9 at 11:30 a.m., South Hall
  • Stefan Wurm, SEMATECH’s director of Lithography, “EUV Lithography: Status and Outlook,” July 10 at 10:55 a.m., South Hall
  • Abbas Rastegar, SEMATECH Fellow “Challenges of Nanodefectivity,” July 10 at 11:50 a.m., North Hall
  • Mark Neisser, SEMATECH research manager, “ITRS Front End of Line Technologies: Lithography,” July 11 at 1 p.m., South Hall

Additionally, SEMATECH will host several public workshops at the San Francisco Marriott Marquis during SEMICON West:

  • Participants will address the challenges associated with infrastructure gaps, particle metrology and filtration for the reduction and prevention of nanoparticles in solutions at the SEMATECH Workshop on Nanoparticle Defectivity Issues in Solutions on July 9 at 8 a.m.
  • Equipment suppliers, semiconductor researchers and device manufacturers will discuss how they are applying new inspection and metrology technologies as well as modified or enhanced existing techniques to improve 3D interconnect processes at the SEMATECH Workshop on 3D Interconnect metrology on July 10 at 8 a.m.
  • Co-sponsored by SEMI and SEMATECH, the Enabling Supply Chain R&D through Collaboration Workshop will identify the most significant affordability challenges for semiconductor R&D and explore new collaborative opportunities that address these challenges on July 10 at 1:30 p.m.
  • A half-day preview of this year’s International Technology Roadmap for Semiconductors will be offered at the Summer ITRS Public Conference on July 11.

Some of SEMATECH’s most prominent technologists in the nanoelectronics industry will be attending SEMICON West. To arrange for meeting attendance or interviews with executives and technical experts, please contact [email protected].

 

IBM and United Microelectronics Corporation, a global semiconductor foundry, today announced that UMC will join the IBM Technology Development Alliances as a participant in the group’s development of 10nm CMOS process technology.

"Established over a decade ago, the IBM alliance allows the partners to leverage our combined expertise and collaborative research and innovative technology development to address the demanding needs for advanced semiconductor applications," said Gary Patton, VP, IBM Semiconductor Research & Development. "UMC is a strong addition to the alliance."

Po Wen Yen, CEO at UMC, added, "IBM is a recognized leader in fundamental semiconductor technology. We are extremely pleased to work jointly with IBM on advanced fundamentals, and to contribute our many years of experience in developing highly competitive manufacturing technology. Our role as one of the world’s top foundries requires us to introduce leading-edge processes in a timely manner to enable next generation customer chip designs. We look forward to collaborating closely with IBM, leveraging their deep technology expertise to shorten our 10nm and FinFET R&D cycles and create a win-win situation for UMC and our customers."

The agreements between UMC and IBM expand upon their 2012 agreements concerning prior nodes, including 14nm FinFET. With IBM’s support from this collaboration, UMC will continue to improve its internally developed 14nm FinFET to offer industry competitive low-power technology enhancements for mobile computing and communication products. The parties plan to develop baseline 10nm process technology to meet the needs of UMC customers. UMC will send an engineering team to join the 10nm development work that will take place in Albany, New York, while UMC’s 14nm FinFET and 10nm implementation will take place at UMC’s Tainan, Taiwan R&D site.

Fab equipment spending will grow two percent year-over-year  (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast. Fab construction spending, which can be a strong indicator for future equipment spending, is expected to grow 6.5 percent ($6.6 billion) in 2013, followed by a decline of 18 percent ($5.4 billion) in 2014. The new World Fab Forecast report covers fab information on over 1,140 facilities, including such details as capacities, technology nodes, product types, and spending for construction and equipment for any cleanroom wafer facility by quarter.

Fab equipment spending for the second half of 2013 is expected to be much stronger with a 32 percent growth rate or $18.5 billion compared to the first half of 2013. The equipment spending increase in the second half is attributed to growing semiconductor demand and improving average selling price for chips. 2014 is expected to have about 23 to 27 percent growth year-over-year (YoY) to reach about $41 billion, which would be an all-time record.

Looking at product types, the largest amounts of spending on fab equipment in 2013 will come from the foundry sector, which increases by about 21 percent. This is driven mainly by capex increases by TSMC. The memory sector is expected to have an increase of only one percent — after a 35 percent decline in the previous year. The MPU sector is expected to grow by about five percent. A double-digit increase in the Analog sector in 2013 will still translate into low absolute dollar amounts, compared to the other sectors.  

 

Construction spending is a good indicator for more equipment spending.  Fab construction spending in 2013 is expected to be almost 15 percent growth YoY ($6.6 billion) with 38 known construction projects. Top spenders for fab construction in 2013 are TSMC and Samsung, who plan to spend between $1.5 and $2 billion each, followed by Intel, Globalfoundries and UMC. The SEMI World Fab Forecast report reveals more detail.

2014 shows a decline of about 18 percent ($5.4 billion) in construction spending with only 21 construction projects expected to be on-going. These construction projects include large fabs; some are 450mm-ready. 

Since the last fab database publication at the end February 2013 SEMI’s worldwide dedicated analysis team has made 389 updates to 324 facilities (including Opto/LED fabs) in the database. The latest edition of the World Fab Forecast lists 1,144 facilities (including 310 Opto/LED facilities), with 61 facilities with various probabilities starting production this year and in the near future. Seventeen new facilities were added and 8 facilities were closed.

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs; and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter.