New flash memory chips are replacing the floating gate with thin layers of material that "trap the charge." The charge trap is a sandwich of materials such as silicon-oxide-nitride-oxide-silicon (SONOS), metal-oxide-nitride-oxide-silicon (MONOS) and tantalum-aluminum oxide-nitride-oxide-silicon (TANOS), all of which are substantially smaller than the floating gate.

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, researchers from Mila Polytechnic, Micron and Intel will present a paper titled "Resolving Discrete Emission Events: a New Perspective for Detrapping Investigation in NAND Flash Memories." The authors say their results provide important insights into the fundamental scaling challenges of aggressively-scaled NAND flash technologies, where the impact of single electrons and defects becomes increasingly important.

Charlie Slayman, IRPS Vice Technical Program Chair, said that researchers looked at the effects of individual discrete traps in the tunnel oxide for 30nm NAND flash (see figure).

Example of ΔVT, i and dti extraction from a detrapping VT transient.

"Looking at the threshold voltage over time, you can actually see the threshold voltage change in discrete quantized steps. They’ve analyzed this and determined these are individual traps in the device that are trapping and detrapping. This will have an impact on future flash technologies where single electron and defects become increasingly important," Slayman said.

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, imec will present new research focused on the stress induced breakdown between the tungsten trench local interconnects (M1, M2) and metal gate in a 28nm CMOS technology. Imec’s Thomas Kauerauf will present a paper titled “Reliability of MOL local interconnects.”

The researchers found that the breakdown voltage shows strong polarity dependence (see figure).

The breakdown voltage revealed significant polarity dependence. Here the VBD data with bias applied at IM1 or the gate is shown.

“This has profound implications for estimating the end-of-life, specifically in bipolar applications,” explained Giuseppe Larosa, IRPS Technical Program Chair. “Here, bipolar means the voltage between the gate and the drain can basically change polarity. That really depends on the situation where the gate can be high and the drain can be ground, or the gate can be ground and the drain can be high. When you’re switching, you are in that situation. The total end of life can be a mix between these two situations.”

The imec authors note that, due to overlay errors, the spacing between the gate and the contact varies, resulting in large VBD and tBD variability across the wafer. They have developed a methodology for an intrinsic TDDB lifetime extrapolation with uniformity correction.

New finFETs feature high-k dielectrics, which are better than conventional silicon nitride dielectrics in that they can be thinner, yet still enable good control of the transistor’s channel region from the gate. Although high-k materials have been in use for five years or more, new reliability concerns associated with their use in finFETs have arisen, particularly bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB).   

"There are two aspects of high k dielectrics that people have to face," said Giuseppe Larosa, IRPS Technical Program Chair. "BTI is again a concern with continued scaling. The second new effect of using high-k oxides is the TDDB physics is really completely different than nitride oxides. There’s been a lot of controversy on how to describe the TDDB for high-k in recent years.”

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, GLOBALFOUNDRIES will present the first large-scale stochastic BTI (particularly PBTI) study in metal gate/high-k technology, confirming fundamental BTI area scaling trends derived from conventional SiO₂ technologies, and IBM will report on TDDB in high-k, and how it will lead to more accurate models.

“Contrary to nitride oxides, high-k brings a higher sensitivity of the NFET devices to PBTI. This is mostly due to the face that the high-k material can be sensitive to electron trap activation or generation so producing PBTI effects that you will not see in standard nitride oxide technologies,” Larosa said. “While in nitride oxide, NBTI is the main BTI mechanism that drives PFET aging, in high-k materials it’s both NBTI for PMOS and PBTI for NMOS that is actually producing some BTI aging.”

In a paper titled “Challenges in the characterization and modeling of BTI induced variability in Metal Gate / High-k CMOS technologies,” GLOBALFOUNDRIES researchers show that PBTI in the NFET is similar to NBTI in the pFET, but with a different type of permutation (see figure).

“The actual distribution shows a slightly different trend than the NBTI distribution,” Larosa said.  But everything can be normalized and scaled exactly the same way.

In another paper, titled “A New Formulation of Breakdown Model for High-k/SiO₂ Bilayer Dielectris,” researchers from IBM show that breakdown can happen slowly.

“Gate leakage is actually starting to progressively increase until you’re going to get a hard breakdown,” Larosa said. “The distribution in the case is really bimodal. You have completely different behavior between when the first breakdown takes place versus when the oxide breakdown is actually evolving into the hard breakdown. The challenge here has been how to simulate this. This works suggest that it can be done with a Monte Carlo simulation that is based on dual-layer percolation statistical model. Why is this important? Because without this model you cannot be confident in predicting end of life, and having this type of simulation can help in making that projection that can be relevant for product level of circuit level reliability.”

The first large-scale stochastic BTI study in metal-gate/high-k transistors shows that PBTI in the NFET is similar to NBTI in the pFET, but with a different type of permutation.

It’s well-known that transistors generate heat when they’re operating, and that can have a significant impact on the chip’s reliability and longterm longevity. A small increase of 10°C–15°C in the junction temperature may result in ∼ 2× reduction in the lifespan of the device.

In conventional bulk transistors, self-heating is controlled in that the heat moves away down into the bulk of the devices. In newer FinFETS, however, it could pose a serious problem because there’s nowhere for the heat to go. 

“In finFETs, because it’s a three-dimensional structure, this self-heating is a bottleneck in scaling down,” said Giuseppe Larosa, Technical Program Chair of the IRPS. “Self-heating become a key important issue. The International Reliability Physics Symposium (IRPS) is being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA.

At IRPS, Intel will present new research in a paper titled “Self-heat Reliability Considerations on Intel’s 22nm Tri-Gate Technology.” This work elaborates on various measurements to observe self-heating as well as the associated reliability implications, not only in the transistors, but the overlying metal lines. “The self-heating of the finFET can locally increase the temperature in the metal wires above, enhancing  electromigration effects,” Larosa said.

Self-heating effects are investigated at various locations in the tri-gate architecture and in long metal lines with multiple finFETs underneath.  FinFET local temperature rise was linear with power and independent of gate stack (predicted by thermal modeling).  A linear trend for metal lines local temperature rise is observed as function powered FinFETs segments.

Intel emphasized the importance of well-calibrated self-heat models for process optimization for cutting-edge performance and reliability. They showed that aging during switching events is affected by local self-heat and shows sensitivity to number of fins or gate lines (see figure). 

“To calibrate the self-heating, you have to make sure that you have a good understanding of the local temperature in the structure that is under investigation,” Larosa said. “The figure shows self-heating at the device level is affecting aging of a given FET. It’s a function of the number of fins and the number of active lines per transistor. “

Self-heat manifests as a sensitivity to the fin or gate count in switching aging degradation. Here, switching conditions are accelerated to enhance the sensitivity.

FinFETs offer several advantages compared to traditional planar transistors, but it’s not yet clear what kind of new reliability problems might arise as FinFETs are scaled to smaller dimensions. One concern is what impact bias temperature instability (BTI), particularly negative BTI (NBTI), might have on FinFETs.

In p-channel transistors, NBTI affects small feature size devices and is quite difficult to reduce or eliminate. As feature sizes become smaller, the effects of NBTI become more pronounced, resulting in increases in threshold voltage and decreases in drain current and transconductance in p-channel devices. NBTI results from a positive charge buildup in p-channel transistors. It occurs at low negative gate-to-source voltages and does not result in an increase in gate leakage current. Rather, it affects off-state drain-to-source leakage and reduces the drive current. Generally, this problem is worse than standard hot carrier degradation because it results in permanent interface traps being generated, reducing device lifetime.

At the International Reliability Physics Symposium (IRPS), being held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA, Intel will present a paper titled “Intrinsic Transistor Reliability Improvements from 22nm Tri-Gate Technology” that shows that FinFETs have a similar total BTI budget at application condition but, while NMOS PBTI can be reduced to near-negligible levels, NBTI sensitivity seems to increase with scaling.

Giuseppe Larosa, IRPS Technical Program Chair said that “Intel’s data suggest that when you look at the total BTI budget, it seems to be even in the finFET world, going from 32 seems to be pretty much okay, but NBTI seems to be an issue because it’s increasing with finFET scaling.” What Intel did was to compare a 32nm planar technology to 22nm finFET technology. The figure shows that 32nm technology in red and the 22nm finFET technology in blue. “You can see that they can manage to really reduce the PBTI, but the NBTI is actually getting worse with scaling,” Larosa said. “NBTI is becoming one of the key challenging issues for finFETs.”

22nm BTI is comparable to 32nm. NMOS is significantly improved due to gate optimization and WF scaling.

ARM and TSMC today announced the first tape-out of an ARM Cortex-A57 processor on FinFET process technology.  The Cortex-A57 processor is ARM’s highest performing processor, designed to further extend the capabilities of future mobile and enterprise computing, including compute intensive applications such as high-end computer, tablet and server products.  This is the first milestone in the collaboration between ARM and TSMC to jointly optimize the 64-bit ARMv8 processor series on TSMC FinFET process technologies.  The two companies cooperated in the implementation from RTL to tape-out in six months using ARM Artisan physical IP, TSMC memory macros, and EDA technologies enabled by TSMC’s Open Innovation Platform (OIP) design ecosystem.

ARM and TSMC’s collaboration produces optimized, power-efficient Cortex-A57 processors and libraries to support early customer implementations on 16nm FinFET for high-performance, ARM technology-based SoCs.

“This first ARM Cortex-A57 processor implementation paves the way for our mutual customers to leverage the performance and power efficiency of 16nm FinFET technology,” said Tom Cronk, executive vice president and general manager, Processor Division, ARM.  “The joint effort of ARM, TSMC, and TSMC’s OIP design ecosystem partners demonstrates the strong commitment to provide industry-leading technology for customer designs to benefit from our latest 64-bit ARMv8 architecture, big.LITTLE processing and ARM POP IP across a wide variety of market segments.”

“Our multi-year, multi-node collaboration with ARM continues to deliver advanced technologies to enable market-leading SoCs across mobile, server, and enterprise infrastructure applications,” said Dr. Cliff Hou, TSMC Vice President of R&D. “This achievement demonstrates that the next-generation ARMv8 processor is FinFET-ready for TSMC’s advanced technology.”

This announcement highlights the enhanced and intensified collaboration between ARM and TSMC. The test chip was implemented using a commercially available 16nm FinFET tool chain and design services provided by the OIP ecosystem and ARM Connected Community partners. This successful collaborative milestone is confirmation of the roles that TSMC’s OIP and ARM’s Connected Community play in promoting innovation for the semiconductor design industry.