Category Archives: Metrology

Integration is a feature we all look for in our electronic devices. Information readily available on our smart phones is integrated with web-based services and with our personal data on our home computer.  This interoperability that we take for granted is thanks to common software and hardware platforms that are shared by all the elements of this system. Platforms surround us everywhere in our daily lives – the specific model of the car we drive is built on a platform, the electrical systems in our house are on a platform: 110/220V with universal plugs. Platforms?! So I got curious and looked up a more formal definition on Wikipedia:

Platform technology is a term for technology that enables the creation of products and processes that support present or future development.

Why has the concept of platforms been on my mind? Because I hear it more and more often from engineers in the trenches of the post-tapeout flow – people who develop the data preparation sequences that ready their design for manufacturing. They say it is getting increasingly complicated to accommodate all the functional requirements and still meet the TAT (turn-around-time) requirements.  The 20nm node adds additional complexity to this flow – beyond retargeting, etch correction, fill insertion, insertion of assist features and the application of optical proximity correction– now decomposition-induced steps are required and replicate some of the steps for both layers.  Industry standards like the OASIS format enable the communication between independent standalone tools, but are not enough to enable extension in new functional areas and maintain a steady overall runtime performance. Users have to be familiar with all the features and conventions for each tool – not an efficient way to scale up an operation.

The oldest and most versatile platform in computational lithography is Calibre. It started with a powerful geometry processing engine and a hierarchical data base and is accessed through an integrated scripting environment using the Tcl-based  standard verification rule format (SVRF) and the Tcl verification format (TVF). As the requirements for making a design manufacturable with available lithography tools has grown, so has the scope of functionality available to lithographers and recipe developers. APIs have expanded the programming capabilities: the Calibre API provides access to the data base, the lithography API provides access to the simulation engine, the metrology API enables advanced programming of measurement site selection and characterization, the fracture API enables custom fracture (Figure 1). All of these functions let you both build data processing flows that meet manufacturing needs and encode your very own ideas for the most efficient data processing approach. The additional benefit of a unified platform is that it also enables the seamless interaction and integration of tools in a data processing flow. If you can cover the full flow within one platform, rather than transferring giant post-tapeout files between point tools, you will realize a much faster turn-around time.

Common workflow
Figure 1: All tools in the Calibre platform are programmed using the SVRF language and tcl extensions and can be customized via a number of APIs – maintaining a common and integrated workflow.

A platform like Calibre is uniformly used in both the physical verification of the design and in manufacturing, so that innovation entering the verification space flows freely over to the manufacturing side without rework and qualification. Examples include the smart fill applications and the decomposition and compliance checks for double-patterning (DP).

The benefits to using a unified software platform in the post-tapeout flow, illustrated in Figure 2, are also leveraged by the EDA vendor—our software developers use the common software architecture in the platform for very fast and efficient development of new tools and features. This reduces the response time to customer enhancement requests. New technology, like model-based fracture and self-aligned double patterning (SADP) decomposition, were rapidly prototyped based on that.

Calibre workflow
Figure 2: Benefit and scope of a platform solution and the support level provided by Calibre.  

 

A platform not only provides the integration and efficient operation at the work-flow level, but it also enables efficiency at the data-center level, considering the simultaneous and sequential execution of many different designs and computational tasks. The tapeout manufacturing system is a complex infrastructure of databases, planning, and tracking mechanisms to manage the entire operation. Common interfaces into the tools used –which are guaranteed by a platform solution–let you track data and information associated with each run and manage interactions and feedback across different jobs.  This leads, for example, to an improved utilization of the computer system overall as well as better demand and delivery forecasting. Operating a manufacturing system requires a different level of support than single tool solutions and the necessary infrastructure has evolved with the development of the components.

Once you start using a unified platform in your post-tapeout flow, you will see how the platform expands and grows. For today’s sub-nanometer technologies, a powerful and flexible platform for computational lithography is part of a successful business strategy.

Author biography

Dr. Steffen Schulze is the Product Management Director for the Mentor Graphics’ Calibre Semiconductor Solutions. He can be reached at [email protected].

Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion, according to the 2013 edition of IC Insights’ McClean Report.  The increase lifted R&D spending by chip companies to 16.7% of total semiconductor sales in 2012, the highest level since the peak of 17.5% was reached in both 2008 and 2009.

For more than three decades, R&D spending as a percentage of total semiconductor sales has trended higher due to increasing costs associated with developing complex IC designs and creating next-generation process technologies to manufacture these circuits.  In the late 1970s and early 1980s, R&D spending as a percent of semiconductor sales by chip companies was typically 7-8%.  R&D-to-sales ratios grew to 10-12% of revenues by the early 1990s and then jumped to over 15% during the last decade, reaching a record 17.5% in 2008.

However, as shown in Figure 1, not all companies have seen a growing portion of sales consumed by R&D.  For example, Samsung’s R&D-to-sales ratio fell from a peak of 25% in 2001 to 8% in 2010 and has remained there since.  

Samsung’s semiconductor business is more capital-intensive than it is R&D-intensive because of the commodity nature of the DRAM and flash memory businesses in which it mainly participates.  As a result, since 2001, Samsung’s semiconductor sales have grown an average of 16% per year, while its R&D spending has increased at about one-third the rate (5%) and it’s capital expenditures have grown by an average of 19% annually.  The main focus of Samsung’s investments is in adding new fab capacity for large-diameter wafers (currently 300mm but heading toward 450mm later this decade).

Intel’s business is also capital-intensive.  Its spending on new fabs and equipment in each of the past two years was about $11 billion, which was only about $1 billion shy of what Samsung spent in each of those years.  Intel’s advanced microprocessors and other incredibly complex logic devices have very short life cycles.  Spending large amounts of money on research and development is part of its business model.  Intel’s $10.1 billion in semiconductor R&D spending in 2012 was more than 7x the amount spent by second-place Qualcomm!  In fact, Intel spent more than one-third of the combined $28.7B spent by the top-10 R&D spenders in 2012, according to the 2013 McClean Report.

Figure 1 also shows how much the industry’s largest pure-play foundry, TSMC, has been spending on R&D as a percent of sales over the past decade-and-a-half.  As the process technology needed for each new generation of ICs has become increasingly difficult to develop, fabless companies and the growing number of fab-lite companies have come to rely on TSMC not only for fabricating their wafers, but also for helping to bring their IC designs into existence.  As a result, TSMC’s R&D spending-to-sales ratio has been gradually climbing over the past 6-8 years.  TSMC’s spending ratio reached 8% in 2001, but that had a lot to do with the fact that its sales were hit hard by the industry recession that year.  Aside from a small dip in 2009, TSMC’s spending on R&D has grown every year since 1998 and at an average annual rate of 25%!  Over that same 1998-2012 timeperiod TSMC’s sales grew an average rate of 19% per year.

KLA-Tencor Corporation (NASDAQ: KLAC) announced the eS805, a new electron-beam inspection system capable of detecting very small defects, and defects that cause electrical problems such as opens, shorts or reliability issues. The eS805 is also designed to provide supplementary information to the fab’s optical inspection systems, with the goal of boosting the ability of the optical inspectors to preferentially capture defects that matter.

Bobby Bell, executive vice president of KLA-Tencor’s Wafer Inspection Group, said: "We believe that optical inspection will continue as the dominant defect inspection approach; its speed is essential for adequate wafer coverage, and our engineers have demonstrated some impressive ideas for stretching optical sensitivity to meet our customers’ anticipated requirements. Electron-beam inspection will continue to complement optical inspection as needed..”

The high performance of the new eS805 is driven by the following advances:

  • New image computer, new auto-focus subsystem, and higher beam current densities than other commercially available systems, enabling detection of buried electrical defects in "voltage contrast" ("VC") mode over relatively large areas of the die;
  • Architecture designed to elicit significant signal from defects hidden at the bottom of high aspect ratio (HAR) structures such as FinFETs and 3D flash; and
  • Advanced algorithms that, together with the new image computer and auto-focus system, enable efficient capture of small defects within non-periodic structures, such as logic areas of the cell.

The eS805 is upgradeable from any previous eS3x or eS8xx-series e-beam inspection system.

New eS805 e-beam inspection systems have been shipped to leading logic and memory chip manufacturers, where they are being used to upgrade existing e-beam inspection capability or to fulfill requirements for additional inspection capacity in advanced development and production lines. To maintain high performance and productivity, the eS805 tools are backed by KLA-Tencor’s global, comprehensive service network. 

ProPlus Design Solutions, Inc., announced it is shipping a new wafer-level, 1/f noise measurement system. Increasingly, circuit designers are interested in 1/f noise data at higher frequencies. They are concerned also about variation effects at leading-edge process nodes, increasing the need for statistical noise models. Generating statistical noise models requires massive amounts of data collection that is particularly challenging at low frequencies.

The 9812D low-frequency 1/f noise measurement system is designed to measure low-frequency noise characteristics of on-wafer or packaged semiconductor devices, including MOSFETs, bipolar junction transistors (BJTs), junction field effect transistors (JFETs), diodes and diffusion resistors. In addition to frequency domain measurement, 9812D can measure device noise in the time domain and can be used to perform on-wafer auto measurement for flicker (1/f) noise and Radom Telegraph Signal (RTS) analyses.

9812D improves upon 9812B, the company’s 1/f measurement system used for more than a decade by foundries, integrated device manufacturers (IDMs) and research organizations. The system, which has a frequency range that exceeds 10 Megahertz (MHz), has a built-in dynamic signal analyzer (DSA) with multi-threaded processing for improved performance and reduced cost.

“Noise is a key figure of merit for semiconductor process quality and also an intrinsic characteristic impacting circuit performance,” said Dr. Zhihong Liu, executive chairman of ProPlus Design Solutions. “To meet the new challenges at 28 nanometer and beyond, we worked with leading foundries on significant improvements of the 1/f system.”

Wafer fabrication facilities use 7*24 1/f noise measurement data to assess process quality. A three-to-10X throughput improvement of the 9812D system means faster data collection and early detection of process issues.

When a 300mm wafer is vacuum mounted onto the chuck of a scanner, it needs to be flat to within about 16nm over a typical exposure field, for wafers intended for 28nm node devices.1 A particle as small as three microns in diameter, attached to the back side of the wafer—the dark side, if you will—can cause yield-limiting defects on the front side of the wafer during patterning of a critical layer. The impact of back side particles on front side defectivity becomes even more challenging as design rules decrease.

Studies have shown that a relatively incompressible particle three microns in diameter or an equivalent cluster of smaller particles, trapped between the chuck and the back surface of the wafer, can transmit a localized height change on the order of 50nm to the front side of the wafer.2 With the scanner’s depth-of-focus reduced to 50nm for the 28nm node, the same back side particle or cluster can move the top wafer surface outside the sweet spot for patterning. The CD of the features may broaden locally; the features may be misshapen. The result is often called a defocus defect or a hotspot (Figure 1). These defects are frequently yield-limiting because they will result in electrical shorts or opens from the defective feature to its neighbors.

A particle on the back side of the wafer may remain attached to the wafer, affecting the yield of only that wafer, or it may be transferred to the scanner chuck, where it will create similar defects on the next wafer or wafers that pass through the scanner.

At larger design nodes, back side defects were not much of an issue. The scanner’s depth of focus was sufficient to accommodate a few microns of localized change in the height of the top surface of the wafer. At larger design nodes, then, inspection of the back side of the wafer was performed only after the lithography track and only if defects were found on successive wafers, indicating that the offending particle remained on the scanner chuck, poised to continue to create yield issues for future wafers. In this case corrective measures were undertaken on the track to remove any suspected contamination. The track was re-qualified by sending another set of wafers through it and looking for defectivity at the front side locus of the suspected back side particle. This reactive approach was economically feasible for most devices throughout volume production of 32nm devices.

At the 28nm node, however, lithography process window requirements are such that controlling back side particles requires a more proactive approach. Advanced fabs now tend to inspect the wafer back side before the wafer enters the scanner, heading off any potential yield loss. Scanner manufacturers are also encouraging extensive inspection of the back side of wafers before they enter the track. As we see what lithography techniques unfold for the 16nm, 10nm nodes and beyond, it’s entirely possible that 100% wafer sampling will become the best-known method.

As with inspection of the front side of the wafer, sensitivity to defects of interest (DOI) and the ability to discriminate between DOI and nuisance events are important. Even though particles need to be two to three microns in diameter before they have an impact on front side defectivity, the inspection system ought to be able to detect sub-micron defects, since small defects can agglomerate to form clusters of critical size. Sub-micron sensitivity is beneficial for identifying process tool issues based on the spatial signature of the defects—while high-resolution back side review enables imaging of localized defects, so that appropriate corrective actions can be taken to protect yield. Sub-micron sensitivity also serves to extend the tool’s applicability for nodes beyond 28nm.

For further information on back side inspection equipment or methodologies, please consult the second author.

Rebecca Howland, Ph.D., is a senior director in the corporate group, and Marc Filzen is a product marketing manager in the SWIFT division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

Notes:

1.       Assuming 193nm exposure wavelength, NA = 1.35 and K2 = 0.5, then depth of field = 50nm. Normally 30% of the DOF is budgeted for wafer flatness.

2.       Internal studies at KLA-Tencor.

IBM (NYSE: IBM) Research scientists Gerhard Meyer, Leo Gross, and Jascha Repp have been awarded the prestigious 2012 Feynman Prize for Experiment by the Foresight Institute at its annual conference.

IBM Researchers Gerhard Meyer, Leo Gross (pictured) and Jascha Repp (now at Regensburg University) won the prestigious Feynman prize given by the Foresight Group. The team of research scientists was the first to produce images detailed enough to identify the structure of individual molecules, as well as metal-molecule complexes. They have also been able to accurately deconstruct individual chemical bonds which provide key insights into designing future molecular systems and nano scale devices.

According to a statement by the Foresight Institute, the Prize recognizes the scientists for their remarkable experiments in advancing the frontiers of scanning probe microscopy. They were the first to produce images of molecular orbitals and charges detailed enough to identify the structure of individual molecules, as well as metal–molecule complexes. They have also been able to precisely make and break individual chemical bonds. These developments provide crucial insights and tools for the design of future molecular systems.

In his laudation Ralph C. Merkle, Chairman of the Prize Committee, said "The work of these Feynman Prize winners has brought us one step closer to answering Feynman’s 1959 question, ‘What would happen if we could arrange atoms one by one the way we want them?’ And the ability to simulate and manipulate atoms advanced by the work of these Prize winners will enable us to design and build engineered molecular machinery with atomic precision. It will take us another step on the way to the development of revolutionary nanotechnologies that will transform our lives for the better."

The awards were presented at the 2013 Foresight Technical Conference in Palo Alto, California.

The Foresight Feynman Prizes were established by the Foresight Institute in 1993. They are named in honor of Nobel Prize laureate Richard Feynman, whose influential essay entitled "There’s Plenty of Room at the Bottom" inspired the first work on nanoscale science. The Institute awards Feynman prizes each year to recognize researchers—one for theoretical work and one for empirical research—whose recent work has most advanced the field toward the achievement of Feynman’s vision for nanotechnology: molecular manufacturing, the construction of atomically precise products through the use of molecular machine systems.

January 11, 2012 – GlobalFoundries says it plans to build a $2 billion R&D facility at its Fab 8 campus in Saratoga County, NY. The new Technology Development Center (TDC) will span more than 500,000 sq. ft of "flexible space" for various technology development and manufacturing activities, including cleanroom and lab space. Construction is planned to begin in early 2013 and completed in late 2014.

The TDC will focus on a variety of semiconductor development and manufacturing work "to support the transition to new technology nodes," and development of "innovative capabilities to deliver value to customers beyond the traditional approach of shrinking transistors," according to the company. Broadly speaking, the TEC is planned to be a collaborative space to develop "end-to-end solutions covering the full spectrum of silicon technology," from EUV lithography photomasks to new interconnect and packaging technologies enabling 3D chip stacking, "and everything in between."

"As the industry shifts from the PC era to a market focused on mobile devices, we have seen increasingly strong interest from customers in migrating to advanced nodes on an accelerated schedule," stated GlobalFoundries CEO Ajit Manocha. "To help facilitate this migration, we are making significant investments in strengthening our technology leadership, including growing our workforce and adding new capabilities to make Fab 8 the hub of our global technology operations." Toward that end, "the new TDC will help us bridge between the lab and the fab by taking research conducted with partners and further developing the technologies to make them ready for volume manufacturing," he added

Other regional New York State leaders chimed in with appreciation and optimism for the project’s synergy with the local and regional economy. "New York has become the world’s hub for advanced semiconductor research and now, the Technology Development Center will further help ensure the innovations developed in New York, in collaboration with our research institutions, are manufactured in New York," said Governor Andrew M. Cuomo. "New York State’s public investments to develop CNSE as a hub of innovation coupled with the private investments of GLOBALFOUNDRIES are prime examples of best practices for public-private partnerships linking research, innovation and production that have made New York a globally recognized center of innovation," added Charles W. Wessner, director of the National Academies’ Innovation Program.

GlobalFoundries began developing its Fab 8 project in the summer of mid-2009; today its campus includes approximately 2 million sq. ft of development. The company has continued to make investments in manufacturing production as well as technology development, including work underway on 20nm and 14nm technology nodes.

January 9, 2012 – SEMI’s HB-LED Standards Committee has approved its first standard, specifying sapphire wafers used in making high-brightness light-emitting diode (HB-LED) devices.

Sapphire wafers are used in producing HB-LED devices for multiple applications: LCD backlights, signage and solid-state lighting. Development of industry standards, in collaboration with the global LED manufacturing supply chain, will help eliminate costs and better enable equipment and process innovation.

Five categories of single-crystal, single-side polished c-axis sapphire wafers are covered by the new HB1 standard:

  • Flatted 100mm diameter, 650μm thick,

  • Flatted 150mm diameter, 1,000μm thick,

  • Flatted 150mm diameter, 1,300μm thick,

  • Notched 150mm diameter, 1,000μm thick, and

  • Notched 150mm diameter, 1,300μm thick

SEMI’s HB-LED Standards Committee was formed in late 2010, comprised of companies involved in HB-LED devices, sapphire wafers, MOCVD wafer processing, and equipment and materials suppliers. Among its various individual efforts:

— The HB-LED Wafer Task Force already is seeking refinements to the HB1 standard, including specs for patterned sapphire substrates, double-sided polished wafers, impurities and defects (wafer and bulk), laser marking and identification, and bow and warp measurements. This group also is beginning a second round of experiments with wafer marking to characterize mark survivability, width, and depth; a first round conducted this year "showed promising results" on 100mm and 150mm wafers with front and back-surface marks (i.e., data matrix and OCR) were subjected to various surface modifications (e.g., slicing, grinding, polishing, GaN Ep). For 2013, the group plans to explore core and wafer defect inspection on ultrasonic technology, and conduct surveys on patterned sapphire substrates and double-side polishing.

— The HB-LED Equipment Automation Task Force plans to reballot a SEMI Draft Document on cassettes for 150mm sapphire substrates, seeking revisions to allow interoperability with existing equipment, taking into account cassette pocket size and spacing. This also will help standardization of load ports and transport systems.

— Meanwhile, a Software Working Group continues to develop a spec for an automation communication interface between process, automation, and metrology equipment. Another new standard, submitted and approved last October at the SEMI NA Standards Fall 2012 meetings, builds on that automation spec to address materials management and job management.

SEMI also plans to begin experiments and test methods based on a survey deployed last summer about defect vs. inspection techniques, aiming to identify sapphire wafer defects and inspection techniques catering to HB-LED manufacturing.

The wafer, automation, and impurities/defects task forces will be meeting at the Strategies in Light conference Feb. 12-14 in Santa Clara, CA. The NA HB-LEB committee and task forces will meet at the NA Standards Spring 2013 meetings April 1-4 in San Jose.

By Dr. Ravi Kanjolia, Chief Technology Officer, SAFC Hitech

We are in an age where chemistry is center stage in the race to advance Moore’s Law and More Than Moore. The continued drive towards smaller feature sizes, increased performance, and lower power consumption requires highly complex architectures using new materials and advanced process technologies. This is primarily true for processes in which physical vapor deposition (PVD) is being displaced by atomic layer deposition (ALD) and chemical vapor deposition (CVD). For example, materials are being developed to form high purity functional layers for applications in logic, memory, and interconnect areas, all within given thermal budgets. In many cases, the CVD process for extremely high-performance applications requires alternative chemistries to fabricate metal and dielectric layers at lower temperatures. All of this begins with the development of base chemistries for high-purity precursors and the R&D support to progress these materials to commercial maturity.  Additionally, the importance of further optimizing cost-of-ownership (COO) and efficiencies of high-purity materials used in semiconductor and LED manufacturing cannot be understated. In low-margin, high-volume product lines you compete on operational efficiency, not necessarily on innovation. This will require close collaboration between materials manufacturers, equipment suppliers, OEMS, IDMs, and foundries; the complexity of the products requires the entire value chain to work together.

While there is some industry-wide sentiment about lackluster CAPEX in 2013, we are positive about growth in the materials market segment. There has already been a noticeable increase in utilization rates across semiconductor manufacturing lines, as ever smaller feature sizes required for advanced CMOS and beyond CMOS technologies fall more on the shoulders of materials providers than equipment manufacturers. Therefore, demand for advanced chemistries is expected to increase even beyond that observed in 2012, and we expect much of that growth to come from Korea and the Chinese-speaking world.

Looking ahead to 2013 and beyond, the future is bright for the semiconductor materials market.  Roadmaps for advanced chemistries that will address the needs of next generation semiconductor manufacturing should reflect that.

The International Data Corporation (IDC) is forecasting that semiconductor revenues worldwide will improve by 4.9% to $319 billion in 2013 and log a compound annual growth rate (CAGR) of 4.1% from 2011-2016, reaching $368 billion in 2016. Bright spots for the semiconductor market include smartphones, tablets, set-top boxes, and automotive electronics, which IDC expects will continue to be key drivers of growth over the coming years.

The group said that 2012 saw a nominal growth of less than 1% reaching $304 billion, due to weakness in PC demand, DRAM and overall memory price deterioration, and semiconductor inventory rationalization. This was coupled with continued global macroeconomic uncertainty from lower global GDP growth, a slowdown in China, the Eurozone debt crisis and recession, Japan’s recession, and ongoing fear of fiscal cliff negotiations’ impact on IT spending by corporations.

IDC expects semiconductor inventories to come into balance with demand in the second quarter of 2013 with growth to resume in the second half of 2013. "We expect lower, but positive global GDP growth in 2013. Semiconductors for smartphones will see healthy revenue growth as appetite for data, multimedia processing, and multitasking will drive high-end smartphone demand in developed countries while an ongoing transition to 3G networks will accelerate smartphone adoption in developing regions. PC demand will continue to remain in a period of transition next year until more technology and design innovation begin to change the course of demand," said Mali Venkatesan, research manager for semiconductors at IDC.

Regionally, Japan and Europe continue to be the two weakest regions. Although GDP growth has slowed in China, India, and Brazil, demand for smartphones, tablets, and automotive electronics remains strong. In the U.S., 4G phones, mobile consumer devices (tablets and e-readers), network infrastructure, and set-top box deployments will drive a healthy semiconductor growth cycle over the next five years.

Other key findings from IDC’s Semiconductor Application Forecaster include:

  • Semiconductor revenues for the Computing industry segment will log year-over-year growth of 1.7% for 2013 and will show a muted CAGR of only 1.7% for the 2011-2016 forecast period. Semiconductor revenues from mobile PC demand will register 5.5% year-over-year growth in 2013, after declining 7.7% in 2012.
  • Semiconductor revenues for the Communications segment will grow 6.5% year over year in 2013 with a five-year CAGR of 5.5%. Semiconductor revenues for 4G phones will experience annual growth of 140.1% in 2013 and a CAGR of 103.4% for 2011-2016.
  • Media tablets, e-Readers, set-top boxes, and blu-ray players, will continue to see above average semiconductor revenue growth. Sales of traditional devices such as DVD players, DVD recorders, DVD players, portable media players, and game consoles will continue to erode. Overall, semiconductor revenues for the Consumer segment will record year-over-year growth of 9.8% in 2013 and a 2011-2016 CAGR of 6.0%.
  • Driven by strong global demand for automobiles and increased semiconductor content (i.e. applications such as in-vehicle infotainment, automobile body electronics, and driver safety systems), semiconductor revenues for the Automotive segment is expected to grow 5.9% (CAGR) for the five-year forecast period.
  • Regionally, Asia/Pacific will continue to grow its share of semiconductor revenues, with year-over-year growth of 5.5% in 2013 and a five-year CAGR of 5.3%.

IDC’s Worldwide Semiconductor Applications Forecaster database serves as the basis for all IDC semiconductor supply-side documents, including market forecasts and consulting projects. This database contains revenue data collected from the top 100 semiconductor companies for 2006-2011 and market history and forecasts for 2006-2016. Revenue for over twelve semiconductor device areas, four geographic regions, six industries, and more than 80 end-device applications are also included in the database.