Category Archives: Metrology

KLA-Tencor Corporation (NASDAQ: KLAC) has announced plans to establish a research-and-development (R&D) center in Ann Arbor, Michigan. The development is expected to include a total capital investment of more than $70 million and create up to 500 new high-tech jobs in the region over the next five years.

“Among the reasons for building a major R&D hub in the Ann Arbor and Detroit metropolitan area are the region’s attractive talent pool, relative low cost of living and proximity to Detroit Metropolitan Airport,” said Bobby Bell, chief strategy officer. “Our plan is to develop innovative solutions that will have an impact across a broad spectrum of semiconductor and electronics applications, including data storage, cloud computing, machine learning and automotive.”

“We’re confident that we can continue to create and deliver impactful technologies that ultimately help enrich the human experience. Our expansion into Michigan will help us realize our vision,” said Rick Wallace, chief executive officer. “This location also allows the company to strengthen our long-term partnership with the University of Michigan, including engaging in collaborative research.”

Semiconductor manufacturing to support the growing automotive electronics industry requires improved device reliability and defect control. In addition, the expanding applications of artificial intelligence (AI) and machine learning are driving strong demand for compute power and memory. Semiconductor manufacturers serving these diverse needs are turning to KLA-Tencor’s advanced process control solutions and services to help address their complex challenges.

KLA-Tencor’s decision to build a new location is founded upon a need to serve growing demand from its global customer base, while expanding the company’s footprint in North America.

The project was conceived in partnership with Michigan Economic Development Corporation and approved by the Michigan Strategic Fund.

North America-based manufacturers of semiconductor equipment posted $2.09 billion in billings worldwide in September 2018 (three-month average basis), according to the September Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 6.5 percent lower than the final August 2018 level of $2.37 billion, and is 1.8 percent higher than the September 2017 billings level of $2.05 billion.

“Quarterly global billings of North American equipment suppliers experienced their typical seasonal weakening in the most recent quarter,” said Ajit Manocha, president and CEO of SEMI. “Relative to the third quarter, we expect investment activity to improve for the remainder of the year.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg.)
Year-Over-Year
April 2018
$2,689.9
25.9%
May 2018
$2,702.3
19.0%
June 2018
$2,484.3
8.0%
July 2018
$2,377.9
4.8%
August 2018 (final)
$2,236.8
2.5%
September 2018 (prelim)
$2,091.9
1.8%

Source: SEMI (www.semi.org), October 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ).

By Jay Chittooran

Last week, the Office of the U.S. Trade Representative (USTR), on instruction from President Trump, notified Congress that the administration intends to begin bilateral trade negotiations with Japan, the European Union (EU), and the United Kingdom.

SEMI stands strong for free trade and open markets, and roundly supports efforts to increase market access and tap into more foreign economies, especially economies like Japan and the EU, both of which are central to the semiconductor industry. The semiconductor industry, which enables the $2 trillion electronics market, is built on global commerce. SEMI members rely on a vast network of supply chains that span the globe, bringing together components and tools made all around the world and assembled into a single sub-system that is then integrated into a larger tool used in the chipmaking process.

These free trade agreements will reduce tariffs, which will result in cost savings and productivity gains, and allow SEMI members to expand and grow. But the benefits of modern free trade agreements extend well beyond tariff reduction. Indeed, these trade deals will establish and enhance global trade rules that enable companies to innovate and compete fairly on a level playing field. Trade agreements strengthen certainty and further business continuity.

While the exact nature and negotiation timelines for the talks remain unclear, SEMI will engage the administration, urging it to maintain high standards in these agreements, such as:

  • Maintain strong respect for intellectual property and trade secrets through robust safeguards and significant penalties for violators
  • Remove tariffs and non-tariff barriers on semiconductor products as well as products that depend on semiconductors
  • Simplify and harmonize the customs and trade facilitation processes
  • Combat any attempts of forced technology transfer
  • Prevent use of data localization measures and enable the free flow of cross-border data flows
  • End discriminatory and/or burdensome regulatory practices
  • Ensure standards in all forms are market-oriented
  • Create rules for state-owned enterprises to ensure fair and non-discriminatory treatment of all companies

According to Trade Promotion Authority (TPA), the U.S. law that guides trade votes in Congress, negotiations with each country can only begin 90 days after last week’s notification. During that period, there will be intensive consultation with Congress and stakeholders. This means, at the earliest, talks can start on January 14, 2019. (Bear in mind that discussions with the UK can only begin in earnest once the UK has formally left the European Union on March 29, 2019.)

The Trump administration’s announcement comes after the U.S. imposed or threatened tariffs on imports on all trading partners, including the EU and China. All told, the U.S. has imposed tariffs on more than $300 billion worth of goods. SEMI has weighed in on the detrimental nature of tariffs, arguing that tariffs on China will ultimately do nothing to address the concerns with China’s trade practices. This sledgehammer approach will introduce significant uncertainty, impose greater costs, and potentially lead to a trade war, ultimately undercutting the ability of semiconductor companies to sell overseas, stifling innovation and curbing U.S. technological leadership.

Elsewhere, the Comprehensive and Progressive Agreement for Trans-Pacific Partnership, the multilateral trade deal that links 11 Asia-Pacific economies, is well on its way to taking force. Canada will be taking its final steps to ratify the deal, joining Mexico, Japan and Singapore. The deal, formerly known as the Trans-Pacific Partnership, should take effect by the first half of 2019.

SEMI will continue tracking ongoing trade developments. Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

With tremendous growth of smartphones over the past decade, foundry sales to the communications market have soared and are now forecast to account for about 3x more than IC foundry sales to the computer market in 2018, based on IC Insights’ extensive part-two analysis of the integrated circuit foundry business in the September Update to The 2018 McClean Report (Figure 1).

Figure 1

Ten years ago, computers/computing systems were easily the largest application for pure-play IC foundry sales, but a relatively flat tablet PC market and lackluster desktop and notebook PC sales since 2011 contributed to weak pure-play foundry sales into the computer segment.

Now, new server applications targeting artificial intelligence (AI), the Internet of Things, Cloud Computing, and cryptocurrency are forecast to breathe new life into this market segment over the next five years. TSMC expects its IC sales into the IoT segment will grow by a CAGR of more than 20% from 2017 through 2022 (the company had greater than $1.0 billion in IoT sales in 2017).

Although IC foundry sales for computer applications are expected to surge 41% this year (driven by TSMC’s cryptocurrency device sales), the communications foundry market is still expected to be about 3x the size of the computer segment in 2018.  The communications foundry market is forecast to display only a 2% growth rate in 2018, six points less than the total pure-play foundry market growth rate expected for this year.

Overall, the communications (52%), computer (19%), and consumer (13%) market segments are forecast to represent 84% of the pure-play IC foundry market in 2018.

By Emir Demircan

SEMI today confirmed its support for a Joint-Industry Cooperation on an RoHS Review aimed at urging the European Commission to, at a minimum, consider dedicating more resources to a targeted outreach programme with third countries. The Joint-Statement is as follows:

Since its inception in 2002, the RoHS Directive has become a global reference point for regulation of hazardous substances in electrical and electronic equipment (EEE). This has been effective and given the EU a competitive advantage. The worldwide impact of RoHS is significant and the undersigned associations consider that this should be considered in the roadmap for reviewing the Directive.

RoHS-type laws have been introduced or are currently being introduced in more than 40 jurisdictions outside the European Economic Area (EEA). These include China, India, the Eurasian Customs Union and the Gulf States. Sometimes RoHS is copied exactly. However, often it is not. For example, countries might introduce a completely different approach on the scope, exemptions and declaration of conformity. Each time a new “RoHS” law is proposed, industry has to establish a bi-lateral dialogue with the relevant local public authorities improving the knowledge and understanding of regulatory stakeholders based on experience with the framework legislation in the EEA. Industry continues to spend a lot of time and money to ensure alignment with EU RoHS as far as possible. This is crucial for the global and complex EEE supply chains.

The European Commission’s DG TRADE “Market Access” services have been helpful with draft laws that have been notified to the WTO and have raised concerns with the Technical Barriers to Trade (TBT) Committee as well as bi-laterally with the countries in question. A recent example was the draft legislation in the United Arab Emirates.

Each time the EU updates the legislation, for example, withdrawing, renewing or granting an exemption, adding a substance, this will have a domino effect on the rest of the world.

To this end, we urge the Commission to, at a minimum, consider dedicating more resources to a targeted outreach programme with third countries. The EU recently adopted a Regulation on responsible minerals supply chains and DG TRADE subsequently launched such outreach with the United States, China, India, United Arab Emirates, Colombia, Mexico, South Africa, Malaysia, Thailand and Canada.

We, the undersigned associations, endorse the Commission’s roadmap for the evaluation and the aim to review and improve the effectiveness, efficiency, relevance of the RoHS Directive, as well as coherence with other EU laws and policies. However, we feel this important global dimension is absent and should be incorporated into the Review.

The Joint-Statement with the full list of participating associations can be accessed here.

SEMI encourages its members to communicate the Joint-Statement at regional and national levels. For more information, contact Emir Demircan, senior manager Advocacy and Public Policy, SEMI Europe, at [email protected].

Total wafer shipments in 2018 year are expected to eclipse the all-time market high set in 2017 and continue to reach record levels through 2021, according to SEMI’s recent semiconductor industry annual silicon shipment forecast. The forecast of demand for silicon units for the period 2018 through 2021 shows polished and epitaxial silicon shipments totaling 12,445 million square inches in 2018; 13,090 million square inches in 2019; 13,440 million square inches in 2020, and 13,778 million square inches in 2021 (see table below).

“As new greenfield fab projects continue to emerge for memory and foundry, silicon shipments are expected to remain strong for 2019 and through 2021,” said Clark Tseng, director of Industry Research & Statistics at SEMI. “Silicon demand will continue to grow as semiconductor content increases in mobile, high-performance computing, automotive, and Internet of Things applications.”

2018 Silicon* Shipment Forecast (MSI = Millions of Square Inches)
Actual
Forecast
2016
2017
2018
2019
2020
2021
MSI
10,577
11,617
12,445
13,090
13,440
13,778
Annual Growth
3.0%
9.8%
7.1%
5.2%
2.7%
2.5%

*Total Electronic Grade Silicon Slices – Excludes Non-Polished Wafers

*Shipments are for semiconductor applications only and do not include solar applications

Source: SEMI (www.semi.org), October 2018

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or chips are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

A new approach in Fault Detection and Classification (FDC) allows engineers to uncover issues more thoroughly and accurately by taking advantage of full sensor traces.

By Tom Ho and Stewart Chalmers, BISTel, Santa Clara, CA

Traditional FDC systems collect data from production equipment, summarize it, and compare it to control limits that were previously set up by engineers. Software alarms are triggered when any of the summarized data fall outside of the control limits. While this method has been effective and widely deployed, it does create a few challenges for the engineers:

  • The use of summary data means that (1) subtle changes in the process may not be noticed and (2) the unmonitored section of the process will be overlooked by a typical FDC system. These subtle changes or the missed anomalies in unmonitored section may result in critical problems.
  • Modeling control limits for fault detection is a manual process, prone to human error and process drift. With hundreds of thousandssensors in a complex manufacturing process, the task of modeling control limits is extremely time consuming and requires a deep understanding of the particular manufacturing process on the part of the engineer. Non-optimized control limits result in misdetection: false alarms or missed alarms.
  • As equipment ages, processes change. Meticulously set control limit ranges must be adjusted, requiring engineers to constantly monitor equipment and sensor data to avoid false alarms or missed real alarm.

Full sensor trace detection

A new approach, Dynamic Fault Detection (DFD) was developed to address the shortcomings of traditional FDC systems and save both production time and engineer time. DFD takes advantage of the full trace from each and every sensor to detect any issues during a manufacturing process. By analyzing each trace in its entirety, and running them through intelligent software, the system is able to comprehensively identify potential issues and errors as they occur. As the Adaptive Intelligence behind Dynamic Fault Detection learns each unique production environment, it will be able to identify process anomalies in real time without the need for manual adjustment from engineers. Great savings can be realized by early detection, increased engineer productivity, and containment of malfunctions.

DFD’s strength is its ability to analyze full trace data. As shown in FIGURE 1, there are many subtle details on a trace, such as spikes, shifts, and ramp rate changes, which are typically ignored or go undetected by a traditional FDC systems, because they only examine a segment of the trace- summary data. By analyzing the full trace using DFD, these details can easily be identified to provide a more thorough analysis than ever before.

Figure 1

Dynamic referencing

Unlike traditional FDC deployments, DFD does not require control limit modeling. The novel solution adapts machine learning techniques to take advantage of neighboring traces as references, so control limits are dynamically defined in real time.  Not only does this substantially reduce set up and deployment time of a fault detection system, it also eliminates the need for an engineer to continuously maintain the model. Since the analysis is done in real time, the model evolves and adapts to any process shifts as new reference traces are added.

DFD has multiple reference configurations available for engineers to choose from to fine tune detection accuracy. For example, DFD can 1) use traces within a wafer lot as reference, 2) use traces from the last N wafers as reference, 3) use “golden” traces as reference, or 4) a combination of the above.

As more sensors are added to the Internet of Things network of a production plant, DFD can integrate their data into its decision-making process.

Optimized alarming

Thousands of process alarms inundate engineers each day, only a small percentage of which are valid. In today’s FDC systems, one of the main causes for false alarms is improperly configured Statistical Process Control (SPC) limits. Also, typical FDC may generate one alarm for each limit violation resulting in many alarms for each wafer process. DFD implementations require no control limits, greatly reducing the potential for false alarms.  In addition, DFD is designed to only issues one alarm per wafer, further streamlining the alarming system and providing better focus for the engineers.

Dynamic fault detection use cases

The following examples illustrate actual use cases to show the benefits of utilizing DFD for fault detection.

Use case #1– End Point Abnormal Etching

In this example, both the upper and lower control limits in SPC were not set at the optimum levels, preventing the traditional FDC system from detecting several abnormally etched wafers (FIGURE 2).  No SPC alarms were issued to notify the engineer.

Figure 2

On the other hand, DFD full trace comparison easily detects the abnormality by comparing to neighboring traces (FIGURE 3).  This was accomplished without having to set up any control limits.

Figure 3

Use case #2 – Resist Bake Plate Temperature

The SPC chart in Figure 4 clearly shows that the Resist bake plate temperature pattern changed significantly; however, since the temperature range during the process never exceeded the control limits, SPC did not issue any alarms.

Figure 4

When the same parameter was analyzed using DFD, the temperature profile abnormality was easily identified, and the software notified an engineer (FIGURE 5).

Figure 5

Use case #3 – Full Trace Coverage

Engineers select only a segment of sensor trace data to monitor because setting up SPC limits is so arduous. In this specific case, the SPC system was set up to monitor only the He_Flow parameter in recipe step 3 and step 4.  Since no unusual events occurred during those steps in the process, no SPC alarms were triggered.

However, in that same production run, a DFD alarm was issued for one of the wafers. Upon examination of the trace summary chart shown in FIGURE 6, it is clear that while the parameter behaved normally during recipe step 3 and step 4, there was a noticeable issue from one of the wafers during recipe step 1 and step 2.  The trace in red represents the offending trace versus the rest of the (normal) population in blue. DFD full trace analysis caught the abnormality.

Figure 6

Use case #4 – DFD Alarm Accuracy

When setting up SPC limits in a conventional FDC system, the method of calculation taken by an engineer can yield vastly different results. In this example, the engineer used multiple SPC approaches to monitor parameter Match_LoadCap in an etcher. When the control limits were set using Standard Deviation (FIGURE 7), a large number of false alarms were triggered.  On the other hand, zero alarms were triggered using the Meanapproach (FIGURE 8).

Figure 7

Figure 8

Using DFD full trace detection eliminates the discrepancy between calculation methods. In the above example, DFD was able to identify an issue with one of the wafers in recipe step 3 and trigger only one alarm.

Dynamic fault detection scope of use

DFD is designed to be used in production environments of many types, ranging from semiconductor manufacturing to automotive plants and everything in between. As long as the manufacturing equipment being monitored generates systematic and consistent trace patterns, such as gas flow, temperature, pressure, power etc., proper referencing can be established by the Adaptive Intelligence (AI) to identify abnormalities. Sensor traces from Process of Record (POR) runs may be used as starting references.

Conclusion

The DFD solution reduces risk in manufacturing by protecting against events that impact yield.  It also provides engineers with an innovative new tool that addresses several limitations of today’s traditional FDC systems.  As shown in TABLE 1, the solution greatly reduces the time required for deployment and maintenance, while providing a more thorough and accurate detection of issues.

 

TABLE 1
FDC

(Per Recipe/Tool Type)

 DFD

(Per Recipe/Tool Type)
FDC model creation 1 – 2 weeks < 1 day
FDC model validation and fine tuning 2 – 3 weeks < 1 week
Model Maintenance Ongoing Minimal
Typical Alarm Rate 100-500/chamber-day < 50/chamber-day
% Coverage of Number of Sensors 50-60% 100% as default
Trace Segment Coverage 20-40% 100%
Adaptive to Systematic Behavior Changes No Yes

 

 

TOM HO is President of BISTel America where he leads global product engineer and development efforts for BISTel.  [email protected].   STEWART CHALMERS is President & CEO of Hill + Kincaid, a technical marketing firm. [email protected]. 

The average revenue generated from processed wafers among the four biggest pure-play foundries (TSMC, GlobalFoundries, UMC, and SMIC) is expected to be $1,138 in 2018, when expressed in 200mm-equivalent wafers, which is essentially flat from $1,136 in 2017, according to a new analysis by IC Insights (Figure 1).  The average revenue per wafer among the Big 4 foundries peaked in 2014 at $1,149 and then slowly declined through last year, based on IC Insights’ extensive part-two analysis of the integrated circuit foundry business in the September Update to The 2018 McClean Report.

Figure 1

TSMC’s average revenue per wafer in 2018 is forecast to be $1,382, which is 36% higher than GlobalFoundries’ $1,014.  UMC’s average revenue per wafer in 2018 is expected to be only $715, about half of the projected amount at TSMC this year.  Furthermore, TSMC is the only foundry among the Big 4 that is expected to generate higher revenue per wafer (9% more) in 2018 than in 2013.  In contrast, GlobalFoundries, UMC, and SMIC’s 2018 revenue per wafer averages are forecast to decline by 1%, 10%, and 16%, respectively, compared to 2013.

Although the average revenue per wafer of the Big 4 foundries is forecast to be $1,138 this year, the amount generated is highly dependent upon the minimum feature size of the IC processing technology. Figure 2 shows the typical 2Q18 revenue per wafer for some of the major technology nodes and wafer sizes produced by pure-play foundries.  In 2Q18, there was more than a 16x difference between the 0.5µ 200mm revenue per wafer ($370) and the ≤20nm 300mm revenue per wafer ($6,050).  Even when using revenue per square inch, the difference is dramatic ($7.41 for the 0.5µ technology versus $53.86 for the ≤20nm technology).  Since TSMC gets such a large percentage of its sales from ≤45nm production, its revenue per wafer is expected to increase by a compound annual growth rate (CAGR) of 2% from 2013 through 2018 as compared to a -2% CAGR for the total revenue per wafer average of GlobalFoundries, UMC, and SMIC during this same timeperiod.

Figure 2

There will probably be only three foundries able to offer high-volume leading-edge production over the next five years (i.e., TSMC, Samsung, and Intel).  IC Insights believes these companies are likely to be fierce competitors among themselves—especially TSMC and Samsung—and as a result, pricing will likely be under pressure through 2022.

Data provided by the Semiconductor Industry Association (SIA) indicates that worldwide sales of semiconductors reached USD 40.16 Billion for the month of August 2018, representing an increase of 14.9% when compared to the August 2017 total of USD 34.96 Billion. Global sales in August 2018were 1.7% higher than the July 2018 total of USD 39.49 Billion. The semiconductor industry is one of the fastest growing industries of the technology sector. According to Stratistics MRC, many semiconductor companies are beginning to embrace IoT to drive new revenue and growth models. Squire Mining Ltd. (OTC: SQRMF), Taiwan Semiconductor Manufacturing Company Limited (NYSE: TSM), Applied Materials, Inc. (NASDAQ: AMAT), Qorvo, Inc. (NASDAQ: QRVO), Entegris, Inc. (NASDAQ: ENTG)

According to a recent report by Accenture, the semiconductor industry is the most bullish sector when it comes to the integration of blockchain within their industry and the impact of artificial intelligence. “Throughout the industry’s complex supply chain, blockchain simplifies business operations leveraging semiconductor chips and related technologies,” said Syed Alam, a Managing Director in Accenture Strategy who leads Accenture’s Semiconductor practice. “This faster traceability will improve companies’ business operations and accelerate delivery of their products to market – while enabling them to do so at lower costs. Semiconductor companies can also use blockchain to create, scale and manage technology-based collaborations and redefine future business transactions.”

Squire Mining Ltd. (OTCQB: SQRMF) is also listed on the Canadian Securities Exchange under the ticker (CSE: SQR). Just earlier today, the company announced breaking news that, “Ennoconn Corporation (“Ennoconn”) as our hardware manufacturer for next generation mining systems to mine Bitcoin Cash, Bitcoin and other associated cryptocurrencies. Ennoconn is a leading industrial motherboard designer and total hardware system solution provider headquartered in Taipei, Taiwan and listed on the Taiwan stock exchange (TPE:6414). In 2007, Foxconn Technology Group, the largest “Electronic Manufacturing Service” company in the world, became the majority shareholder of Ennoconn, forming a strong strategic alliance in embedded system and electronic manufacturing.

On August 21, 2018, Squire announced that AraSystems Technology Corp. (“AraSystems”), a subsidiary of Squire, had entered into a provisional non-binding agreement with a major global technology assembly company. This company, now revealed to be Ennoconn, will assist in the design and assembly of our next generation mining rig at such time as a working prototype of our debut ASIC chip is completed.

On October 3, 2018 Squire announced the successful completion and testing of its FPGA working prototype microchip, with early results of the terahash-to-energy consumption ratio, indicating that the final ASIC chip and mining system has the potential to reduce operational costs by up to 40% for enterprise mining facilities.

● This cost reduction was estimated by one leading enterprise mining group to be worth up to $60M per year in savings to their operations alone.

● The final ASIC chip and mining system together are expected to provide up to a four times improvement in the performance of mining the blockchain, a process that enables miners to be paid, thereby increasing the return on investment, and profit, for miners. Such calculations are based on comparisons with the majority of current generation mining machines operating inside enterprise facilities around the world.

Following this success, the Company has signed a binding Memorandum of Understanding with Ennoconn and funded work to commence Phase 1 design and development of AraSystem’s next generation mining system in collaboration with its partners in Taipei, Taiwan and in Seoul, South Korea. Definitive documentation will be entered into following delivery of final specifications and data sheets to Ennoconn later this month.

Squire’s engineers are currently working with Ennoconn to design and develop AraSystem’s mining rig which will house the debut ASIC chip currently under development by the Company’s subsidiary AraCore Technology Corp (“AraCore”), in conjunction with GaonChips and Samsung Electronics (see news releases dated September 25 and October 3, 2018). In turn, Ennoconn will be responsible for mass assembly of the mining rig once all design, development and testing work has been completed.

A prototype of the mining rig along with full specifications of the AraCore ASIC chip are expected to be presented at the CoinGeek Conference in London on November 28 – 30, 2018, with presales expected to commence on or around that date. Significant interest has already been expressed by several of the industry’s largest enterprise mining companies, which currently host hundreds of thousands of mining machines in their facilities across the world.”

‘We are very pleased to be partnering with the skilled engineers at Ennoconn, one of the world’s leading electronic manufacturing companies,’ stated Simon Moore, Executive Chairman and CEO of Squire. ‘As we launch our next generation mining rig with a suite of proprietary innovations, it’s imperative that our manufacturing partners have the talent, experience and capacity to not only deliver unique hardware, but also deliver best in class quality. We believe Ennoconn will help ensure the production of an exceptional mining rig for the marketplace,’ he said. Further, Mr. Moore noted, ‘based on initial interest from the sector, the potential for significant sales and the subsequent revenue for Squire is on track in the coming year which would make Squire and its partners a noteworthy industry provider of crypto mining hardware and next generation innovation on a global scale.’

Taiwan Semiconductor Manufacturing Company Limited (NYSE: TSM) is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry segment’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. TSMC recently announced the initial availability of its Open Innovation Platform® Virtual Design Environment (OIP VDE), which enables semiconductor customers to securely design in the cloud, leveraging TSMC OIP design infrastructures within the flexibility of cloud infrastructures. OIP VDE is the result of TSMC collaboration with TSMC OIP design ecosystem partners and leading cloud providers to deliver a complete systems-on-chip (SoCs) design environment in the cloud. TSMC OIP VDE’s first implementations of digital RTL-to-GDSII and custom schematic capture-to-GDSII flows are via partnerships with TSMC’s inaugural Cloud Alliance partners, Amazon Web Services (AWS), Cadence, Microsoft Azure, and Synopsys. In TSMC’s enablement of OIP VDE, both digital and custom design flows have been validated in the cloud, along with OIP design collateral-including process technology files, PDKs, foundation IP, and reference flows. To ensure low barriers to entry and high technical support levels, Cadence and Synopsys act as the focal point helping customers to set up VDE and providing first line support.

Applied Materials, Inc. (NASDAQ: AMAT) is a developer of materials engineering solutions used to produce virtually every new chip and advanced display in the world. Applied Materials recently celebrated the 20th anniversary and 5,000th shipment of the Producer® platform, a manufacturing system that helps make virtually every chip in the world. The Producer platform was launched in July of 1998 to help enable chips to run faster by changing their wiring from aluminum to copper, which is a better conductor. The transition was needed by the industry to drive the performance and power improvements associated with Moore’s Law, but it also required many additional steps that could have made the progress unaffordable. To help, Applied Materials designed every element of the Producer platform to give customers the highest performance at the lowest possible operating cost. “With the landmark Producer platform, Applied achieved something that had never been done before on this scale: create a highly flexible architecture that can support multiple technology generations and still remain incredibly productive,” said G. Dan Hutcheson, Chief Executive Officer of VLSIresearch. “Today, the Producer platform continues to allow chipmakers to imagine and build chips in entirely new ways. Congratulations to Applied Materials on this impressive milestone for one of the most important process systems in the semiconductor industry.”

Qorvo, Inc. (NASDAQ: QRVO) recently introduced a new System in Package (SiP) that enables dynamic, simultaneous support for Zigbee® 3.0, Green Power, Thread and Bluetooth Low Energy (BLE). This new SiP integrates Qorvo power amplifier technology providing 20 dBm output, which is especially important for U.S. smart home applications. The Qorvo QPG6095M is a fully integrated SiP for ultra-low power wireless communications. It is BLE 5.0 and Zigbee 3.0 platform and product certified, and offers Green Power energy efficiency. This SiP also extends range and battery life and enables robust interference mitigation. The QPG6095M delivers optimized connectivity throughout the home, eliminating the need for complex mesh architectures and unnecessary battery consumption in intermediate devices. The QPG6095M blends Qorvo’s power amplifier (PA) technology with a multi-standard, multi-protocol chip. Its level of integration and performance benefit product designers by lowering development costs and speeding time to market. Cees Links, General Manager of Qorvo’s Wireless Connectivity business unit, said, “This new SiP is another example of Qorvo’s commitment to combining and leveraging RF technologies to improve the consumer’s connected experience. Developers can now deliver BLE, Zigbee and Thread simultaneously with more range and reliability, and reduce concerns about future compatibility.”

Entegris, Inc. (NASDAQ: ENTG) is a developer and provider of specialty chemicals and advanced materials solutions for the microelectronics industry and other high-tech industries. Entegris, Inc. recently released the next generation EUV 1010 Reticle Pod for high-volume IC manufacturing using extreme ultraviolet (EUV) lithography. Developed in close collaboration with ASML, one of the world’s largest manufacturers of chip-making equipment, Entegris’s EUV 1010 is the first to be qualified by ASML for use in the NXE:3400B and beyond. As the semiconductor industry begins ramping EUV lithography for the high-volume manufacturing (HVM) of advanced technology nodes, keeping EUV reticles defect-free is more demanding than ever. Entegris’s EUV 1010 Reticle Pod is now fully qualified by ASML for their latest generation scanner having demonstrated outstanding protection of the EUV reticles, including against the most critical particle challenges. As a result, Entegris’s EUV 1010 enables customers to safely transition to smaller and smaller line widths, as needed for the most advanced lithography processes.

Toshiba Memory Corporation (TMC) today announced the appointment of Stacy J. Smith as Executive Chairman, effective on October 1, 2018.

Smith brings a long and proven track record of executive leadership to TMC. He has extensive international experience, having both lived and led organizations in the Asia-Pacific, Latin America, Europe, the Middle East and Africa. He will work closely with CEO Yasuo Naruke to provide overall leadership to the business.

Smith previously spent three decades at Intel leading organizations across multiple disciplines. In his role as President, Manufacturing, Operations and Sales, from 2016 to 2018, he led 40,000 employees involved in worldwide manufacturing, technology development, supply chain, pricing and sales. He also served as Intel’s Chief Financial Officer for almost a decade and in this role also had responsibility for corporate strategy, M&A, and Intel Capital. Prior to that he served as Intel’s Chief Information Officer and Vice President for Sales for Europe, the Middle East and Africa.

Smith also brings strong board leadership experience. He currently serves as board chairman at Autodesk and as a director for Metromile. He served previously as a director for Virgin America and for GEVO. He also serves on the Board of Trustees for The Nature Conservancy of California and on the University of Texas McCombs School of Business Advisory Board. Smith attended The University of Texas at Austin, where he received his MBA in 1988 and his BBA in 1985.

“We are thrilled that Stacy is joining Toshiba Memory Corporation in this crucial leadership role at an important time in the company’s history,” said Yasuo Naruke, President and CEO of TMC. “With Stacy’s wealth of international leadership experience and knowledge of the semiconductor space, there is no doubt he is the perfect person to help lead our company in the next phase of growth as an independent company.”

“I am excited to take on this important challenge, and honored to join the TMC team,” said Smith. “Toshiba invented flash memory, and with TMC now operating as an independent company with increased capacity to invest in developing and growing semiconductor technology, the company has a strong growth trajectory ahead of it.”

Smith’s hiring follows the acquisition this year of TMC by an industry consortium led by Bain Capital Private Equity. Bain Capital Private Equity has a long history of successful investments in Japan including Skylark, Jupiter Shop Channel, BellSystem24, Domino’s Pizza Japan, Ooedo Onsen, and Asatsu-DK. The firm’s deep market knowledge, extensive local networks and expertise in driving operational improvement strategies have made Bain Capital a valued partner for Japanese companies.

“Stacy is the right leader to help TMC, already a technology leader in the flash memory industry, achieve its potential as an independent company,” said David Gross-Loh, a director of TMC and a managing director and co-head of Asia for Bain Capital Private Equity. “We are very pleased to welcome Stacy to TMC and look forward to working closely with him and the expanded management team.”