Category Archives: Metrology

December 17, 2012 – Samsung Austin Semiconductor sent out a PR last week about previously announced $4B investments in its Austin, TX facilities. The site is on schedule for production in 2H13 for mobile application processors (28nm process technologies on 300mm wafers). Samsung Austin Research Center also is adding about 200 engineers to fuel this effort, according to the company. The commitment — representing the largest single foreign investment ever made in the state of Texas — will bring Samsung’s total investment in its Austin Semiconductor unit to more than $15B since 1996.

The original Samsung Austin investment announcement — much less this update, thin on new details — wasn’t exactly a surprise; a 3Q12 retrofit had been seen as one of the key capex drivers for the latter half of this year. Samsung is expected to push its capex by 11% in 2012 to $13.1B, just ahead of Intel’s $12.5B (16% Y/Y growth) — together representing fully 40% of worldwide capital spending this year.

In a quick research note, Barclays’ CJ Muse notes that Samsung’s overall capex could be as much as halved this year (a -30% to -50% range), with most of it coming from the logic side due to an Apple defection. He currently models Samsung LSI’s capex in 2013 declining about 25% to KRW 6 trillion (~$5.4B), and possibly even more, and that it will focus on a 32nm-to-28nm transition, i.e. "spending will be shrink-oriented vs. capacity-oriented." Near-term, Muse sees Samsung’s orders, currently at "negligible levels," as possibly picking up in 1H13 to support this Austin push. He thinks this will contribute to an overall sector-wide orders environment of "flattish to slightly up (in-line with expectations)."

Another thing this announcement accomplishes, Muse notes, is a signal to the marketplace that Samsung is still investing to remain competitive with TSMC. Apple has openly partnered with Samsung in Austin to make the "engine" of the iPhone and iPad, despite the two companies’ fierce and broad competition in finished electronics devices. That business is in doubt, though, as many speculate about the electronics giant will seek other noncompetitive partners for future chip orders. With this $4B pledge, even if Samsung loses Apple’s business, it is sending a message to other fabless firms who may decide to grab some of that vacated capacity in 2013-2104.

In an IC fab, cycle time is the time interval between when a lot is started and when it is completed. The benefits of shorter cycle time during volume production are well known: reduced capital costs associated with having less work in progress (WIP); reduced number of finished goods required as safety stock; reduced number of wafers affected by engineering change notices (ECNs); reduced inventory costs in case of a drop in demand; more flexibility to accept orders, including short turnaround orders; and shorter response time to customer demands. Additionally, during development and ramp, shorter cycle times accelerate end-of-line learning and can result in faster time to market for the first lots out the door.

Given all the benefits of reducing cycle time, it’s useful to consider how wafer defect inspection contributes to the situation. To begin with, the majority of lots do not accrue any cycle time associated with the inspection, since usually less than 25 percent of lots go through any given inspection point. For those that are inspected, cycle time is accrued by sending a lot over to the inspection tool, waiting until it’s available, inspecting the lot and then dispositioning the wafers. On the other hand, defect inspection can decrease variability in the lot arrival rate—thereby reducing cycle time.

Three of the most important factors used in calculating fab cycle time are variability, availability, and utilization. Of these, variability is by far the most important. If lots arrive at process tools at a constant rate, exactly equal to the processing time, then no lot will ever have to wait and the queue time will be identically zero. Other sources of variability affect cycle time, such as maintenance schedules and variability in processing time, but variability in the lot arrival rate tends to have the biggest impact on cycle time.

In the real world lots don’t arrive at a constant rate and one of the biggest sources of variability in the lot arrival rate is the dreaded WIP bubble—a huge bulge in inventory that moves slowly through the line like an over-fed snake. In the middle of a WIP bubble every lot just sits there, accruing cycle time, waiting for the next process tool to become available. Then it moves to the next process step where the same thing happens again until eventually the bubble dissipates. Sometimes WIP bubbles are a result of the natural ebb and flow of material as it moves through the line, but often they are the result of a temporary restriction in capacity at a particular process step (e.g., a long “tool down”).

When a defect excursion is discovered at a given inspection step, a fab may put down every process tool that the offending lot encountered, from the last inspection point where the defect count was known to be in control, to the current inspection step.  Each down process tool is then re-qualified until, through a process of elimination, the offending process tool is identified.

If the inspection points are close together, then there will be relatively few process tools put down and the WIP bubble will be small.  However, if the inspection points are far apart, not only will more tools be down, but each tool will be down for a longer period of time because it will take longer to find the problem.  The resulting WIP bubble can persist for weeks, as it often acts like a wave that reverberates back and forth through the line creating abnormally high cycle times for an extended period of time. 

Consider the two situations depicted in Figure 1 (below). The chart on the top represents a fab where the cycle time is relatively constant. In this case, increasing the number of wafer inspection steps in the process flow probably won’t help.  However, in the second situation (bottom), the cycle time is highly variable. Often this type of pattern is indicative of WIP bubbles.  Having more wafer inspection steps in the process flow both reduces the number of lots at risk, and may also help reduce the cycle time by smoothing out the lot arrival rate.

 

Because of its rich benefits, reducing cycle time is nearly always a value-added activity. However, reducing cycle time by eliminating inspection steps may be a short-sighted approach for three important reasons. First, only a small percentage of lots actually go through inspection points, so the cycle time improvement may be minimal. Second, the potential yield loss that results from having fewer inspection points typically has a much greater financial impact than that realized by shorter cycle time. Third, reducing the number of inspection points often increases the number and size of WIP bubbles. 

For further discussions on this topic, please explore the references listed at the end of the article, or contact the first author.

Doug Sutherland, Ph.D., is a principal scientist and Rebecca Howland, Ph.D., is a senior director in the corporate group at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

References

1.       David W. Price and Doug Sutherland, “The Impact of Wafer Inspection on Fab Cycle Time,” Future Technology and Challenges Forum, SEMICON West, 2007.

2.       Peter Gaboury, “Equipment Process Time Variability: Cycle Time Impacts,” Future Fab International. Volume 11 (6/29/2001).  

3.       Fab-Time, Inc.  “Cycle Time Management for Wafer Fabs:  Technical Library and Tutorial.”

4.       W.J. Hopp and M.L. Spearman, “Factory Physics,” McGraw-Hill, 2001, p 325.

December 11, 2012 – Our slideshow of 14 interesting papers at this week’s IEEE International Electron Devices Meeting (IEDM 2012), did not include what are often some of the more intriguing papers — the ones that come in late and are unavailable for preview. This year there are four such papers, and we’re now able to give you a sneak peek at them, being unveiled starting this afternoon and through the week at IEDM in San Francisco.

ZnNO for next-gen displays

Stability degradation, especially at high mobility regime, limits the application of oxide semiconductors in next-generation displays. Zinc oxynitride, with its high mobility characteristics and small bandgap, is getting attention as an alternative for pixel-switching devices in ultra-high definition and large-area displays. Researchers from Samsung Advanced Institute of Technology and Seoul National University will describe ZnON-thin film transistors (TFTs) with field effect mobility near 100 cm2/Vs and operation stability(< 3 V) under light-illumination bias-stress. The uniformity is observed to be suitable for display applications, and with mobility performance comparable to that of polysilicon (poly-Si). (#5.6, "High mobility zinc oxynitride-TFT with operation stability under light-illuminated bias-stress conditions for large area and high resolution display applications")

Structure of ES-type ZnON-TFT fabricated by photolithography. (left) Top view from optical microscope and (b) cross-sectional TEM image at the vicinity of contact region.

SnO transistor for BEOL-CMOS I/Os

Renesas Electronics’ LSI Research Laboratory has devised a new P-type amorphous SnO thin-film transistor with high Ion/Ioff ratio (>104) as a component to complement N-type IGZO transistors for on-chip voltage-bridging BEOL-CMOS I/Os on conventional Si-LSI Cu-interconnects. (The transistor gives standard LSIs a special add-on function to control high-voltage signals directly.) Their BEOL-transistor (BEOL-Tr) uses a wide-band-gap InGaZnO (IGZO) as the channel and cap-SiN/Cu-interconnect as the gate dielectric/bottom-gate electrode. Normally-off transistor characteristics with relatively high mobility, high-Vd tolerance, high Ion/Ioff ratio, have made the BEOL-Tr attractive for voltage-bridging devices mountable onto advanced MCUs and SoCs. Realization of P-type transistors to complement IGZO-based NFETs and form BEOL-CMOS is also a key function for more sophisticated applications, they claim. (#18.8, "High On/Off-ratio P-type Oxide-based Transistors Integrated onto Cu-interconnects for On-chip High/Low Voltage-bridging BEOL-CMOS I/Os")

XTEM of the integrated device structure with G/D offset of 0.5μm. SnO is integrated onto Cu interconnect to realize P-type BEOL-Tr with high Ion/Ioff ratio. Device integration requires only one mask addition.

III-V TFETs for the 7nm node

III-V tunneling field-effect transistors (TFET) for low-voltage logic applications have gained attention, but their nonoptimized carrier tunneling limit drive currents. Researchers from the Rochester Institute of Technology and SEMATECH set out to map III-V Esaki tunnel diode performance, engineering tunnel diodes (TD) with ultrahigh-current densities while maintaining large peak-valley current ratios. In this paper, they report a comprehensive experimental benchmarking of an Esaki diode, including GaAs, In0.53Ga0.47As, InAs, InAs0.9Sb0.1/Al0.4Ga0.6Sb, and InAs/GaSb. Engineering the hetero-junctions enhances peak and Zener current densities beyond homo-junctions, to a record 2.2 MA/cm2 and 1.1 MA/cm2 (-0.3 V), laying the groundwork for III-V TFETs at the 7nm technology node. (#27.7, "Benchmarking and Improving III-V Esaki Diode Performance With a Record 2.2 MA cm2 Current Density to Enhance TFET Drive Current")

(a) Cross-section of a TD fabrication process flow. (b) SEM image of a characteristic submicron TD after mesa etch. (c) schematic of a fully-fabricated TD.

Integrated CMOS silicon photonics on 90nm

IBM researchers in the US and Europe are demonstrating the first sub-100nm technology (a current 90nm base SOI logic technology) that allows monolithic integration of optical modulators and germanium photodetectors — putting optical and electrical circuits side-by-side on the same chip. The resulting 90nm CMOS-integrated nano-photonics technology is optimized for analog functionality to yield power-efficient, single-die multichannel wavelength-mulitplexed 25Gbps transceivers. (IBM has a fuller description of the technology in a separate press release.) (#33.8, "A 90nm CMOS Integrated Nano-Photonics Technology for 25Gbps WDM Optical Communications Applications")

Cross-sectional SEM view of a 90nm CINP metal stack with Ge PD embedded into the front-end. Zoomed-in image of a photodetector is shown on top left. Optical microscope top-down image is shown on the low left.

Angled view of a portion of an IBM chip showing blue optical waveguides transmitting high-speed optical signals and yellow copper wires carrying high-speed electrical signals.

December 6, 2012 – Semiconductor equipment demand is persistently sluggish as the industry takes a break from a "multiyear expansion period" to digest recent investments and wrestle with a broader economic slowdown. But make no mistake: leading-edge technology investments are still happening, and growth will return in the typical cyclical pattern, predicts SEMI in its updated year-end forecast, issued this week at SEMICON Japan.

Sales of semiconductor manufacturing equipment overall is now seen declining -12.2% in 2012 to $38.22B, after a 9% increase in 2011 to $43.53B and a 151% spike in 2010 to $39.92B, according to SEMI’s updated numbers. SEMI’s midyear forecast released at SEMICON West called for a -2.6% in overall equipment sales to $42.38B, followed by a 10.2% growth rebound in 2013. A significant downgrade had been expected, as after a strong early part of the year monthly data trends in semiconductor equipment demand have continued to turn sour.

"Sales of semiconductor manufacturing equipment in 2012 reflect significant investments over the prior two years, normal patterns of industry cyclicality and a slowdown in the broader economy," stated SEMI president/CEO Denny McGuirk. "What’s more important is that technology investments at the advanced nodes and in leading-edge packaging remain important drivers, and when market confidence returns, we expect capacity investments to increase."

Forecast by region. (Source: SEMI)

By region, only two areas will see any growth in 2012: Taiwan (12.7% to $9.60B) and South Korea (10.7% to $9.59B). Both will leapfrog the North American market, which is seen sliding -14% to $7.95B. Biggest declines will be in the smaller regions: Rest-of-World (-38% to $2.12B), Europe (-36% to $2.68B), and Japan (-36% to $3.72B). Among the drivers in Korea’s market are obviously numerous investments by Samsung (Lines 16, S1-A, and S1-C, and technology upgrades to other lines) and Hynix (upgrades to M10 and M11+M4, and the ramp of M12), noted Lara Chamness from SEMI Industry Research and Statistics. In Taiwan, TSMC is pouring resources into Fab 12, Fab 14, and Fab 15. "Other smaller device manufacturers are making non-trivial investments in the region," she added.

By equipment type, 2012 is being weighted down by the wafer processing segment, by far the largest segment, at nearly a -15% dropoff from 2011. The backend categories will decline but only about -5%, while the "other" category (facilities, mask reticles, other tools) will actually grow about 6%.

The picture brightens somewhat in 2013 with a deceleration of decline, -2.1% to $37.42B. By region there will be slight to moderate growth in China, Taiwan, and Japan, but offset by a -10% dropoff in Korean investments, SEMI predicts. By technology, the tables will turn: wafer processing will actually sneak into the black (0.3%), but backend categories will weigh down the overall picture.

Return to true growth will finally arrive in 2014, with 12.4% growth to $42.08B. All regions, and for all equipment types, will enjoy increased sales generally in the low-teens, predicts SEMI.

Forecast by equipment type. (Source: SEMI)

November 21, 2012 – A reference book from the Global Semiconductor Alliance (GSA) and IC Insights puts foundry information at the fingertips of those who need it the most.

GSA and IC Insights have joined forces again to produce the fifth edition of the IC Foundry Almanac, a concise annual reference book for foundry segment analysis, five-year forecasts, wafer and mask set pricing information, and foundry company profile data.

The partnership combines IC Insights’ analysis of market growth and capacity trends with GSA’s analysis of wafer and mask set pricing data and extensive database of IC foundry service provider profiles.

Report highlights include:

  • Foundry segment analysis, including IC foundry industry analysis, sales analysis, and capacity;

  • Wafer fabrication and mask set pricing & capacity trends, including median wafer fabrication and mask set pricing, additional purchase details, foundry details, and capacity trends; and

  • IC foundry service provider company profiles, with company contact information and stock exchange/ticker.

 

November 16, 2012 – The latest monthly numbers are in for semiconductor manufacturing equipment demand, and they’re not pretty: lows in both orders and sales not seen since the last major downcycle three years ago, and the short-term comparisons continue to widen.

North America-based manufacturers of semiconductor manufacturing equipment reported bookings (orders) of just $743.2M in October, down -18% from September and roughly -20% from a year ago. Billings (sales) came in at $986.5M, off by -15% M/M and nearly -22% Y/Y. (Both are three-month moving averages.) SEMI also revised downward its September data: Bookings lowered to $912.8M (they had been $952.9M), and billings down to $1164.4M (vs. $1177.4M). The book-to-bill (B:B) came in at an anemic 0.75, meaning that $75 worth of orders came in for every $100 shipped out. (A B:B above 1.0 would indicate a good sign of more business coming in; a number below 1.0 means the opposite, and a number substantially below 1.0 and sinking for a while, well…)

Here are some chilling metrics to illustrate just how sour the market for chip tools has become as we head to the finish line of 2012. (All data is compiled from SEMI’s historical tallies dating from Jan. 1991)

  • Bookings are at their lowest point since October 2009. Billings haven’t been this low since January 2010. Since peaking in May, equipment bookings have been slashed by half (-54%) and sales are off by more than a third (-36%).

  • For the ten months through October, equipment orders were tracking down -8.5% from the same period in 2011 to $12.6B, and sales were down -15.7% at $13.3B.

  • Bookings have declined by double-digits for five consecutive months (-11% to -18%), which hasn’t happened since the grand old days of December 2000-April 2001. Except for a single month of mathematically zero growth (April), bookings have declined Y/Y for 16 out of the past 17 months. (This might say more about the industry’s reliably brutal cyclicality than current malaise; May 2011 was the end of a 19-month period in the black, which was preceded by a 29-month trip through the doldrums.)

  • The B:B ratio has been in freefall since April when it was well above the parity level (1.12) — that’s six straight months of decline, which according to SEMI’s data hasn’t happened since late 2010. (We’ve had several five-month slides in the past two years.)

Denny McGuirk, president and CEO of SEMI, labeled the environment for semiconductor industry investments as "muted" entering the final quarter of 2012, though he stated that "investments in leading-edge technologies will continue to drive spending in the near-term." The outlook for 2013 will clear up shortly as chipmakers crystallize their 2013 capex plans, he added. (Note that with about six weeks remaining, any lack of clarity into 2013 planning doesn’t exactly inspire confidence.)

SEMI will present its updated consensus forecast in conjunction with SEMICON Japan on Tuesday Dec 4 (technically it’ll be 11am local time, which is the wee hours late Monday/early Tuesday morning here in the US). One can reasonably expect some drastically different numbers from its current official forecast, issued at SEMICON West in July, which predicted an overall -2.6% decline for the year in global frontend + backend equipment. Hopefully there will be some improved clarity in these coming weeks.

In prep for Semicon Japan in December, Advantest announces three new tools: 2 SEMs and a litho system. These are the wafer MVM-SEM tool E3310, mask defect review SEM E5610, and the F7000 EB lithography system for the 1x nm node.

MVM-SEM tool E3310

The multi-vision metrology scanning electron microscope, MVM-SEM E3310, measures fine-pitch patterns on a wide range of wafer types and uses Advantest’s proprietary electron beam-scanning technology.

The E3310’s multi-detector configuration allows it to achieve stable, highly accurate measurements at the 1x nm node. Its proprietary detection algorithm enables measurement of 3D FinFET architectures that are in the process of full-scale adoption by the semiconductor industry.

The E3310 performs fully automatic measurements even at high SEM magnification, thanks to its high-accuracy stage, charge control function, and contamination reduction technology. Silicon wafers, along with AlTiC, quartz, and silicon carbide wafers, among others, are supported in sizes from 150mm to 300mm, depending on type.

Mask defect review SEM E5610

The mask DR-SEM E5610 reviews and classifies ultra-small defects in photomask blanks. The E5610 inherits the highly stable, fully automatic image capture technology developed by Advantest for its multi-vision metrology SEM for photomasks and features a newly developed beam-tilt mechanism that enables scanning at oblique angles.

Its proprietary column architecture delivers spatial resolution down to 2nm, even at the low acceleration voltages appropriate for photomask screening. The E5610 also features an electrically controlled tilt module that allows its beam to tilt by up to 15 degrees for performing 3D defect reviews. The E5610 is compatible with mainstream mask inspection systems: the tool imports defect location data and automatically images the locations.

EB lithography system for 1x nm node F7000

This new F7000 electron beam lithography system supports substrates of diverse materials, sizes, and shapes, including nanoimprint templates, as well as wafers, and is optimized for diverse applications such as advanced LSIs, photonics, MEMS, and other nanoprocesses.

The F7000 offers the company’s EB technology in a system capable of writing patterns as fine as 1x nm. The system also supports template fabrication for nanoimprint lithography. Advantest has developed a new column technology—key to electron beam writing accuracy—for meeting the needs of semiconductor R&D at the 1x nm node. 

The F7000’s adjuster function enables it to write to diverse sizes of wafer, glass substrates, and square substrates. Moreover, simply by switching adjusters, the system can support silicon, gallium arsenide, and substrates of other materials, utilizing separate adjusters for each material to avoid contamination.

The systems will be featured in Advantest’s exhibit (booth #3D-803 in Hall 3) at the Semicon Japan trade show, December 5-7, in Makuhari Messe in the Chiba prefecture.

November 14, 2012 – Swiss firm Adlyte, a developer of high-brightness laser-produced plasma (LPP) EUV light source for actinic mask inspection, is outlining its current expansion efforts, which includes appointing a longtime industry exec to its strategic advisory board.

At SPIE in early 2011, Adlyte described results with low conversion efficiency (~1%), but respectable source brightness in a compact footprint requiring lower power. More recently, at the EUV Symposium this fall, Adlyte updated its progress: a completed characterization of the engineering tool, a prototype now in development and bill-of-materials procurement completed, installation and integration planned for year’s end, testing/demo in 1H13, followed by volume production. It claims 20W of power into 2π with >250W/mm2 steradian brightness, which exceeds requirements for actinic mask and aerial image metrology (AIMS) system.

Building on that work, the firm has built a new facility that nearly triples the amount of available development space, and is building an additional light source to address requirements for actinic mask inspection, AIMS, and other types of inspection for sub-1x-nm devices. Adlyte also has appointed longtime semiconductor manufacturing exec Joseph R. Bronson (20+ years at Applied Materials, plus stints at FormFactor, Sanmina-SCI, and SVTC Technology) to its strategic advisory board.

“Adlyte is continuing its commitment to the semiconductor industry by assembling the team, products and executive management, which are required to implement EUV and enable the continuation of Moore’s Law for the semiconductor industry,” stated Adlyte co-founder Reza S. Abhari.

When you’re designing a geometrically complex structure like a high-k metal gate, FinFET, or vertical DRAM, you will probably use SEM/TEM cross-sectional imaging to work out the bugs. Maybe even a touch of AFM. However, in production, optical scatterometry-based technology is used, chosen for its speed, non-destructive nature and ability to monitor the 3D shape of a feature. This group of metrology techniques is commonly called OCD (Optical Critical Dimension) or SCD (Scatterometry Critical Dimension).

SCD tools commonly employ either reflectometry, ellipsometry, or a combination of the two methods.  In both approaches, the tool focuses a beam of light onto the structure and collects the light that bounces back. By varying the wavelength, a spectrum is constructed that can be sensitive to the shape of the structure, to the optical properties of the materials that comprise the structure, and to previous-layer features buried within materials transparent at the measurement wavelength.

For a given structure and SCD measurement setup, a set of modeled spectra are generated (either on the fly, or offline and stored as a library of curves) that characterize how the spectrum would change if a parameter of interest were varied—for example, the depth of a trench in a vertical DRAM. The measured spectrum is then compared to the modeled spectra to determine which of the models fits best. The result should correspond to a precise, repeatable value for the parameter of interest.

Of course, seldom is anything that simple in real life. Sometimes more than one parametric change (e.g. trench depth and top CD) results in about the same change in the spectrum. The SCD community calls this phenomenon “parametric correlation.”

Let’s say SCD is being used to monitor the shape of a high-k metal gate structure in production

(Figure 1). Suppose the metal undercut, metal and silicon layer bottom CDs and the silicon sidewall angle are the parameters of interest; various failure analysis techniques have shown that small variations in these parameters can correspond to significant degradation in device performance or yield. Let’s also say that small variations in the undercut length are evident in the SCD spectrum—but in a way that’s indistinguishable from what happens when the metal bottom CD changes. A similar issue was reported by GLOBALFOUNDRIES and IBM, in a paper published in a recent SPIE Proceedings on Advanced Lithography.1 

 

How can you unravel which structural or material variation is causing the change in the spectrum in the presence of parametric correlation? It’s easy if you are certain that one of the two correlated parameters is well controlled—and therefore you can assume that the other parameter is changing. Unfortunately, this is not always the case.

A related way to reduce the variables in the problem is by carrying data forward from previous layers.  If the results for a given layer on a given wafer have already been determined, that information can be used to “fix” the values of some parameters in new layers.  This capability is available today if the wafer has been consistently measured on the same SCD tool. In the future it will be possible to extend this capability to wafers measured on different SCD tools within a fab—as long as those tools are well matched.

When it’s not possible to remove variables by fixing their values, parametric correlation can often be broken by changing the type of SCD measurement: using a different wavelength range; sending the light in at a different azimuth or altitude angle; changing the polarization; or using ellipsometry instead of reflectometry or vice versa. If you have enough different technologies to throw at the problem, you may find one setup that allows the SCD tool to respond sensitively to one of the correlated parameters and not the other.  Sometimes it’s necessary to combine spectra from multiple technologies (angles, polarizations, etc.) or from measuring multiple structures (vertical and horizontal lines, or isolated and dense lines) to come up with a unique solution.

In the example cited earlier, GLOBALFOUNDRIES and IBM found that the use of multiple azimuth angles (parallel and perpendicular to the direction of the dominant lines and spaces) allowed SCD to monitor variations in the metal undercut with high precision and repeatability—and low parametric correlation.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Lanny Mihardja is a product marketing manager in the Films and Scattering Technology (FaST) Division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

References

1.       Matthew Sendelbach, Alok Vaid, Pedro Herrera, Ted Dziura, Michelle Zhang and Arun Srivatsa, “Use of multiple azimuthal angles to enable advanced scatterometry applications,“ Metrology, Inspection, and Process Control for Microlithography XXIV, ed. Christopher J. Raymond, Proc. of SPIE Vol. 7638, 76381G, 2010.

FEI, Hillsboro, OR, has introduced its new Helios NanoLab 450 F1 DualBeam system designed to provide faster, better images of their most advanced device architectures. A new STEM (scanning transmission electron microscope) detector delivers improved contrast between materials, and the new flip stage and rotating nanomanipulator support advanced preparation techniques for complex device architectures, such as finFETs and three-dimensional (3D) memory structures.

Dual beam instruments combine an SEM (scanning electron microscope) for imaging and a FIB (focused ion beam) for milling and deposition. Dual beams also provide STEM imaging capability by adding a detector for collecting transmitted electrons below the sample. An increasingly important application of dual beam instruments is the preparation of the ultra thin samples required for TEM analysis.

The Helios NanoLab 450 F1 is the most recent addition to FEI’s line of DualBeam systems. The FlipStage 3 quickly flips the sample between thinning and STEM viewing positions, and a new rotation axis permits viewing from either side of the section. The EasyLift nanomanipulator provides precise motorized sample manipulation, including rotation, to support automated "lift-out" and advanced preparation procedures, such as inverted thinning.