Category Archives: Metrology

October 4, 2012 – Fab equipment spending continues to soften in 2012, but don’t hope for a reprieve until later in 2013, warns one analyst.

Worldwide wafer fab equipment (WFE) spending is projected at $31.4 billion in 2012, a -13.3% decline from 2011, according to Gartner. But counter to some other industry watchers, the firm now thinks there won’t be a big rebound in 2013 — it’s now forecasting a -0.8% slip next year to $31.2B, before finding its footing again and bouncing back in 2014 with 15.3% growth to $35.9B.

Earlier this summer Gartner foresaw a -8.9% decline in 2012, followed by 7.4% growth in 2013. Less than a month ago SEMI predicted 2013 could be a "golden year" with nearly 17% growth in fab spending.

"The outlook for semiconductor equipment markets has deteriorated as the macro economy has weakened," stated Bob Johnson, research VP at Gartner. After starting the year strong thanks to sub-30nm production ramps at foundries and other logic manufacturers, demand for new equipment logic production will soften as yields improve, leading to declining shipment volumes for the rest of the year."

Fab utilization rates will erode to the low 80% range by the end of this year, slowly increase to about 87% by the end of 2013. (That’s less optimistic than its June outlook which saw mid-80% in mid-2012 and 87% by the end of the year.) Leading-edge capacity will recover slightly better, hitting the high-80% range by year’s end and gradually getting into the low-90% range as 2013 progresses.

Increased demand combined with less-than-mature yields at the leading edge had been hoped to consume extra capacity and raise utilization rates. In leading-edge logic that has in fact helped create inventory shortages, Johnson noted, but "not enough to bring total utilization levels up to desired levels. In the memory segment, some suppliers are even cutting production in an attempt to shore up weak market fundamentals."

Memory is expected to be weak through 2012, with strong declines in DRAM investments and a virtually flat NAND market, the firm notes. Foundry spending has been revised downward for both 2012 and 2013; some foundries have improved their 28nm yields, but mainly for SiON technology, as 28nm high-k/metal gate (HKMG) processes are still yielding below normal. Longer-term, Gartner thinks foundries will ratchet up their spending more in future years due to aggressive development of EUV lithography and 450mm wafer processing.

ProPlus Design Solutions, Inc., a provider of Design for Yield (DFY) solutions that integrate device modeling, parallel SPICE simulation and statistical analysis, unveiled NanoYield, yield prediction and optimization software for memory, logic, analog and digital circuit design.

The company says that NanoYield, which is part of its transistor-level statistical modeling and design and variations-aware product portfolio, is faster than traditional Monte Carlo analysis for both regular three-sigma and advanced six-sigma analysis. It features High Sigma analysis, advanced Monte Carlo analysis and NanoSPICE parallel SPICE simulator to accelerate statistical simulation performance.

NanoYield can be integrated into an existing design flow and predicts yield at early design stages, enabling engineers to evaluate and optimize integrated circuit (IC) designs for optimum yield and performance tradeoffs.

It includes innovative algorithms and parallel technologies to accelerate statistical simulation performance. NanoYield’s engine is the NanoSpice parallel SPICE simulator and contains Monte Carlo Pro (MC-Pro) technology with parallel processing that can deliver 10 to 100 times acceleration over traditional Monte Carlo products. Its High Sigma Pro (HS-Pro) feature licensed and validated by IBM increases high-sigma (e.g., 5-6s) statistical simulation performance by 103 to 106 times, offering accurate predictions of the extreme low-failure rate of cell blocks. With HS-Pro, engineers can predict the yield of repetitive structure circuits, such as memory where small cell failure rate is necessary but not predictable by practical Monte Carlo runs.

The NanoYield design flow starts with circuit design and simulation. Engineers input nominal design and statistical models that represent process variations into NanoYield to calculate process, voltage and temperature (PVT) variations and run Monte Carlo statistical simulations. A report will highlight yield estimations, output distributions and sensitivity and failure analysis, along with some guidelines for optimized designs. Engineers can iterate the design to further optimize it within the NanoYield flow until it meets yield and performance targets.

NanoYield takes input from the command line, the Cadence Virtuoso Analog Design Environment or NanoExplorer, a design exploration and analysis environment used to validate and analyze models and circuit blocks. It is fully compatible with HSPICE from Synopsys and Cadence’s Virtuoso Spectre format inputs.

ProPlus Design Solutions has integrated advanced device modeling, a high-performance SPICE engine and hardware-qualified sampling algorithms into one DFY solution for faster and more accurate statistical analysis. In addition to its circuit simulation software, its product portfolio includes three SPICE modeling solutions. BSIMProPlus is the de-facto golden SPICE model extraction and validation platform. NoisePro/9812B is the de-facto golden low-frequency noise characterization and modeling system. Model Explorer is a model validation and evaluation tool.

by Karen Lo, director, SEMI Taiwan

September 26, 2012 – At the SEMICON Taiwan 2012 450mm Supply Chain Forum on September 7, leading foundries and equipment manufacturers such as TSMC, TEL, Lam Research, Applied Materials, and KLA-Tencor convened to discuss the latest trends in 450nm technology as well as the opportunities and challenges involved. The experts at the forum agreed that many technical obstacles remain on the path to achieve mass production for 450mm wafers by 2018. The industry supply chain must collaborate on innovation to make this vision a reality.

In a presentation entitled "450mm challenges and opportunities," Dr. C.S. Yoo, senior director of the 450mm program at TSMC, said that increasing node complexity means diminishing returns from process miniaturization. For this reason, the industry began studying 450mm wafers with the goal of improving production efficiency, accelerating technology ramp-up, and shortening production cycles. Yoo stated that these advantages, together with higher land and personnel utilization rates, hopefully will offer the semiconductor industry more opportunities for long-term development.

Dr. C.S. Yoo, sr. director of 450mm program, TSMC

According to Yoo, the biggest question in the bid to realize mass production by 2018 is whether the industry can successfully develop the lithography required for 10nm node processes by 2015. At the same time, the industry must solve problems such as rationalizing equipment costs to make return on investments predictable, realizing significant improvements in productivity, and development of automated unmanned foundry operations, smart equipment, and green foundries.

The industry made many technological breakthroughs during the conversion over to 300mm wafers — and Yoo expects that the transition to 450 will produce even more innovative technologies in the future. TSMC will leverage its partnership with the Global 450 Consortium (G450C) as well as work with IC and equipment manufacturers to support the successful transition of the industry to 450mm.

Dr. John Lin, general manager of G450C, introduced the latest developments at G450C, noting that significant advances in 450mm technology have occurred in the past year and industry interest is continuing to build. He stated that the goal of G450C is to begin demonstrating 14nm technology this year and put 10nm into pilot production between 2015 and 2016. Major improvements in the quality of supply for 450mm wafers have been made, and most of the production machinery should complete the prototype phase by 2014. As for lithography — the most crucial part of the project — the preliminary prototype will probably be completed in 2016 and be ready for mass production by 2018.

The CNSE cleanroom is expected to be ready by December 2012; it will be the first 450mm foundry in the world. Lin said that G450C will continue to collaborate with suppliers and SEMI to promote the standardization of 450mm hardware infrastructure components as well as back-end processing and packaging and testing operations. By sharing in the costs of development, the industry will enjoy the benefits offered by 450mm.

Among equipment manufacturers, Dr. Akihisa Sekiguchi (VP and GM of corporate marketing, TEL), Mark Fissel (VP of 450mm program, Lam Research), Kirk Hasserjian (corporate VP of silicon systems group, Applied Materials) and Hubert Altendorfer (senior director of 450mm program, KLA-Tencor) all talked about the challenges involved with developing 450mm equipment.

Seikiguchi believes that 450mm will revolutionize the semiconductor industry and that only companies with strong financial fundamentals will survive due to the high cost of investment. With several years to go until the target of achieving mass production by 2018, Seikiguchi believes that the risks and uncertainty during this period makes proper communication and collaboration between customers, equipment suppliers, foundries and industry associations all the more important. The semiconductor industry should learn from past experience with 300mm transition to avoid making the same mistakes.

Mark Fissel of Lam Research also invoked the transition to 300mm as an example. The first prototype was completed in 1995 but the "dot-com" bubble and other economic factors slowed progress, so it took nine years for 300mm wafer shipments to finally exceed 200mm wafers in 2004. The development of 450mm equipment must also contend with design issues and challenges in terms of technology, capacity, cost and size. Fissel believed that the industry must balance the risk for 450mm development with its long-term ROI.

Kirk Hasserjian of Applied Materials proposed six important factors for a smooth transition to 450mm: Synchronization of the industry’s transition timetable, maturity of lithography, cost sharing, collaboration, innovation, and supply chain readiness.

The eventual wafer size transition will have widespread implications, both for those who make the transition as well as for those that wait. Much of the semiconductor ecosystem is now paying attention to — and planning for — the transition. SEMI is facilitating the development of industry standards and the flow of information throughout the supply chain. SEMI recently launched 450 Central, a web-based information service to help the industry efficiently transition to 450mm-ready solutions and keep the industry informed of important news and perspectives on 450mm wafer processing.

The most knowledgeable and authoritative voices in the industry discuss these tough issues at SEMI events around the world. Our objective is advance the dialog — to convey useful information to our attendees — and to serve as a platform for productive collaboration on these and other industry issues. The upcoming SEMICON Europa (October 9-11) features a 1.5 day session on "Progress in 450mm." For more information on SEMI, visit www.semi.org.

September 21, 2012 – Demand for chip tools fell again in August and is off by -30% from its peak in early summer, fulfilling fears that the second half of 2012 will be sluggish for chipmaking investments, according to the latest data from SEMI.

North America-based manufacturers of semiconductor manufacturing equipment reported $1.12B in orders worldwide in August (a three-month moving average), down -9.2% from July’s slightly downwardly revised level of $1.23B and down -3.6% from a year ago. Worldwide billings slipped to $1.34B, off by -7.4% from a similarly lowered mark in July and off by -8.4% from the same month in 2011.

For the year through August, chip tool bookings are running about -8% off the same pace in 2011 ($10.97B), with billings off by about -15% at $11.16B, according to SEMI’s historical data. Demand clearly peaked in the spring, flattened in the summer, and has now waned significantly. Global demand for semiconductor manufacturing equipment actually started slipping in 2Q12 with softness in just about every region except Taiwan. (As bad as the current pullback is, it’s a far cry from the -40+% dropoff seen toward the end of 2011.)

"The second half of the year continues to show reduced order and billing levels for the 2012 spending cycle," said Dan Tracy, senior director of SEMI Industry Research and Statistics. Industry watchers already were expecting a pullback in demand especially in 3Q12 (and so are the chipmakers themselves), with mixed feelings about a possible bump in 4Q12.

SEMI’s still sticking with its official forecast issued at SEMICON West which predicts a -2.6% decline for the year. "We expect 2012 equipment revenues to decline slightly with total spending for front-end and back-end semiconductor equipment globally remaining at the $40 billion or greater level for the third consecutive year," reiterated Tracy.

SEMI is growing increasingly bullish, however, for 2013, with initial projections of 17% growth in equipment spending.

  Billings Bookings Book-to-bill
March 1,287.6 1,445.7 1.12
April 1,458.7 1,602.8 1.10
May 1,539.3 1,613.7 1.05
June (f) 1,535.7 1,424.3 0.93
July (r) 1,442.8 1,234.6 0.86
August (p) 1,335.5
 1,120.6
 0.84

Semiconductor bookings and billings, 3-month averages. (Source: SEMI)

Researchers are investigating the use of high electron-mobility materials as a way to improve FinFET performance, such as germanium (Ge) for the channels in p-type transistors. But it is difficult to grow Ge directly on a silicon substrate and usually many interface layers are built, each successive layer having a greater concentration of germanium. However, this gives rise to unwanted complexity and cost.

At this year’s International Electron Devices Meeting (IEDM), foundry TSMC will describe an alternative: a heterogeneous epitaxial growth process which for the first time enables Ge to be directly grown on Si. With careful process optimization, the researchers determined that when a fin’s height-width aspect ratio is ~1.4 or greater, imperfections at the Ge-Si interface (called threading dislocations) will be confined to the bottom part of the fin, leaving its top portion—the active area—defect-free. They demonstrated the technique by building devices with excellent subthreshold characteristics (slope=74mV/dec), good short-channel-effects control and high performance (1.2mA/µm at Vdd=1V). The work paves the way for the use of Ge in future p-type FinFETs.

The schematics show representations of the threading dislocations in (a) wide and (b) narrow active areas. In (b) the threading dislocations terminate at the sidewalls, leaving the top part defect-free.

The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM). They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction and improves manufacturability. The new architecture also enables the use of a novel “staircase” bitline contact formation method to minimize fabrication steps and cost. The result is an eight-layer device with a wordline feature size of 37.5nm, bitline feature size of 75 nm, 64 cells per string and a core array efficiency of 63%. The researchers say the technology not only is lower cost than conventional sub-20nm 2D NAND, it can provide 1 Tb of memory if further scaled to 25nm feature sizes. At that size the Macronix device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density.

A previously proposed 3D vertical gate NAND architecture.

An overview of the proposed architectural layout that is said to be an improvement.

 

A cross-sectional views of the new device.

 

TEM electron microscope views of the staircase bitline contacts.

Graphene, a one-atom-thick sheet of carbon atoms, is seen as a potential replacement for silicon in future transistors because it has an exceptional set of properties (high current density, mobility and saturation velocity). However, transistors made of graphene cannot be turned off because graphene has almost no band gap.

Researchers have begun to investigate a new 2D material—molybdenum sulfide (MoS)—which has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly. At the upcoming International Electron Devices Meeting (IEDM), an MIT-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material’s 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter). The transistors demonstrated record MoS mobility (>190 cm2/Vs), an ultra-high on/off current ratio of 108,  record current density (~20 µA/µm) and saturation, and the first GHz RF performance from MoS. The results show MoS may be suitable for mixed-signal applications and for those which require high performance and mechanical flexibility.

 

The lattice structure of MoS.

 

A schematic of the CVD process for growing single-layer MoS.

 

An optical micrograph of single-layer MoS sheets grown by this process, showing great uniformity and coverage.

 

 

Flash memory lifetimes are limited by use, because repeated program/erase (P/E) cycles degrade the tunnel oxide which insulates flash memory cells. In principle, heating the oxide will repair the damage but thermal annealing has been impractical because flash memories can’t tolerate the high temperatures and long baking times required.

At the upcoming International Electron Devices Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed. They modified the wordline from a single-ended to a double-ended structure, which enabled current to be passed through the gate to generate Joule heating. High temperatures (>800° C) thus were generated only in immediate proximity to the gate. The devices demonstrated record-setting endurance of >100 million P/E cycles with excellent data retention. Interestingly, the researchers also saw that the heating enabled faster erasing, which is thought to be temperature-independent.

 

The schematic image above shows the structure of the diode-strapped wordline. A PN diode can be formed directly on top of the wordline, and local interconnect can be used to connect to the metal heat plates.

While conventional charge-based memory is approaching fundamental scaling limits, several so-called “emerging memories” have migrated from laboratory samples to integrated products. Among various emerging memory technologies, MRAM (magnetoresistive random access memory) has been making impressive progress, ahead of other emerging memories, and has demonstrated the capability to be a successor to DRAM or SRAM. MRAM data is stored via magnetic moments. Parallel or anti-parallel magnetic moments in MRAM stacks present the “0” or “1” state. In earlier generations of MRAM, these states were switched by current-induced magnetic field but that is an obstacle for scaling.

The invention of ST (spin-torque) MRAM, which is switched by injecting spin-polarized tunneling current, removes the scaling limitation. In an invited paper at the International Electron Devices Meeting, researchers from Everspin Technologies will describe how they built the largest functional ST-MRAM circuit ever built, a 64-Mb device with good electrical characteristics. The work shows that MRAM technology is fast approaching commercialization.

Everspin MRAM products employ a one transistor, one magnetic tunnel junction (MTJ) memory cell for the storage element. The MTJ is composed of a fixed magnetic layer, a thin dielectric tunnel barrier and a free magnetic layer. When a bias is applied to the MTJ, electrons that are spin polarized by the magnetic layers traverse the dielectric barrier through a process known as tunneling. The MTJ device has a low resistance when the magnetic moment of the free layer is parallel to the fixed layer and a high resistance when the free layer moment is oriented anti-parallel to the fixed layer moment.

ST-MRAM uses an alternate method for programming an MTJ element that has the potential to further simplify the MRAM cell and reduce write power. Programming is accomplished by driving current directly through the MTJ to change the direction of polarization. The read operation is accomplished by sensing the MTJ resistance, just like Toggle MRAM.

Everpsin says that ST-MRAM products will offer a new storage class memory solution for non-volatile buffers and caching applications as well as deliver a new nanosecond-class, gigabyte-per-second non-volatile storage tier. Using a spin-polarized current for switching, ST-MRAM can overcome scaling limitations to address persistent DRAM applications in densities from megabits to gigabits.

 

The device has a wide separation between applied and breakdown voltages— the more separation, the wider the device operation margin.

 

This “shmoo plot,” is a graphical display of the ST-MRAM’s performance over a range of voltages. The green area signifies there were no failures of the memory as voltages increased, indicating that its design is robust.

CMOS technology uses the two types of MOSFET transistors (N and P) working together in a complementary fashion: when one is on, the other is off. However, the conflicting materials and design requirements for N- and P-type devices make achieving balanced performance and desired threshold voltage challenging.

Meanwhile, extremely thin SOI (ETSOI) technology is a viable device architecture for continued CMOS scaling to 22nm and beyond. Among the reasons why are that it offers superior short-channel control and low device variability with undoped channels.

At the International Electron Devices Meeting (IEDM) in December, a team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device. They integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. A novel STI-last (isolation-last) process makes the hybrid architecture possible. The researchers built a ring oscillator circuit to benchmark performance, and the hybrid planar devices enabled the fastest ring oscillator ever reported, with a delay of only 11.2ps/stage at 0.7V, even better than FinFETs.

 

An electron microscope view at the top and an EDX (energy-dispersive X-ray) spectroscopic view below it of a SiGe-channel PFET with 6-nm channel thickness, 22-nm gate length, 100-nm contacted gate pitch, high-k/metal gate architecture and ISBD SiGe raised source drain. Source: IBM.