Category Archives: Metrology

August 2, 2012 — The ConFab, Solid State Technology’s invitation-only event for the semiconductor industry, took place in June, with presenters from top companies and analyst firms. If you couldn’t be there, check out all the coverage from the event — reports, presentations, video interviews and more — via the links below.

Presentations and analysis

A virtual IDM concept can unite foundries, fabless companies, and packaging houses

The ConFab 2012 opened in Las Vegas with a keynote address from John Chen, PhD, VP of technology and foundry operations at Nvidia Corporation.

@ The ConFab: How to prevail over silicon cycles

At The ConFab’s opening session, “The Economic Outlook for the Semiconductor Industry,” capex was a major point of interest. Jackie Sturm of Intel, Dan Hutcheson of VLSIresearch, and Jim Feldhan of Semico all touched on it, with Hutcheson expanding on the idea of capex trends.

@ The ConFab: Semiconductor industry experts look to the future

The ConFab’s sessions opened with “The Economic Outlook for the Semiconductor Industry,” featuring Jackie Sturm of Intel, Dan Hutcheson of VLSIresearch, and Jim Feldhan of Semico.

 

Legacy fab issues @ The ConFab 2012

Older production facilities face equipment obsolescence; skills obsolescence; scarce availability of parts, software, and support; and equipment capability extension and tool re-use. At the ConFab 2012 Executive Roundtable, representatives from Sematech/ISMI, IDMs, OEMs, equipment dealers, and others.

 

ISMI addresses tool obsolescence

Speaking at The ConFab 2012, Sanjay Rajguru, director of ISMI, pointed out that more than half the current fab capacity today comes from facilities that are more than ten years old, which is creating a problem with equipment obsolescence.

@ The ConFab: Supply chain or supply web for 3D packaging?

With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of front-end fab at the foundry and back-end fab at the packaging and test house is falling apart. The ConFab session, “Advanced Packaging and Progress in 3D Integration,” focused heavily on this dynamic.

 

3D/2.5D packaging technologies @ The ConFab

As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue “Advanced Packaging and Progress in 3D Integration,” a session focused on the higher I/O density and other performance benefits of 3D packaging.

 

The ConFab: Chasing price, power, and performance

At The ConFab 2012, fabless companies and foundries have a common goal: reduce power, increase performance and reduce price (not necessarily in that order).

Semiconductors in the smart society: Next-generation connectivity @ The ConFab

Day 2 of The ConFab opened in Las Vegas with Ali Sebt, CEO of Renesas Electronics America, delivering “Smart Society, the Sensing Era and Signal Chain.”

 

The ConFab: Turning the technology knobs for system scaling

Chip scaling will go on for the foreseeable future, enabling new product with more compute power, more memory, faster on-chip communication. That was one of the conclusions put forth by imec’s An Steegen, speaking on technology trends at The ConFab 2012.

Big data and today’s semiconductor industry
Upon arriving at The ConFab’s venue, The Encore at The Wynn, Solid State Technology chief editor Pete Singer had an impromptu discussion about how the semiconductor industry has changed over the years, around smartphones and “big data,” with colleagues. Over 90% of the world’s data has been created in the last two years. What is big data? According to IBM, every day, we create 2.5 quintillion bytes of data.

ConFab interviews

G450 Consortium’s Tom Jefferson on 450mm timeline

Tom Jefferson, G450 Consortium, shares an update on 450mm wafers for semiconductor manufacturing. The consortium is adding staff and ramping its silicon supply, and getting ready for equipment selection.

Bill Tobey on EUV lithography

Bill Tobey, president of ACT International Consulting, speaks about the evolution of extreme ultra violet (EUV) lithography at The ConFab 2012.

Amkor’s Ron Huemoeller on 3D packaging readiness

Ron Huemoeller of Amkor presented in the Advanced Packaging session of Solid State Technology’s The ConFab. He speaks with editor-in-chief Pete Singer.

ISMI’s Bill Ross on managing legacy fabs and supply obsolescence

Bill Ross, ISMI, is moderating a session today at The ConFab 2012 on managing legacy semiconductor fabs and dealing with tool and materials obsolescence at 200mm and smaller. He speaks with Pete Singer about coping with these changes.

Ali Sebt advocates switch from On/Off to smart sensing

Ali Sebt, CEO of Renesas Electronics America, keynoted Day 2 of Solid State Technology’s The ConFab 2012. Here, he discusses the role of inexpensive sensors and microcontrollers in energy savings, in a video interview.

Dai Nippon Printing’s Naoya Hayashi on mask readiness

Naoya Hayashi, research fellow for electronic device operations at Dai Nippon Printing, speaks with Solid State Technology chief editor Pete Singer during The ConFab 2012. Hayashi presented “NGL Mask Readiness” in The ConFab’s session on technology trends.

Semico’s Jim Feldhan on SSDs and semiconductor trends

Jim Feldhan of Semico speaks with Solid State Technology editor-in-chief Pete Singer about expectations for the semiconductor industry and solid-state drives.

Nvidia’s John Chen on semiconductor industry success

John Chen of Nvidia gave the opening keynote address of The ConFab 2012, presenting the concept of a “virtual IDM” comprising fabless companies, semiconductor foundries, and packaging houses working seamlessly together.

VLSI Research’s Dan Hutcheson on silicon cycles

Dan Hutcheson, VLSI Research Inc. spoke with Solid State Technology editor-in-chief Pete Singer at The ConFab 2012. Hutcheson presented on the cyclical nature of the semiconductor industry.

Visit the ConFab’s website here.

July 31, 2012 — EDAX Inc., a leader in X-ray microanalysis and electron diffraction instrumentation, introduced the Octane Series silicon drift detectors (SDD) for its TEAM EDS Analysis Systems on electron microscopes.

Also read: Metrology: EFTEM provides elemental mapping at nanometer resolution

Octane SDD enable high-quality EDS data collection at faster speeds, without detrimental losses in data quality at high count rates.

The Octane Series includes four models — the Pro, Plus, Super, and Ultra — for the specific demands of key microanalysis applications. The series’ advanced spectrometer design and state-of-the-art electronics enable energy resolution down to 121eV, with high efficiency in converting input counts into stored data. Its resolution stability translates into higher-quality data at high input count rates.
Pairing the new SDD technology with EDAX’s TEAM EDS software allows users to take advantage of the Smart Features in TEAM Systems to optimize their analysis time and get the best data possible from their sample. In addition to Smart Quant and EXpert ID, the Smart Pulse Pile-Up Correction feature minimizes concerns typical of high count rate collections and allows maximum use of SDD technology.

“Extraction of high-resolution quantitative analysis is now possible from a map collected at 200,000 counts per second,” comments Mike Coy, technical product manager for microanalysis at EDAX.

EDAX supplies Energy Dispersive Microanalysis, Electron Backscatter Diffraction and X-ray Fluorescence instrumentation. EDAX designs, manufactures, installs and services high-quality products and systems for leading companies in the semiconductor, metals, geological, pharmaceutical, biomaterials, and ceramics markets. EDAX is a unit of AMETEK Materials Analysis Division. AMETEK, Inc. is a leading global manufacturer of electronic instruments and electromechanical devices. Website: www.edax.com.

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July 30, 2012 — FEI (NASDAQ:FEIC), imaging and analysis systems maker, launched the Verios extreme-high-resolution (XHR) scanning electron microscope (SEM) for metrology on beam-sensitive and sub-namometer-scale materials in advanced semiconductors.

The SEM can be used for process control at the 22nm semiconductor technology node and below, combined with FEI’s IC3D software. The SEM also suits materials science imaging, extending SEM into areas previously only served by tunneling electron microscopy (TEM) or other techniques.

The Verios provides sub-nanometer resolution and enhanced contrast for beam-sensitive materials. A second-generation FEI XHR SEM, it enables sensitivity to surface detail even at low kV, thanks to advanced optics. Users can switch quickly between various operating conditions, maintain sample cleanliness, and obtain sub-nanometer resolution at any accelerating voltage from 1 kV to 30 kV. New detection technologies come from optimized signal collection and advanced filtering abilities, for better contrast generation and metrology on a greater range of samples such as non-conductive or beam-sensitive materials.

FEI (Nasdaq: FEIC) is a leading diversified scientific instruments company providing electron- and ion-beam microscopes and solutions for nanoscale applications across many industries. More information can be found at: www.fei.com.

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July 24, 2012 — SEMI recently conducted a survey of semiconductor fab equipment and materials suppliers, finding that 60+% of respondents say that intellectual property (IP) challenges have had an adverse impact on their companies.

Also read: Semiconductor IP myths and revenue growth

IP supports a company’s innovation and is fundamental to new technologies and methods. A relatively high percent of revenue is reinvested into R&D to create IP in the semiconductor industry, and IP fuels competitiveness in the supply chain.

On average, semiconductor equipment and materials companies invest 10-15% of their revenues back into R&D each year, with 2011’s R&D investment translating to $9-14 billion. Semiconductor equipment and materials companies have unique challenges associated with their IP, but realizing a return on their R&D investment is still essential.

The SEMI IP survey was sent to a global group of SEMI members and almost half responded. Over 60% of companies reported that IP challenges have translated into an adverse impact on their companies. About 75% of the companies responding had pursued legal action against IP violators. 

In terms of the types of violations experienced, patent infringement and counterfeiting were the recurring themes, with some regions more problematic than others. The survey also asked whether the situation in each region was improving, worsening, or staying the same.

This survey information will be used in SEMI’s efforts on IP protection with governments and partners around the world.

To download the IP White Paper, visit: www.semi.org/en/2012IPWhitePaper. SEMI is a global industry association serving the nano- and microelectronics manufacturing supply chains. For more information, visit www.semi.org.

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July 23, 2012 — Researchers sponsored by Semiconductor Research Corporation (SRC), a leading university-research consortium for semiconductors and related technologies, developed new sensor-based metrology technology that can significantly reduce water and related energy usage during semiconductor manufacturing.

The sensor-based real-time monitoring approach showed 30% less water and energy used for ultra-clean chip production. The SRC Engineering Research Center (ERC) for Environmentally Benign Semiconductor Manufacturing team at the University of Arizona (UA) calls this “the most significant metrology improvements for the rinse and cleaning of wafers in more than a decade.”

Figure. In-situ monitors provide unprecedented control of water and chemical usage during surface preparation for silicon wafers. Highly sensitive sensors, like those shown in this micrograph of a sensing channel, can reduce the amount of resources needed for the cleaning of surfaces.

Surface preparation, when semiconductor wafers are cleaned, rinsed, and dried to prevent defects between various front end of line and back end of line (FEOL/BEOL) steps, is one of the largest water-consuming processes in semiconductor manufacturing. The International Technology Roadmap for Semiconductors (ITRS) identifies lower resource utilization at current and future fabrication steps among its goals.

Also read: Semiconductor fabs use significantly less energy today, but work remains from ISMI.

The ERC team’s real-time monitoring approach is applicable to current cleaning processes for 300mm silicon wafers, and the gain is expected to be especially beneficial when the industry transitions to 450mm wafers. At 450mm, chipmakers will need to clean and prep a wafer surface that is more than twice the size of current state-of-art wafers.

Current surface preparation practices are recipe-based and not controlled with real-time, in-line monitoring of the process steps. Surface prep is carried out without feedback or control, with a large cushion of safety to overcome lack of regulation. This sizeable safety factor creates unnecessary waste of chemicals, water and energy.

“The challenge is how to balance a minimal application of precious resources with the grave risk of allowing contamination to occur, which can kill huge investments made elsewhere in the fabrication process,” said Dr. Steve Hillenius, executive vice president for SRC.

The next step is to commercialize the monitoring technology, said Farhang Shadman, lead researcher and the ERC director at UA for the SRC-funded research. Semiconductor equipment and manufacturing companies, as well as other industries that use ultra-clean for planar or patterned surfaces and small structures could use the real-time metrology technology to improve resource management. Examples include optics, optoelectronics, and flat panel display (FPD) makers.

For more information about the research, please visit http://dx.doi.org/10.1109/TSM.2010.2089542. Contributors for the joint effort include K. Dhane, J. Han, J. Yan, O. Mahdavi, D. Zamani, B. Vermeire and F. Shadman.

SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. For more information, visit www.src.org.

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July 23, 2012 — The market for refurbished semiconductor manufacturing equipment has grown steadily — estimated at $6 billion (Semico report, 2010). Fabs looking to increase capacity quickly and minimize costs commonly acquire secondary equipment.

Various companies, from refurbishers to brokers, sell secondary semiconductor equipment at a lower cost than new equipment. While finding used tools is easy, semiconductor manufacturers must consider the additional installation, refurbishment, reconfiguration, warranty, service, support, and other factors involved in using secondary equipment.

Fabs typically need a number of tools, requiring a fab to approach different vendors who handle each individual tool. Vendors may only be capable of handling part of the fab’s needs rather than a full turnkey project, necessitating a project manager at the chipmaker to oversee the process. Adhering to timelines, and ensuring quality and reliability, present significant challenges.

Flexibility creates stability and predictability

Instead of providing individual tools or services, a different model handles the fab’s needs as a single, seamless turnkey project.

In the common refurbisher/broker model, where neither party is fully integrated with the other, there is a potential for delays and cost over-runs as negotiation for core tools and configuration design issues arise. Refurbishment should be just one step of a refurbishment project, wherein a team of experts ensure quality and reliability at every stage — delivering on time, ramping to schedule and staying within budget are equally important.

The turnkey services model integrates each step as part of a process rather than a single service or product sold to a fab. This can be called a "project-process model" (as compared to providing a single step solution in which the user seeks out the supplier of the next step in the process elsewhere).

Secondary equipment options

The project-turnkey process aims to transform a complex series of tasks, each with a high degree of variability, into a predictable outcome — on time and within budget. To achieve this, the project begins with analysis of the fab’s needs, building a plan to deliver this at the highest quality, lowest risk, and lowest cost.

Once the fab’s configuration needs are understood, numerous options are available: for equipment there is anything from ‘as-is’ to Tier II process demonstration. Purchasing secondary equipment ‘as-is’ is the cheapest solution but it is also the riskiest. It is often difficult to accurately understand the condition of the equipment and if it will match the configuration needs of the fab. There are indeed no guarantees that the equipment will work. Some fabs will take this risk, as they have the in-house engineering capabilities to work with the tool.

On the other hand, a full Tier II installation eliminates the risk of the unpredictable at an additional cost. The turnkey model dictates that the project does not end at installation but rather all equipment is installed under warranty with the option of expert escalation, should the need arise.

Another way to minimize costs is for fabs to work with their equipment source to identify equipment running at other facilities, which can be de-installed, shipped and re-installed at the fab (this is known as a relocation project). From a cost and time to ramp perspective, this is normally the most effective way of getting tools in to production. However, the shutdown, documentation and de-install of the tools are critical steps in this process. It is not uncommon for fabs to purchase operational equipment only later to have it shut down incorrectly or without fingerprinting. This makes start up challenging and creates needless expense. When handling a turnkey project where tools from another facility are utilized, the best method is to shut down tool adhering to a well-documented iterative process. This helps ensure the same performance in the new location. Occasionally, relocation procedures may facilitate opportunities for repair or modification before install.

Whether its a complete Tier II turnkey approach or a blended approach with relocation tools, the aim is effective tool acquisition at minimal cost, for predictable, stable fab expansion within the company’s ramp timing.

Figure. RED Equipment warehouse.

Buying ahead of the market

Semiconductor manufacturing equipment is expensive. Without an acquisition model, buying a tool could easily be seen as a given expense — a certain tool is needed, it costs a certain amount, and there is nothing much that can be done about it. The turnkey project-process takes a different approach. Utilizing a more flexible model, users can obtain more, at lower cost.

Turnkey equipment suppliers can hold a large inventory, and buy the tools for customers’ future needs ahead of their budget availability. Often, fab tools become available when a fab’s capital expenditures (capex) budget has not yet been approved.

Buying ahead of the market can ease both cost and availability concerns. The market for used equipment is just as dynamic as the rest of the semiconductor industry, with its own cycles. When the market is good, tools become scarce and their prices go up. Often, tools are available at a lower cost in a weak market, but chipmakers do not have budget to acquire them. A forward-thinking partnership between semiconductor manufacturer and secondary equipment supplier can manipulate the ups and downs of semiconductors to their advantage. This approach requires a very close working relationship between the turnkey provider and fab.

A close working relationship with the equipment supplier may also yield alternate procurement models to the ones the fab envisioned, in the event that the requested core tools are not available in the market; the OEM no longer exists or no longer supports the tool; or parts or consumables are highly priced. In these cases, an alternate model may be a better option. The turnkey project model takes these situations into consideration, while a ‘one tool, one service’ model does not.

Engineering services

Usually, semiconductor fabs need more than just equipment for a new line or expansion. The engineering services required are unique to each fab and project, based on maturity of technology, experience of the chipmaker’s engineering team, and fab location. However, there is often an ongoing need for post-install engineering services, such as spares, training, or technical support.

Where appropriate, an engineering team from a turnkey equipment source will suggest cost-saving options during the design phase of the project. Ongoing spare parts costs can be reduced by qualifying new sources during the ramp. For example, alternate quartz in a furnace or strip tool, or a different type of ceramic in a process chamber. Installing tools to Tier II qualification provides the fab with the opportunity to fast-track part changes into their facility, avoiding months of process requalification.

Conclusion

The turnkey provider is motivated to ensure that a fab’s expansion project happens. The single tool provider is focused on selling the tool type that they specialize in without considering the whole view.

The turnkey model sees refurbishment from the fab’s point of view rather than that of the product or service provider. Refurbishment is more than just tool selection and adjustment. Frustration and expense can be mitigated by planning ahead and seeing the whole picture — handling the refurbishment as a project rather than simply providing a single tool or service. By equipment supplier/fab partnership, the resulting purchases meet technical requirements and time constraints, and minimize risk for the fab.

Carl McMahon is VP of North America sales at RED Equipment. He holds a BS in Information Technology and Economics from The Open University, United Kingdom.

Also read: Refurbished equipment: heating up and coming of age

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July 17, 2012 — Sonoscan unveiled its Lab Model 9600 C-SAM acoustic micro imaging system to serve laboratory/failure analysis applications and for use in low-volume semiconductor production inspection.

Model 9600 incorporates advanced Sonolytics software with a graphical user interface (GUI). PolyGate analysis software for multilayer or bulk materials analysis is standard. PolyGate permits the user to set up to 100 individual gates per channel for a sample. During a single scan, PolyGate produces a separate acoustic image for each gate. Depending on the material, each gate may be as thin as 20µm.

The 9600 is tailored for high-performance laboratory acoustic microscopy for budget-conscious users.

The 9600 uses a linear motor for X-axis scanning, a tower-mounted scan reference platform, and is rated for Class 1000 cleanroom operation. It has a portfolio of optional features available.

Also read: Sonoscan software enables acoustic imaging of 3D IC and die stacks

Sonoscan makes acoustic microscopes and sophisticated acoustic micro imaging systems, widely used for nondestructive analysis of defects in industrial products and semiconductor devices. Internet: www.sonoscan.com.

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July 16, 2012 — SEMICON West kicked off with a surprise announcement regarding Intel’s strategic investment into ASML, but generally the event highlighted trends “as expected” in the semiconductor manufacturing supply chain, say Barclays Capital analysts.

Most semiconductor production equipment makers are seeing an order/shipment pull-back in Q3. Rising capital intensity, chip manufacturing complexities, Intel’s march to 14nm, and foundry’s 20nm investments contribute toward Q4 and 2013 capex optimism. Barclays investigates this trend further in Q3 semiconductor tool capex pull-back: Seasonal, expect Q4 uptick

Seasonality is now indeed winning over cyclicality, with Q3 drifting into a lull as it did in 2011 and 2010. Consensus estimates clearly are going to move lower given the cautious tone and the expectations for a near term pause in order.

Barclays is maintaining its wafer fab equipment capex estimate for 2012 at $31.5 billion (flattish over 2011) and for 2013 at $31.5 billion to 34.5 billion (flat to +10% over 2012).

Barclays is also keeping its lithography tool forecast for 2012 intact: immersion lithography demand is holding up with the lack of extreme ultraviolet (EUV) availability. Expect KrF lithography spending to taper in H2 2012.

SOC test is also going to taper in H2, but still tracking to be about $2.6 billion capex in 2012.

The surprise 450mm/EUV lithography tie up between ASML and Intel made a splash at SEMICON West. According to Bloomberg, sources reported that Samsung Electronics Co., Ltd. and TSMC are in talks to acquire about 10% stake in ASML as well. Look for more analysis on blogger Dick James’ page, in The Elephant Has Left the Room — 450 mm is a Go!

Intel continues to be the main driver of 450mm adoption, which could benefit more than ASML (look for Edwards Vacuum to also support the 450mm transisiton at Intel sometime in the 2018/2019 timeframe).

Cymer continues to the leader within the group of lithography light-source contenders, with Extreme/Ushio still experiencing reliability issues with its IMEC source and Gigaphoton yet to assemble an integrated source, Barclays concludes.

Read the full report at http://live.barcap.com/PRC/servlets/dv.search?contentPubID=FC1838914&bcllink=decode

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July 13, 2012 – BUSINESS WIRE — Bruker Corporation introduced three 450mm X-ray and atomic force microscopy (AFM) semiconductor metrology tools — the InSight-450 3DAFM, the D8 FABLINE X-ray system, and the S8 FABLINE-T X-ray system — during SEMICON West, this week in San Francisco, CA.

Eliminating the need for model setup, and providing TEM-like accuracy in fractions of the time without wafer damage, Bruker’s automated atomic force microscopes (AFMs) enable critical technology development and continued process control in semiconductor production. Based on the production-proven InSight 3DAFM platform for 300mm, the InSight-450 3DAFM suits various roughness, depth and CD applications. Capabilities include bare wafer process validation, roughness characterization and pit/bump/scratch defect metrology; incoming substrate qualification; thin film and epitaxial deposition performance with micro/nano roughness and angstrom-level step height precision; etch depth metrology for process development and control, in-line resist profile measurements of CD, SWA, and LER with full TEM-like profiles; and CMP flatness performance to monitor dishing and erosion. All of these applications are available in a single tool with no modeling required, full NIST traceability and no material or wafer damage, making it the ideal tool to provide early learning in 450mm process development with scalability to 450mm production.

Bruker’s X-ray metrology provides a reliable, accurate and non-contact method of characterizing various essential semi parameters without the need to use a reference. The next-generation D8 FABLINE is equipped with the latest high-brilliance X-ray sources, detector technology and user-friendly software for improved data analysis. The system provides various in-line, thin film X-ray measurements for front end of line (FEOL) and back end of line (BEOL) process monitoring on blank or product wafers. It can be used to determine thickness, composition and strain in SiGe, SiC, SOI, III-V on Si; as well as composition and thickness for metal films and stacks, including ALD layers. New and emerging device processing creates metal contamination control challenges for IC manufacturing. Bruker developed the S8 FABLINE-T TXRF (Total X-ray Reflection Fluorescence) for non-destructive trace metal and light element contamination analysis in semiconductor applications.

“Both X-Ray and high-resolution AFM technologies have been identified by the 2011 International Technology Roadmap as critical for the success of future semiconductor technology nodes,” said Bruker AXS division president Dr. Frank Burgäzy, speaking about the industry transistor from 300mm to 450mm wafers. Also read: The elephant has left the room — 450mm is a go! from blogger Dick James, Chipworks.

Bruker Corporation (NASDAQ:BRKR) provides high-performance scientific instruments and solutions for molecular and materials research, as well as for industrial and applied analysis. For more information about Bruker Corporation, please visit www.bruker.com.

Check out Solid State Technology’s coverage of SEMICON West 2012!