Category Archives: Packaging and Testing

Intel Corporation today announced two new technologies for Intel Custom Foundry customers that need cost-effective advanced packaging and test technologies.

Embedded Multi-die Interconnect Bridge (EMIB), available to 14nm foundry customers, is a breakthrough that enables a lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package. Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate. EMIB eliminates the need for TSVs and specialized interposer silicon that add complexity and cost.

“The EMIB technology enables new on-package functionality that may have been too costly to pursue with previous solutions,” said Babak Sabi, Intel vice president and director, Assembly and Test Technology Development.

Intel also announced the availability of its revolutionary High Density Modular Test (HDMT) platform. HDMT, a combination of hardware and software modules, is Intel’s test technology platform that targets a range of products in diverse markets including server, client, system on chip, and Internet of Things. Until now, this capability was only available internally for Intel products. Today’s announcement makes HDMT available to customers of Intel Custom Foundry.

“We developed the HDMT platform to enable rapid test development and unit-level process control. This proven capability significantly reduces costs compared to traditional test platforms. HDMT reduces time to market and improves productivity as it uses a common platform from low-volume product debug up to high-volume production,” said Sabi.

EMIB is available to foundry customers for product sampling in 2015 and HDMT is available immediately.

S2C, Inc. announced today the opening of a direct sales and support office in Seoul, Korea, appointing Suk-Ha Lee (SH Lee) as country manager.

“We’ve had numerous requests for our systems in Korea – this is clearly an opportunity for us,” said Toshio Nakama, CEO of S2C. “Opening an office in Seoul is a natural decision. A lot of high-end consumer products are developed in Korea, all built upon complex SoCs driven by sophisticated software. Our solutions meet this challenge perfectly.”

Heading the new office is SH Lee – a professional with 24 years of sales and customer support experience in the Korean EDA market. “I couldn’t be more excited about this opportunity,” said Lee. “Customer satisfaction is always first and foremost in my mind. S2C has the right product at the right time – I look forward to supporting our customers with this important technology, insuring their experience is positive and productive.”

Prior to his position at S2C, Mr. Lee was the country manager for Forte Design Systems in Korea. Previous positions include country manager for Synplicity Korea, and Major Accounts Manager for Synopsys Korea. Mr. Lee’s experience includes ESL solutions, FPGA applications, and ASIC design flows.

Headquartered in San Jose, California, S2C provides SoC prototyping solutions.

MEMSIC, Inc., a MEMS sensing solution provider, announced today the availability of its MXC400xXC, the world’s first monolithic 3D accelerometer, and also the first 3D accelerometer to utilize WLP technology. The technology breakthrough in combining the 3D IC sensor with full WLP translates directly to a 60% reduction in cost and a 50% reduction in size, enabling a new generation of mobile consumer devices including phones, tablets, toys and wearable devices.

The key to this breakthrough is MEMSIC’s proprietary and patented thermal accelerometer technology, in which the MEMS sensor structure is etched directly into standard CMOS wafers, enabling the world’s only CMOS monolithic solution. This technique uses thermal convection of heated gas molecules inside a sealed cavity to sense acceleration or inclination, and has been used for many years in MEMSIC’s products for automotive stability control and rollover detection, digital cameras, projectors and many other applications. MEMSIC’s designers have now taken the technology to a new level by combining 3D sensing with full WLP while keeping the same small size and low cost.

The MXC400xXC offers a number of benefits to system designers of space- and cost-sensitive consumer devices. In addition to offering the world’s lowest cost, the device provides 12-bit resolution on all three axes, programmable FSR of ±2g/±4g/ ±8g, an 8-bit temperature output, plus orientation/shake detection. With a package size of 1.2 x 1.7 mm, board space is reduced by 50% over industry-standard 2×2 mm solutions. And like all MEMSIC thermal accelerometers, the MXC400xXC has no moving parts, making the sensor structure extremely robust to shock and vibration (withstands shock in excess of 200,000g with no change in sensor performance). This is critically important to wearable and many consumer applications.

Dr. Yang Zhao, MEMSIC CEO and Founder, commented “While we have been supplying thermal accelerometers for more than a decade, the MXC400xXC is a real breakthrough in sensor design, signal processing architecture and MEMS WLP. This is the industry’s first and only monolithic 3D accelerometer with full WLP technology, enabling us to achieve a new level of size and cost, which are critical for mobile consumer devices.”

University of California, Davis researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, are exploring new materials and device structures to develop next-generation memory technologies.

The research promises to help data storage companies advance their technologies with predicted benefits including increased speed, lower costs, higher capacity, more reliability and improved energy efficiency compared to today’s magnetic hard disk drive and solid state random access memory (RAM) solutions.

Conducted by UC Davis’ Takamura Research Group that has extensive experience in the growth and characterization of complex oxide thin films, heterostructures and nanostructures, the research involves leveraging complex oxides to manipulate magnetic domain walls within the wires of semiconductor memory devices at nanoscale dimensions. This work utilized sophisticated facilities available through the network of Department of Energy-funded national laboratories at the Center for Nanophase Materials Sciences, Oak Ridge National Laboratory and the Advanced Light Source, Lawrence Berkeley National Laboratory.

“We were inspired by the ‘Race Track Memory’ developed at IBM and believe complex oxides have the potential to provide additional degrees of freedom that may enable more efficient and reliable manipulation of magnetic domain walls,” said Yayoi Takamura, Associate Professor, Department of Chemical Engineering and Materials Science, UC Davis.

Existing magnetic hard disk drive and solid state RAM solutions store data either based on the magnetic or electronic state of the storage medium. Hard disk drives provide a lower cost solution for ultra-dense storage, but are relatively slow and suffer reliability issues due to the movement of mechanical parts. Solid state solutions, such as Flash memory for long-term storage and DRAM for short-term storage, offer higher access speeds, but can store fewer bits per unit area and are significantly more costly per bit of data stored.

An alternative technology that may address both of these shortcomings is based on the manipulation of magnetic domain walls, regions that separate two magnetic regions. This technology, originally proposed by IBM researchers and named ‘Race Track Memory,’ is where the UC Davis work picked up.

With most previous studies focused on metallic magnetic materials and their alloys due to well-established processing steps and high Curie temperatures, challenges still remain in manipulating parameters such as the type of domain walls formed, their position within the nanowires and their controlled movement along the length of the nanowires.

The UC Davis research investigates the use of complex oxides, such as La0.67Sr0.33MnO3 (LSMO), and heterostructures with other complex oxides as candidate materials. Complex oxides are part of an exciting new class of so-called “multifunctional’ materials that exhibit multiple properties (e.g. electronic, magnetic, etc.) and may thereby enable multiple functions in a single device. For the case of LSMO, it is a half metal, exhibits colossal magnetoresistance (CMR), meaning it can dramatically change electrical resistance in the presence of a magnetic field, and undergoes a simultaneous ferromagnetic-to-paramagnetic and metal-to-insulator transition at its Curie temperature.

In addition, these properties are sensitive to external stimuli, such as applied magnetic/electric fields, light irradiation, pressure and temperature. These attributes may allow researchers to better manipulate the position and movement of the magnetic domain walls along the length of the nanowires.

“While still in the early stages, the innovative research from the UC Davis team is helping the industry gain a better fundamental understanding linking the chemical, structural, magnetic and electronic properties of next-generation memory materials,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

New Japan Radio Co., Ltd. and United Microelectronics Corporation, a global semiconductor foundry, today announced that the two companies have successfully collaborated to achieve high-volume manufacturing for NJR’s MEMS microphone products. Adding UMC’s MEMS manufacturing capabilities to NJR’s Fukuoka and Kawagoe fabs will ensure NJR’s smooth and scaled production ramp to address this rapidly growing market. To date, NJR has already surpassed 100 million shipments for MEMS microphone ICs.

Mr. Takaaki Murata, NJR Director & Manager of its corporate office said, “NJR’s rapid growth in the MEMS microphone business cannot be achieved without UMC’s close support, technical expertise and manufacturing capability. Porting MEMS devices to foundry is extremely difficult since MEMS ICs contain mechanical modules, which cannot be electronically simulated as semiconductor devices. UMC’s superior process control expertise and manufacturing capability ensured a perfect performance match, equal to that of our own mother fab. With UMC’s strong support, we expect NJR’s MEMS shipments to continue its growth, enabling us to gain market share.”

The MEMS microphone market is experiencing high growth, as conventional ECM (electro condenser microphone) is being phased out in favor of MEMS for today’s most popular smartphones. To accommodate NJR’s current and future MEMS growth and help NJR maintain a market leadership position in the sector, UMC expanded its MEMS manufacturing capacity and resources, positioning the foundry as NJR’s joint process development center for future generations of high performance MEMS for microphones and other applications.

J H Shyu, senior vice president of Production and Operation Integration at UMC, commented, “NJR has been a wonderful UMC partner for many years. We have achieved several significant goals together, including the delivery of the world’s lowest noise OpAmp to market. It is a great pleasure to add another important area of corroboration in the form of MEMS devices. We look forward to continuing our partnership with NJR in both process technology and manufacturing to realize additional milestones in the future.”

The SEMI Strategic Materials Conference, held September 30–October 1 in Santa Clara, Calif., will examine the drivers for new materials and how they impact material suppliers and the value chain they serve. The theme this year is “Materials Matter — Enabling the Future of IC Fabrication and Packaging,” delving into the market opportunities, scaling challenges, and emerging solutions to meet the sub-20nm technology node production challenges. SMC is the only conference dedicated to exploring the synergies, trends and business opportunities in advanced electronic materials. The agenda includes presentations by market analysts, leading device manufacturers, as well as equipment and material suppliers.

The increasing semiconductor content in mobile, computing, entertainment, and transportation are driving demands for higher performance and lower power consumption. The IC industry today is moving beyond scaling as the primary driver and looking to new materials and architectures.  Candidate materials span the spectrum from fabricating non-planar transistor structures to reducing interconnect RC delays.  3D interconnect and multi-chip bonding are facilitating form factors for use in phones, tablets and devices encompassing the internet of things.   In this “Age of Materials,” SMC will discuss market opportunities, scaling challenges, emerging solutions and more to meet the constantly growing demands.

Matt Nowak, senior director, Global Operations Group at Qualcomm, offers the conference’s keynote with insights on the emergence of the Digital Sixth Sense: Opportunities that will drive consumer demand over the coming decades, and the associated adoption of new IC devices and electronic materials. Tim G. Hendry, VP, Technology & Manufacturing Group at Intel, will kick off the session “Supply Chain Challenges, Interdependence for Future Growth” with his keynote, “Delivering Complexity to Beyond the Leading Edge.”

Other companies presenting include: Air Products & Chemicals, Air Liquide Electronics, Dow Chemical, Edwards Vacuum, Entegris, GLOBALFOUNDRIES, Hilltop Economics, IBM, Intel, Linx Consulting, Lux Research, Matheson, Pall Corp, SAFC Hitech, Sandisk, Stanford University, Stifel Nicolaus, TechSearch International, TriQuint Semiconductor, and VLSI Research.

For the “advanced materials”-enabled microelectronics industry, the Strategic Materials Conference is a planning, forecasting, and business development necessity. Organized by the Chemical and Gas Manufacturers Group (CGMG), a SEMI Special Interest Group comprised of leading manufacturers, producers, packagers and distributors of chemicals and gases used in the microelectronics industry, SMC has provided valuable information and networking opportunities to materials and electronics industry professionals since 1995.

For the complete agenda, additional information and to register, visit the Strategic Materials Conference webpage atwww.semi.org/smc.  For information on SEMI, visit www.semi.org.

Solid State Equipment LLC (SSEC), a provider of single-wafer wet processing systems for advanced packaging (including 2.5D and 3D ICs), MEMS, and compound semiconductor markets, was awarded a 2014 3D InCites Award in the category of 2.5D/3D Manufacturing Equipment. The 3D InCites Awards recognize achievements to further the commercialization of 2.5D and 3D IC technologies. SSEC received the award for the WaferEtch TSV Revealer tool, which is a single wafer wet processing platform for 3D IC and interposer wet etching applications designed to reduce process and capital equipment costs. The WaferEtch features superior uniformity of silicon thickness (as low as -/+ 0.7%) and high throughput. 

“Bringing 3D ICs to high-volume manufacturing is a requirement for the industry to move forward into the next technology node,” said Erwan Le Roy, Marketing Vice President at SSEC. “SSEC’s WaferEtch TSV Revealer helps to achieve this through integrating a low-cost wet etch process with metrology for performing thickness measurement. Our system replaces four tools with one (CMP, silicon thickness measurement, plasma etch, and clean), so we are able to achieve this at the lowest cost to the manufacturer.”

The 3D InCites Awards were established in 2013 to recognize achievements to further the commercialization of 2.5D and 3D IC technologies. The 2014 3D InCites Awards were presented at a breakfast ceremony hosted by Impress Labs on Thursday, July 10, 2014, at the Impress Lounge during SEMICON West. The event featured guest speaker Bryan Black, Senior Fellow, AMD, who has led AMD¹s die stacking program for the past seven years. Black talked about the future of die stacking and where the benefits lie within the context of mainstream computing CPUs, APUs, and GPUs.

This year’s event was co-promoted by 3D InCites, the premier online content source for reliable 3D technology information; SEMI, the global industry association serving the nano- and microelectronics manufacturing supply chains; and TechSearch International, the leading market research firm for advanced semiconductor packaging technology.

SSEC

To address the rising demands of imaging systems in mobile, medical, automotive and other technology applications, the Imaging Without Limits Conference (7-8 October) will be introduced at SEMICON Europa 2014 this year to address this surging market. Until recently, the imaging market was based primarily on mobile phone based applications. However, new technologies for imaging-based applications are now being introduced — including wearable electronics (e.g. smart watches), automotive, tablets, machine vision, security and surveillance, and medical applications. SEMICON Europa 2014, the region’s largest event for the microelectronics manufacturing and innovation supply chain, will be held 7-9 October 2014 in Grenoble.

Covering a broad range of imaging systems, the two-day “Imaging Without Limits” conference at SEMICON Europa 2014 will explore the promise of imaging-related systems, existing applications and new applications and technologies now on the horizon. Keynote speakers include Eric Fossum, Dartmouth University and the father of CIS, and Pascal Brosset, chief innovation officer of Schneider Electric. The first day will address applications (mobile, automotive, industrial, medical) and technologies (sensors, optics, processing and packaging) while the second day will delve into specific implementation techniques.

According to Yole Developpement, the CMOS Image Sensor (CIS) market is expected to grow at a 10 percent CAGR in revenue in the five-year period from 2013 to 2018, growing from US$ 7.8 billion in 2013 to $12.8 billion in 2018. While many applications drive the integration of CMOS image sensors, mobile phones accounted for approximately 66 percent of total shipments in 2013.  But other new applications — including tablets and automotive — are set to drive the future growth of this industry. Tablets also significantly contribute to the market growth with a 17 percent CAGR over 2013-2018.

The next wave of imaging will likely focus on automotive applications because additional image sensors are necessary for many of the safety improvements required by new government regulations.  CAGR for CIS automotive applications is expected to increase 36 percent between 2013 and 2018. Yole states that the market is “expected to reach about $700 million in 2018, and will drive the need for high-performance sensors: global shutter, high dynamic range, and high sensitivity. The requirements of the automotive market are hence completely different from the mobile phone market, which is still in the race for higher resolution and smaller pixels.”

In addition, Yole also sees several other applications with a high CAGR, including wearable devices (103 percent), machine vision (33 percent), and camera pills (32 percent).

Key companies involved in the imaging conference and exposition include: ARM, Asia Optical-EtherO, Audi, European Space Agency, French Institute of Vision, Hamamatsu, Heptagon, Microsoft, Schneider, Sofradir and STM.  Many research centers are also involved — CEA-LETI, CSEM, Fondazion Bruno Kezler, Fraunhofer Institut, Grenoble University Hospital, and more. Start-up and SMEs involved in the conference include: Aldebaran, Awaiba, CMOSIS, Caeleste, Mesa, Blue Eye Video, ISD, Kaleido, Multix, NikkoIA , NIT, Pyxalis, Yole, and Wavelens.

Imaging Without Limits is an exceptional opportunity for visitors to learn more about the imaging industry evolution and the business opportunities arising from this growing technology.

ANSYS, Inc., and Intel Corporation announced the availability of a production-proven reference flow for power, EM and reliability sign-off using ANSYS simulation solutions for Intel’s 14nm Tri-Gate process, showcasing it at last week’s Design Automation Conference. This technology allows customers of Intel Custom Foundry to design the next-generation mobile and cloud enterprise products that deliver the highest performance while meeting stringent product power targets.

ANSYS and Intel Custom Foundry teams developed reference flows around ANSYS RedHawk for system on chip power and electromigration (EM) sign-off, ANSYS Totem for custom intellectual property power and EM integrity and ANSYS PathFinder for full-chip ESD validation. This collaboration extends the work on the Intel Custom Foundry 22nm process design platform to the 14nm platform.

Intel’s 14nm process technology is the world’s most advanced process technology and is the second generation of Tri-Gate process technology. These Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing an unprecedented combination of improved performance and energy efficiency compared to previous state-of-the-art transistors. The capabilities give chip designers the flexibility to choose transistors targeted for low power or high performance, depending on the application. Collaboration with ANSYS on the Intel Custom Foundry 14nm and 22nm design platforms allows designers to take advantage of Intel’s process technologies.

“As designers continue to push the technology envelope, having access to a robust and foundry-certified power EM and reliability sign-off flow becomes critical,” said Aveek Sarkar, vice president of product engineering and support at Apache Design, a subsidiary of ANSYS. “Our long-standing relationship with Intel Custom Foundry has allowed us to provide optimized tools and methodologies for customers to adopt the latest technologies with greater confidence.”

“A close collaboration between Intel Custom Foundry and ANSYS on reliability verification reference flow for 22nm and 14nm enables our customers to efficiently deliver more robust and reliable designs for next-generation electronic products,” said Venkat Immaneni, senior director, Foundry Design Kit Enablement, Intel Custom Foundry. “This platform enables our customers to use an industry-leading power, EM and reliability sign-off solution on our design platforms.”

By Dr. Lianfeng Yang, Vice President of Marketing, ProPlus Design Solutions, Inc.

Embedded memory is now consuming most of the area on an SoC chip. Complexity and circuit size are only growing, which means smaller process geometries, larger designs, and tighter design margins. This also translates to the need for larger post-layout and more highly accurate simulation. With memory designers’ growing concern about increasing circuit sizes, giga-scale SPICE simulation is the term to describe the emerging trend in large-scale circuit designs. This is due, in large measure, to FastSPICE’s inability to meet the simulation accuracy challenge. Likewise, traditional SPICE simulators are limited by their capacities.

The semiconductor industry is calling for high-capacity, high-performance parallel SPICE simulators to support giga-scale circuit simulation primarily for memory applications and leading-edge technologies including 16/14nm FinFET. Recently emerging giga-scale SPICE simulators would meet the need and could enable the simulation of complex designs using pure SPICE engine –– say, more than one-billion element memory blocks or full chip circuits –– with no loss of accuracy. And, deliver competitive simulation performance as a FastSPICE simulator.

Memory designers, more typically, have had to make trade-offs between accuracy and performance/capacity with FastSPICE simulators for large scale memory simulation and verification. FastSPICE simulators may offer speed/capacity while sacrificing accuracy, while new giga-scale SPICE simulators are able to combine pure SPICE accuracy with FastSPICE capacity and performance, readily handling design sizes.

Let’s look at several successes. One giga-scale SPICE simulator was used recently for a 495-million element post-layout SRAM simulation to verify full-chip leakage power. It took 11.37 hours to finish the entire simulation on a 24-core computer server, consuming 69.1 GB of memory. Meanwhile, an aggressive FastSPICE run took 15.3 hours to finish the same simulation with inaccurate results, while a conservative simulation with FastSPICE took 35.5 hours and 173  GB of memory to achieve reasonable verification results. Obviously, the giga-scale SPICE simulator beats FastSPICE on simulation accuracy, and delivers reliable results with no need to experiment with complicated partitioning and other FastSPICE options. Moreover, it can also provide competitive or better performance and less memory consumption than FastSPICE simulators. It’s a natural choice for memory designers when accuracy is a concern in memory characterization and verification.

In another example of the superior capabilities of a giga-scale SPICE simulator, it was able to simulate a full-chip SRAM circuit with 109-million elements within 6.54 hours on a 32-core computer server, consuming 44.6 GB of memory.  Ready for one more examples? The giga-scale SPICE simulator was able to finish simulating a 576-million element DRAM within eight hours, consuming only 14.8 GB of memory.

Other commercially available parallel SPICE simulators were unable to handle any of these sample cases.

Now, readers may be wondering what new giga-scale SPICE simulator is able to accomplish this rate of success. I’m pleased to report that it’s ProPlus’ newly announced NanoSpice Giga that offers accuracy, performance and capacity. As a pure SPICE simulator, it is able to accurately solve full matrix and analytical device model calculations without approximations, and has full SPICE analysis features. It supports industry-standard inputs and outputs. With its newly designed database for efficient memory handling and innovative matrix solver technology, NanoSpice Giga is the only SPICE simulator that can handle one-billion+ element memory circuits with superior performance.

NanoSpice Giga was created primarily for large-scale memory circuit simulations, including the characterization of large embedded SRAM blocks, simulation and verification of memory integrated circuits (ICs) such as SRAM, DRAM and flash memory, typically the domain of FastSPICE simulators. With shrinking technology, supply voltage reductions and the impact of increasing process variations, memory circuit simulation requires better accuracy, often a limitation of FastSPICE simulators.

The news release with more information can be found at: http://tiny.cc/udjkfx.

ProPlus will exhibit at the 51st Design Automation Conference (DAC) in Booth #905, demonstrating the latest DFY solutions for giga-scale SPICE simulations and nano-scale SPICE modeling. Interested readers may reserve a time for meeting by sending email to [email protected]. DAC will be held Monday, June 2, through Wednesday, June 4, from 9 a.m. until 6 p.m. at the Moscone Center in San Francisco. Information about DAC can be found at www.dac.com.

Read more for ProPlus Design Solutions Blog:

DAC panels tackle giga-scale SPICE simulation

Long live FinFET

SPICEing up circuit design