Category Archives: Packaging and Testing

NXP Semiconductors N.V. (NASDAQ:NXPI) announced a $22 million dollar program that expands its operations in the United States, enabling the Company’s US facilities to manufacture security chips for government applications that can support critical US national and homeland security programs. Upon completion of the expansion project, NXP facilities in Austin and Chandler will be certified to manufacture finished products that exceed the highest domestic and international security and quality standards.

“This initiative advances NXP’s long-term commitment to developing secure ID solutions for federal, state and local government programs in the United States and demonstrates our deep dedication to serving the American market,” said Ruediger Stroh, Executive Vice President of Security and Connectivity at NXP. “The expansion program further positions NXP to deliver solutions for the IoT, connected devices and many other fast-growing applications in the United States as we continue to be a major contributor to the country’s global leadership in the semiconductor industry.”

As the market leader in secure identification solutions, NXP’s proven technology is included in core components that power secure government-issued ID documents in more than 120 countries, and is used by 95 countries worldwide to secure electronic passport programs.

Steve Adler, the Mayor of Austin, said, “We are excited to see NXP investing in Austin and in the cyber security of our country. We trust this initiative will also secure thousands of jobs and further foster the growth of Austin as a major technology hub.”

NXP R&D manufacturing facilities in San Jose, Austin and Chandler have also undergone a thorough security cite certification process to produce Common Criteria EAL6+ SmartMX microcontroller family products. Common Criteria is an international set of guidelines and specifications developed for evaluating information security products to ensure they meet a rigorous security standard for government deployments.

Three leading U.S. universities are the latest recipients of funding from the Nano-Bio Manufacturing Consortium (NBMC), operated by SEMI.  NBMC’s mission is to further the development of human performance monitoring (HPM), thereby broadening the use of advanced electronics in this highly anticipated application space. Among other applications, HPMs are expanding the fast growing wearable electronics markets. According to Research and Markets, “The global market for wearable electronic devices was valued at around USD $20 billion in 2016 and is expected to reach USD $97.8 billion, growing at a CAGR of around 24.1 percent from 2017 to 2023.”

The new awards announced today total more than $870,000 and include:

  • University of Arizona: To meet the needs of NBMC industry members, the University of Arizona will focus on determining which HPM sweat patch configuration is best suited to meeting performance requirements. The initial investigation will include a “lab-in-a-bandage” that collects and analyzes biomarkers within one minute from sweat secretion.  The follow-on project will determine the feasibility of using organic semiconductor sensor technology (compatible with flexible substrates and manufacturing techniques) for sweat biomarker detection sensitivity and selectivity with sweat sample volumes in the nano- and pico-liter range.
  • University of California at Los Angeles: UCLA will partner with i3 Electronics of Binghamton, NY to investigate the use of Fan-Out Wafer Level Packaging (FOWLP) methods as a new way to build versatile, biocompatible physically-flexible heterogeneous electronic systems. FOWLP is a relatively new packaging process that gaining widespread use in portable devices such as smart phones. It offers the advantages of true heterogeneous integration of different dies, including high performance electronics, tight pitch interconnects, and components (such as low profile passives) with a short turn-around, scalable, manufacturing process.
  • University of Massachusetts at Amherst: U Mass Amherst will conduct a detailed systematic assessment of microfluidic subsystem architecture and operational approaches for sweat-based biomarker detection.  The study will address issues associated with accurate, time-stamped sweat sample collection and delivery, effluent control and removal for continuous operation, and dynamic performance design aspects to address sample handling under conditions of high and low sweat rates.

“The NBMC program continues to push technology limits in ways that integrate leading edge microelectronics,” said Dr. Melissa Grupen-Shemansky, SEMI’s CTO for flexible electronics and advanced packaging.  “Consequently, SEMI is helping to identify new equipment, materials and process opportunities for our members and their customers.”

The NBMC program is funded through a cooperative agreement with the Air Force Research Laboratory in Dayton, Ohio.

For an increasing number of designs, companies are finding it beneficial to design their own ASICs with system-on-a- chip (SoC) complexity. For reasons of cost reduction, quality improvement, IP protection and security, a full turn-key ASIC can be achieved for $1-5 million, particularly if the design can be built using mature technology nodes.

To further explore this topic, we asked questions from three leading experts in the field. Participating in the Q&A are:

• Michel Villemain, CEO, Presto Engineering, Inc.
• Guillaume Etorre, VP Engineering, Devialet
• Venkata Simhadri, CEO, Gigacom Semiconductor

Q: What is the decision-making process for deter- mining which applications are best addressed with an ASIC vs standard, off-the-shelf components? How does one calculate non-recurring engineering (NRE) costs, for example, and how does the anticipated part volume impact the decision?

Etorre: In many cases, particularly for IoT or other space-constrained designs, going with multiple standard compo- nents is simply not an option. A single chip must embed the microcon- trollers, sensors, battery management system, radios, etc. required by the application, in the smallest possible form factor.

When space is available, a standard component approach can be more appropriate to meet tight deadlines or to address situations where demand for the product is unproven. It can also serve as a stop-gap to serve the market immediately while a lower-cost ASIC solution is being designed.

If demand for the product is proven, a net present value calculation over a range of scenarios (best, typ., worst case for volumes and schedule for instance) will provide guidance on the best approach. An ASIC typically carries higher NRE (design, tapeout, qualification, test) but yields lower unit cost than an off-the-shelf solution. Depending on anticipated volumes and cost of capital, the lower unit cost of an ASIC will outweigh the higher NRE.

Simhadri: Primarily two factors can impact a company’s decision to design its own ASIC.
1. Competitive advantage – If the company is building its system using off-the- shelf components, competition can quickly reproduce it and you are only left with software as the differentiating factor. In this situation, you must have your own ASIC to protect your IP.
2. Cost – When addressing large volume markets the unit cost becomes an important factor and the only way to cut down the cost is to integrate/optimize the off-the-shelf components.

The typical NRE cost includes the cost of design, proto- typing (shuttle) and qualifying the part. Companies typically use a few benchmarks to justify the upfront cost.

For example, NRE cost is primarily dependent on the infrastructure (staff and tools) the customer already has in place. If the company already has a design team, EDA tools, etc. then the incremental cost might not be too high. However, without a design infrastructure already in place, it’s going to be a lot more time- consuming and costly. In this case, it is much easier to work with an ASIC design house to have all the infra- structure and some of the building blocks put in place.

Villemain: NRE is somewhat challenging to calculate since the duration of the project is often underestimated and unpredicted issues (who really does anticipate them!) bring additional cost to such a project. One way of mitigating this is to use external sources provided on (primarily) fixed- cost engagements. Beside ROI on NRE (function of margins and volume, indeed), drivers for using ASICs include: form factor, reliability, IP, power consumption and security.

Q: What are the tools and supply chain partners needed to successfully design an ASIC solution, including EDA software, foundry, packaging and test house?

Simhadri: You need the standard EDA tools for both Analog/ Digital, if you are designing a mixed-signal chip. Typically, you will have to work with at least two EDA vendors, such as Synopsys, Cadence, or Mentor Graphics. Many of the foundries will also work with small companies, provided you show a path to volume. However, in terms of design support (pdks, libraries, etc) foundries with better design infrastructure can save significant time. If you are a start-up or doing it for the first time, it can be quite daunting to setup the relationships and you can lose quite a bit of time to get the process going. But there are ways to save time and cost by outsourcing some of the work to the right design companies and echo system partners.

Villemain: Success is a function of a combination of multiple competencies that need to work coher- ently throughout the life of the product, especially post-design: industrialization, supplier management, quality, planning, logistics and product sustaining. This typically represents more than ten different skillsets that need to be part of the extended product team.

Etorre:
• Availability of proven IP (CPU, peripherals, interconnects, digital & analog I/O,…) for the chosen technology node.
• Affordable EDA software, with specific packages for companies designing only one or two chips at any given time, for specific end-user products vs. fabless IC companies which can spread the EDA license cost over many different chip designs every year.
• Efficient turn-key supply chain partner that can abstract out the complexity of foundry, packaging, test, storage and logistics for companies that lack critical mass.

Q: With the rise of IoT, IIoT and wearables, there’s much interest in analog/mixed-signal ASICs. How are their requirements different from traditional digital designs?

Villemain: Analog/RF designs tend to be smaller in size and to require less aggressive wafer fab processes. From a design standpoint, they demand less expensive EDA tools and less costly verification. However, their characterization and test is typically more complex and requires more expertise than a purely digital equivalent. Finally, yield management can be more demanding as the equation design window vs. process window is left more to the engineers than digital products, which can use semi-automated tools.

Simhadri: The primary difference in the require- ments is power and connectivity. If the ASICs must be connected to the internet, determining which protocols you need to incorporate on to the chip makes a big difference. Power is going to be a huge differentiating factor for the wearables, and designers are looking at various power saving techniques in an effort to optimize the power. Also, the foundries are offering special process nodes like SOI to address these markets.

In addition to the standard low power techniques like voltage islands and power shut off modes, the ASIC can further optimize the power by custom- izing the IP blocks for the specific applications. For, example, serial interfaces that burn lot of power, can be optimized.

Etorre:
• Design cycle is longer for analog IP than for digital.
• It is therefore critical to choose a foundry and a node for which all or most of the required IP are available.
•Analog IP is typically not portable between foundries or between nodes without significant rework.• •Custom analog IP is therefore a significant investment that will be depreciated if a foundry change or node change is required.
• The best nodes for analog, MEMS, RF, high- voltage and digital are usually not the same.
• Selecting the most appropriate node for the applications is not a trivial task.
• Introducing new functionality in a subse- quent version of an ASIC can require a node change and therefore major redesign of analog / mixed signal circuits. Anticipating future requirements can help make better technology choices.

Q: How do mask set costs of more mature technologies (180-40nm node) compare with those of 28nm and below, and how do mask costs enter into the overall cost equation?

Simhadri: I strongly advise our customers to use shuttles to prototype the ASIC and completely qualify it before spending a huge amount on the full mask. As expected, the 180-40nm shuttle costs are signifi- cantly lower than 28/16nm.

Villemain: With verification being less of a factor for analog/RF designs, mask sets can become a significant part of NRE below 90nm. Process technology is obviously a leading factor, but in addition, process routes can be costly because of additional options or IP, implying the addition of a mask/process layer, and thus, decreasing ROI in smaller geometries. Also, cost plateaus do exist (depending on the foundries) due to equipment transition (wafer size, lithography technol- ogies, etc.)

Etorre: The mask cost ratio between older technol- ogies and more recent ones can reach 20:1. For a 180nm design, once design, qualification and test fixtures are factored in, mask cost is not a significant contributor to the overall NRE.

Q: Out of the various advantages of ASIC design — cost reduction, quality improvement, IP protection and security – how would you rank their importance. Are there other advantages to ASIC solutions?

Villemain: What we see in the industry is a combi- nation of those factors (cost reduction, quality to architect an ASIC that replaces the discrete compo- nents in the system, which can reduce the BOM improvement, IP protection and security) as a function of the market our customers are operating in. The most common drive is, of course, that of cost (ASICs usually bring a dramatic product cost reduction), although for infrastructure applications, reliability is a key criterion, while for battery-operated applica- tions, power consumption reduction is mandatory— and all are benefits of using an ASIC.

In addition, more and more IoT segments require security in order to be even just a contender in the market, and an ASIC-based solution offers both a certifiable source of design and a cost benefit as compared to standalone secured elements.

Finally, in very competitive markets, the IP differen- tiation that an ASIC provides is a huge benefit.

Simhadri: IP protection and security shall rank first, followed by cost reduction. In some cases, off-the-shelf chips may not meet the performance requirements.

Etorre:
1. Real estate savings – an ASIC-based design is much smaller than an off-the-shelf approach;
2. Cost reduction
3. IP protection
4. Quality improvement, if any – combining various
functions and technologies (analog, digital, RF, power, MEMS, etc.) on the same die can lead to lesser quality.

Q: How has your company benefitted from an ASIC approach?

Etorre: Devialet’s Analog-Digital Hybrid (ADH) audio amplification technology was first implemented with discrete components. This discrete design is used in our high-end Expert Pro amplifiers and it supports the widest range of operating conditions.

In our Phantom speakers, we had to fit the same technology is a much smaller area. We specialized the analog circuit for the specific speaker drivers used in the Phantom and we designed an ASIC to deal with the analog part of the ADH technology.

Simhadri: Gigacom has been working with a company in the industrial IoT space and building systems for sensing gases and air quality. We have worked together by 10x and reduce the area and power significantly at the same time.

Q: How has the supply chain evolved to meet this new kind of demand?

Villemain: The supply chain needs to evolve in order to focus more on the backend than the frontend. If SoC brought RFCMOS to mass adoption with connected product, IoT, relying on a sensor-specific package, must integrate a companion ASIC driver and a transceiver; System in Package back-end technologies are gaining tremendous momentum. More and more companies will design their own ASICs, on well-proven, stable fab processes. However, packaging, reliability, test and security will become prime drivers, defining not only product costs, but also the ability to ramp, yield and scale up in volume. Supply chains (and especially the management of supply chains) is evolving accordingly.

For example, until recently, building an ASIC for an IoT device required the assembly of a team of experts, each with expertise in a different part of the process. The design might be created in-house or through an outside firm, and large companies, like automotive manufacturers, might assemble whole organizations, often called “operations” departments, with the sole task of managing the production of the specialized devices they needed. For a small company, with a game-changing new product idea, the cost and delay of assembling such a team can be fatal. If a competitor beats you to market you might not get a second chance. This need for manufacturing expertise led to the creation of “outsourced operations” companies, like Presto Engineering, that can manage the entire semiconductor manufacturing process from the completion of the design to the delivery of the tested product. By reducing the risk, cost, and difficulty of the production process, companies, such as Presto, are playing a key role in accelerating the proliferation of application specific semiconductor solutions.

Etorre: By design, ASICs run in lower volumes that standard parts. The supply chain must adapt to deal with more customers running lower volumes. This creates an opportunity for companies providing turn-key supply chain services to bridge the gap between numerous mid-volume customers and tradi- tional foundries and packaging houses who only address the largest fabless IC vendors.

Simhadri: The supply chain needs some improve- ments in the following areas. The older process nodes from 180nm to 40nm have suddenly become popular for IoT applications. However, most of the PDKs and other collateral were developed for older EDA tool versions and they need to be updated. Also, most of the IP vendors are targeting their resources for developing the IP for the latest process nodes where they get the best returns on their investment. Some of this IP has to be ported back to enable the ASICs in older nodes.

Also, to bring up these ASICs, the industry needs good support for packaging and testing facilities and all the top vendors are focused on high volume and leading- edge ASICs. Companies like Presto can potentially fill the needs.

Boston Semi Equipment (BSE), a global semiconductor test handler company, announced today it has received a follow on order for multiple Zeus gravity test handling systems for pressure MEMS. The order comes from a major manufacturer of tire pressure monitoring system sensors, which selected Zeus’ pressure MEMS solution for its high accuracy and throughput.

“The Zeus handler applies the pressure stimulus directly to the device while it is at the handler’s test site,” said Kevin Brennan, vice president of marketing for BSE. “This eliminates the need to hand off the package to a separate pressure unit for testing. The tool also reaches desired pressure set points faster, cycles through pressure levels in shorter times and offers a faster index time than other solutions. Combined, these advantages result in higher throughput for pressure MEMS devices, making Zeus an ideal solution.”

The Zeus is a tri-temperature handler that can be configured with up to eight test sites. Cold temperature testing is achieved using LN2 or a BSE-designed, two-stage chiller, the MR2. The Zeus offers the features and performance needed by today’s test cells at a more affordable price point.

CMOS image sensor sales are on pace to reach a seventh straight record high this year and nothing ahead should stop this semiconductor product category from breaking more annual records through 2021 (Figure 1), according to IC Insights’ 2017 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.

After rising 9% in 2017 to about $11.5 billion, worldwide CMOS image sensors sales are expected to increase by a compound annual growth rate (CAGR) of 8.7% to $15.9 billion in 2021 from the current record high of $10.5 billion set in 2016, based on the five-year forecast in the 360-page O-S-D Report, which covers more than 40 different product categories across optoelectronics, sensors and actuators, and discrete semiconductors.

Figure 1

Figure 1

After strong growth from the first wave of digital cameras and camera-equipped cellphones, image sensor sales leveled off in the second half of the last decade.  However, another round of strong growth has begun in CMOS image sensors for new embedded cameras and digital imaging applications in automotive, medical, machine vision, security, wearable systems, virtual and augmented reality applications, and user-recognition interfaces.

Competition among CMOS image sensor suppliers is heating up for new three-dimensional sensing capability using time-of-flight (ToF) technology and other techniques for 3D imaging and distance measurements.  ToF determines and senses the distance of faces, hand gestures, and other things by measuring the time it takes for light to bounce back to sensors from emitted light (often an infrared laser or LED).  CMOS technology has progressed to the point of supporting integration of ToF functions into small chip modules and potentially down to a single die.  Sony, Samsung, OmniVision, ON Semiconductor, STMicroelectronics, and others have rolled out and developed 3D image sensors. Infineon has also jumped into the image sensor arena with a 3D offering that is built in ToF-optimized CMOS technology.

Automotive systems are forecast to be the fastest growing application for CMOS image sensors, rising by a CAGR of 48% to $2.3 billion in 2021 or 14% of the market’s total sales that year, says the 2017 O-S-D Report.  CMOS image sensor sales for cameras in cellphones are forecast to grow by a CAGR of just 2% to $7.6 billion in 2021, or about 47% of the market total versus 67% in 2016 ($7.0 billion).  Smartphone applications are getting a lift from dual-camera systems that enable a new depth-of-field effect (known as “bokeh”), which focuses on close-in subjects while blurring backgrounds—similar to the capabilities of high-quality single-lens reflex cameras.

Industry experts answer questions about the new standard in a virtual roundtable.

In recent years, energy consumption has decreased due to several innovations that have helped to improve the energy efficiency of process tools and sub-fab equipment, but an increase in the number of processes and the growing complexity of processing at the current node has resulted in a spike in energy consumption in the fab. Approximately 43% of the energy consumed in the fab is due to the processing equipment and, of this, 20% is vacuum and abatement (8% overall).

A new standard from SEMI, E175, defines energy saving modes, which combined with the EtherCAT signaling standard, can help fabs save energy and other gas/utility costs when the tool is not processing and with no impact on subsequent wafer processing.

EtherCAT, based on industrial Ethernet, provides high- speed control and monitoring. It is the communication standard of choice for the latest semiconductor tool controllers to connect to sensors and actuators around the tool, including vacuum and abatement systems.

SEMI E175 defines how process tools communicate with sub-fab equipment, such as vacuum pumps and gas abatement systems, to reduce utility consumption at times when wafers are not being processed by the tool, and returning to full performance when the tool is again required to process wafers. It builds on SEMI E167, which defines communication between the fab host/ WIP controller and the process tools for the purpose of utility saving.

Collaboration between the E175 and EtherCAT groups has seen a harmonization of the communication standards to provide co-ordinated energy saving across devices in the fab.
We invited experts in this area to answer a few questions in a virtual roundtable. The participants are:

• GERALD SHELLEY, Senior Product Manager Communication and Control at Edwards, and the EtherCAT Chair Abatement / Roughing pump working groups, E175 task force.

• MIKE CZERNIAK, Environmental Solutions Business Development Manager at Edwardsm Co-Chair of SEMI International Standards E167 & E175, and campaigner for energy saving

• GINO CRISPIERI, Applied Materials – Past Co-chair of E175 (originally SEMATECH/ISMI, then independent consultant, prior to Applied Materials)

• MARTIN ROSTAN, Executive Director, EtherCAT Technology Group

Q: Please explain what drove the standards work on energy saving and the achievements to date.

SHELLEY: There is increased pressure on the industry to reduce energy and utility saving from both a cost and environmental standpoint. Subfab equipment is a major consumer of utilities, which is wasted when a tool is not in use. Different manufacturers have implemented energy saving solutions, with minimal direct connection to the tool. However, direct tool connection has emerged as the best way to maximize saving without any risk to wafer processing.

CZERNIAK: This work originated in the ISMI part of SEMATECH as a follow-on to generic work aimed at reducing the overall utilities footprint of modern fabs. In response to this and requests from customers, Edwards developed vacuum pumps and gas abatement systems that had energy-saving functionality. However, it soon became clear that the limitation to implementing such savings was the absence of standardised signalling between the process tool and sub-fab equipment.

CRISPIERI: A SEMATECH project around 2009 started to look into opportunities for saving energy in the semiconductor factories. At that time, suppliers of pumps and abatement systems already had started initiatives to provide their own solutions to the initiative. Since that time, the industry has adopted two new standards: SEMI E167 Specification for Equipment Energy Saving Mode Communication (between factory and semicon- ductor equipment) and SEMI E175 Specification for Subsystem Energy Saving Mode Communication (between semiconductor equipment and subsystems).

Q: Please describe how the energy saving task force was born and why you decided to get involved.

CRISPIERI: Back in 2009 while working for SEMATECH in Austin, Texas, prior to SEMATECH’s move the New York, Thomas Huang an assignee for GlobalFoundries to the EHS Program approached and asked me if I would be interested in helping him drive a standard for equipment suppliers to enable their equipment to save energy during idle times. Because of my previous experience working with equipment suppliers and developing standards for equipment and factory communication, I accepted to chair a task force to drive the equipment supplier’s new capability requirement into a standard. At first, we thought it would be an easy task and that everyone would jump to help create and approve the standard in a short amount of time because of its benefits. A two phase approach was defined to drive the standardization process and engage semiconductor and sub-fab equipment suppliers accordingly. It took almost three years to complete the Phase I (2013) and another three to complete the Phase II (2016) standards.

SHELLEY: The task force was an extension of E167 which previously defined the communication into the tool from the supervisory systems, however to achieve maximum benefit signalling to tool subsystems was key and the E175 task force was the result.

CZERNIAK: Following-on from the above, the ISMI working group became a SEMI Standards Task Force and began work at developing a standard, initially for Host to process tool (E167) and then from tool to sub-fab (E175), which I was co-chair for to ensure continuity and clear the signalling “roadblock”.

Q: How have suppliers collaborated on E175?

CRISPIERI: Compared with the suppliers who partic- ipated in SEMI E167 development, the suppliers involved in the development and approval of SEMI E175 were more committed to make it happen and helped drive the standardization process to conclusion much more efficiently. Edwards, AMAT, TEL, Hitachi- Kokusai and DAS-Europe regularly participated and provided inputs to standardize behavior and require- ments for their own equipment. We run into some difficulty getting aligned with other standard activities that were driven by SEMI’s EHS Committee because their changes affected our standardization process. I must note that the overall participation was excellent in particular from Edwards Vacuum and AMAT.

ROSTAN: Within the ETG Semiconductor Technical Working Group individual task groups already had multiple suppliers collaborating on the detail of the EtherCAT profiles for all devices, with technical support from the EtherCAT Technical Group. We were fortunate to have a delegate from Edwards in both the Semi E175 Task Force and key EtherCAT Task Groups to informally broker agreement between the teams.

SHELLEY: The suppliers were able to use their collective experience to work through a number of options to find the optimum way of controlling subfab equipment, tackling variability in wakeup time and control architec- tures between device types and equipment technology.

CZERNIAK: Suppliers, automation providers, tool OEMs and end-users have all collaborated to help develop a standard that works for everyone and aligns with earlier standards like S23.

Q: How was the EtherCAT collaboration beneficial to E175?

SHELLEY: By sharing information and understanding in real time we demonstrated the E175 concept is achievable using the favored protocol for new tool platforms and defined how it would be implemented. We co-operated to take both these standards to alignment in one simul- taneous step, saving considerable committee time on both sides that would have been necessary to resolve any divergence of the detail.

ROSTAN: By devising the implementation of E175 in parallel the EtherCAT Task Groups involved were able to feedback detailed technical proposals and show the E175 standard could be implemented relatively easily within the existing EtherCAT standards.

CRISPIERI: Participation and collaboration from the EtherCAT Working Group was critical to accelerate the implementation and adoption of the standard. Dry Contacts and EtherCAT communication protocol messages were added to two Related Information sections and included in the SEMI E175 standard at the time of its publication.

CZERNIAK: This enables a “richer” signalling environment than simple dry contacts (which are also supported) that enables even greater utility savings to be made.

Q: How has EtherCAT been able to support the require- ments of the tool and Semi E175?

CZERNIACK: By providing timing information; the longer the time the tool is inactive, the greater the savings possible.

ROSTAN: As the control network of choice for the latest semiconductor tools, EtherCAT has been ideally placed to support enhancements, such as the energy saving connectivity increasingly being requested by the fabs. In particular, it was good to see the Pump and Abatement Task Groups of the existing Semiconductor Technical Working Group formulate an E175 compliant solution within the timescales of the second release of the EtherCAT semiconductor device profiles. The EtherCAT Technology Group was also more than happy to support the publication of extracts of the EtherCAT standards being used as protocol examples in the Imple- mentation guidelines of the Semi E175 document.

SHELLEY: EtherCAT has the fast / deterministic connec- tivity and proven integration with tool controllers that allows E175 functionality to be easily added without any loss of performance. By including the requirements of Semi E175 in the EtherCAT standards, both equipment suppliers and tool vendors can establish energy saving communication quickly and easily.

CRISPIERI: The coordination between EtherCAT Working Group and the SEMI ESEC task force group was conducted by Mr. Gerald Shelley from Edwards Vacuum. With his help and leadership, we reached effortlessly agreement and acceptance for the required messages, parameters and values into the EtherCAT respective Pump and Abatement Profile documents. Havingworking usage scenarios and support from the EtherCAT Working Group has been invaluable.

Q: Why is energy saving important to the industry?

ROSTAN: In the industrial world, EtherCAT users are increasingly using our communication and control technologies to drive down energy consumption. The semiconductor industry operates in parts of the world where energy is a limited and expensive resource, whilst the latest wafer processing requires more power. The manufacturers are therefore in great need for energy saving opportunities, such as when the tool subsystems are not in use.

SHELLEY: The fabs are being squeezed by an increase in the complexity and number of processes involved in manufacturing a wafer, driving consumption up and increasing scarcity of energy supply. This is further compli- cated with associated cost and government pressure to “keep the lights on”.

CRISPIERI: It is not hard to see why is so important for device makers or the semiconductor manufacturing industry to adopt and require energy conservation capabilities in their factories. Energy consumed by many equipment components and support systems, such as pumps and abatement systems, never stop from running even when the equipment is idle and waiting for product to be delivered for processing. These components and support systems can save millions of dollars each year if their power consumption is reduced. This energy consumption reduction extends their life cycle thus reducing costs of maintenance and parts replacement. Any effort to reduce energy consumption helps lower costs and adds gains to not only the manufacturer but to those who have to generate the energy for consumption.

CZERNIACK: Cost reduction is always important, but electrical supply is limited in some areas.

MEMS & Sensors Industry Group (MSIG), the industry association advancing MEMS and sensors across global markets, today announced its line-up of speakers for its TechXPOT program, What’s Next for MEMS & Sensors: Big Growth of Disruptive Applications for Smart Sensing Changes the Business, on July 11 during SEMICON West 2017. Speakers from industry and academia will explore the disruptive influence of MEMS and sensors on applications that span human-machine interfaces, disposable wireless electronics, and wireless sensor nodes for smart cities. They will also discuss advancements in piezoelectric materials for emerging applications as well as MEMS foundry process technologies that speed time to market.

“From smart autos and smart manufacturing to smart cities and smart health monitoring, emerging markets for MEMS and sensors are creating greater demand for integrated intelligence,” said Karen Lightman, vice president, MEMS & Sensors Industry Group, SEMI. “MSIG speakers at SEMICON West will help MEMS and sensors suppliers to more ably respond to this demand, as they learn how to add value through technological innovation and integration.”

Topics and presenters at the MEMS program at the SEMICON West TechXPOT on July 11 include:

  • What’s Next for the MEMS Industry? ─ Jean-Christophe Eloy, CEO and founder, Yole Développement
  • New MEMS Opportunities from Piezoelectric Technology ─ David Horsley, professor, Mechanical & Aerospace Engineering, University of California Davis
  • Smart IT Systems and Development Protocols Enable Faster Time-to-Market in MEMS ─ Tomas Bauer, senior VP, sales/business development, Silex Microsystems
  • Waggle and the Future of Edge Computing and Smart Cities ─ Pete Beckman, co-director, Northwestern-Argonne Institute for Science and Engineering
  • Roll-up Implementation of Gesture Sensing and Voice Isolation Sensing Wall for Future Human-Machine Interface ─ James Sturm, professor, Electrical Engineering, Princeton University
  • Three Bit NFC Sensor Labels Based on a Flexible, Hybrid Printed CMOS TFT Process ─ Arvind Kamath, VP of Engineering, Thin Film Electronics

Register now for MSIG’s session at SEMICON West or contact MSIG at [email protected] for more information.

Standards and Task Force Meetings at SEMICON West

MSIG also invites members to attend the MEMS/NEMS Committee Meeting, including a Task Force on microfluidics, from 3:30-5:30 pm on July 13 at the San Francisco Marriott Marquis. Visit: www.semiconwest.org/standards

With the increasing sophistication of future vehicles, new and more advanced semiconductor technologies will be used and vehicles will become technology centers.

BY DR. JEAN-CHARLES CIGAL and GREG SHUTTLEWORTH, Linde Electronics, Taipei, Taiwan

Large efforts are being deployed in the car industry to transform the driving experience. Electrical vehicles are in vogue and governments are encouraging this market with tax incentives. Cars are becoming smarter, capable of self-diagnostics, and in the near future will be able to connect with each other. Most importantly, the implementation of safety features has greatly reduced the number of accidents and fatal- ities on the roads in the last few decades. Thanks to extensive computing power, vehicles are now nearing autonomous driving capability. This is only possible with a dramatic increase in the amount of electronic devices in new vehicles.

Recent announcements regarding acquisitions of automotive electronics specialists by semiconductor giants and strategic plans from foundries highlight the appetite from a larger spectrum of semiconductor manufacturers for this particular market. Automotive electronics has become a major player in an industrial transformation.

Automotive electronics is, however, very different from the consumer electronics market. The foremost focus is on product quality, and the highest standards are used to ensure the reliability of electronics components in vehicles. This has also an impact on the quality and supply chain of materials such as gases and chemicals used in the manufacturing of these electronics devices.

Automotive electronics market: size and trends

When you include integrated circuits, optoelectronics, sensors, and discrete devices, the automotive electronics market reached around USD 34 billion in 2016 (FIGURE 1). While this represents less than 10% of the total semiconductor market, it is predicted to be one of the fastest growing markets over the next 5 years.

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There are several explanations for such growth potential:

• The vehicle market itself is predicted to steadily grow on an average 3% in the coming 10 years and will be especially driven by China and India, although other developed countries will still experience an increase in sales.
• The semiconductor content in each car is steadily increasing and it is expected that the share of electronic systems in the vehicle cost could reach 50% of the total car cost by 2030 (FIGURE 2).

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While it is clearly challenging to describe what the driving experience will be in 10 to 15 years, some clear trends can be identified:

• Safety: The implementation of integrated vision systems, in connection with dozens of sensors and radars, will allow thorough diagnoses of surrounding areas of the vehicles. Cars will progressively be able to offer, and even take decisions, to prevent accidents.
• Fuel efficiency: The share of vehicles equipped with (hybrid) electrical engines is expected to steadily grow. For such engines, the electronics content is estimated to double in value compared to that of standard combustion engines.
• Comfort and infotainment: Vehicle drivers are constantly demanding a more enhanced driving experience. The digitalization of dashboards, the sound and video capabilities, and the customization of the driving and passenger environment should heighten the pleasure of time spent in the vehicle.

In order to coordinate all these functions, communication systems (within the vehicle, between vehicles, and between vehicles and infrastructures) are critical and large computing systems will be necessary to treat large amount of data.

Quality really makes automotive electronics different

Automotive electronics cannot be defined by specific technologies or applications. They are currently characterized by a very large portfolio of products based on mature technologies, spanning from discrete, optoelectronics, MEMS and sensors, to integrated circuits and memories.

Until now, the automotive electronics market has been the preserve of specialized semiconductor manufacturers with long experience in this field. The reason for this is the specific know-how required for quality management.

A component failure that appears harmless in a consumer product could have major safety consequences for a vehicle in motion. Furthermore, operating conditions of automotive electronics components (temperature, humidity, vibration, acceleration, etc.), their lifetime, and their spare part availability are differentiators to what is common for consumer and industrial devices (FIGURE 3).

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Currently, some of the most technologically advanced vehicles integrate around 450 semiconductor devices. As they become significantly more sophisticated, the semiconductor content will drastically increase, with many components based on the most advanced semiconductor technology available. Introducing artificial intelligence will require advanced processors capable of computing massive amount of data stored in high-performance and high capacity memory devices. This implies that not only the most advanced semicon- ductor devices will be used, but that these will need to achieve the highest degree of reliability to allow a flawless operation of predictive algorithms.

It is expected that smart vehicles capable of fully autonomous driving will employ up to 7,000 chips. In this case, even a failure rate of 1ppm, already very low by any standard today, would lead to 7 out of 1,000 cars with a safety risk. This is simply unacceptable.

The automotive electronics industry has therefore introduced quality excellence programs aimed at a zero defect target. Achieving such a goal requires a lot of effort and all constituents of the supply chain must do their part.

The automotive electronics industry is one of the most conservative in terms of change management. Longestablished standards and documentation procedures ensure traceability of design and manufacturing deviations. Qualification of novel or modified products is generally costly and lengthy. This is where material suppliers can offer competence and expertise to provide material with the highest quality standards.

What does this mean for a material supplier?

As a direct contact to its customer, the material supplier is responsible for the complete supply chain from the source of the raw material to the delivery at the customer’s gate. The material supplier is also accountable for long-term supply in accordance with the customer’s objectives.
There are essentially two fields where the material supplier can support its customer: quality and supply chain (FIGURE 4).

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Given the constraints of the automotive electronics market, material qualification must follow extensive procedures. While a high degree of material purity is a prerequisite, manufacturing processes are actually much more sensitive to deviations of material quality, as they potentially lead to process recalibration. Before qualification starts, it is critical that candidate materials are comprehensively documented. This includes the manufacturing process, the transport, the storage, and, where appropriate, the purifi- cation and transfill operations. Systematic auditing must be regularly performed according to customers’ standards. As a consequence, longer qualification times are expected. Any subsequent change in the material specification, origin, and packaging must be duly documented and is likely to be subject to a requalification process.

Material quality is obviously a critical element that must be demonstrated at all times. This commands the usage of high-quality products with a proven record. Sources already qualified for similar applica- tions are preferred to mitigate risks. These sources must show long-term business continuity planning, with process improvement programs in place. Purity levels must be carefully monitored and documented in databases. State-of-the-art analysis methods must be used. When necessary, containment measures should be deployed systematically. Given the long operating lifetime of automotive electronic compo- nents, failure can be related to a quality event that occurred a long time before.

Because of the necessary long-term availability of the electronics components and the material qualification constraints, manufacturers and suppliers will generally favor a supply contract over several years. Therefore, the source availability and the supply chain must be guaranteed accordingly.

Material suppliers are implementing improved quality management systems for their products in order to fulfill the expectations of their customers, in terms of quality monitoring and trace- ability. Certificate of analysis (COA) or consistency checks are not sufficient anymore; more data is required. In case deviation is detected, the inves- tigation and response time must be drastically reduced and allow intervention before delivery to the customer. Finally, the whole supply chain must be monitored.

Several tools must be implemented in order to maintain a reliable supply chain of high-quality products (FIGURE 5): statistical process and quality controls (SPC/SQC), as well as measurement systems analysis (MSA), allow systematic and reliable measurement and information recording for traceability. Imple- menting these tools particularly at the early stages of the supply chain allows an “in-time” response and correction before the defective material reaches the customer’s premises. Furthermore, some impurities that were ignored before may become critical, even below the current detection limits. Therefore, new measurement techniques must be continuously inves- tigated in order to enhance the detection capabilities.

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Finally, a robust supply chain must be ensured. It is imperative for a material supplier to be prepared to handle critical business functions such as customer orders, overseeing production and deliveries, and other various parts of the supply chain in any situation. Business continuity planning (BCP) was introduced several years ago in order to identify and mitigate any risk of supply chain disruption.

Analyzing the risks to business operations is fundamental to maintaining business continuity. Materials suppliers must work with manufacturers to develop a business continuity plan that facilitates the ability to continue to perform critical functions and/or provide services in the event of an unexpected interruption. The goal is to identify potential risks and weakness in current sourcing strategies and supply chain footprint and then mitigate those risks.

Because of the efforts necessary to qualify materials, second sources must be available and prepared to be shipped in case of crisis. Ideally, different sources should be qualified simultaneously to avoid any further delay in case of unplanned sourcing changes. Material suppliers with global footprint and worldwide sourcing capabilities offer additional security. Multiple shipping routes must be considered and planned in order to avoid disruption in the case, for instance, of a natural disaster or geopolitical issue affecting an entire region.

Material suppliers need to be aware and monitor regulations specific to the automotive electronics industry such as ISO/TS16949 (quality management strategy for automotive industries). This standard goes above and beyond the more familiar ISO 9001 standard, but by understanding the expectations of suppliers to the automotive industry, suppliers can ensure alignment of their quality systems and the documentation requirements for new product development or investigations into non-conformance.

Future of automotive electronics

With the increasing sophistication of future vehicles, new and more advanced semiconductor technologies will be used and vehicles will become technology centers. These technologies will allow communication and guidance computing. Most of these components (logic or memory) will be built by manufacturers relatively new to the automotive electronics world— either integrated device manufacturers (IDM) or foundries.

In order to comply with the current quality standards of the automotive industry, these manufacturers will need to adhere to more stringent standards imposed by the automobile industry. They will find support from materials suppliers like Linde that are capable of deliv- ering high-quality materials associated with a solid global supply chain who have acquired global experience in automotive electronics.

For more information about this topic or Linde Electronics, visit www.linde.com/electronics or contact Francesca Brava at [email protected].

After several years of low and inconsistent growth rates primarily because of intense pricing pressure, the market for semiconductor sensors and actuators finally caught fire in 2016 with several of its largest product categories—acceleration/yaw and magnetic-field sensors and actuator devices—recording strong double-digit sales increases in the year, according to IC Insights’ new 2017 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.  In addition to the easing of price erosion, substantial unit-shipment growth in sensors and actuators continues to be fed by the spread of intelligent embedded control, new wearable systems, and the expansion of applications connected to the Internet of Things, says the 2017 O-S-D Report.

The new 360-page report shows worldwide sensor sales grew 14% in 2016 to a record-high $7.3 billion, surpassing the previous annual peak of $6.4 billion set in 2015, when revenues increased 3.7%. Actuator sales climbed 19% in 2016 to an all-time high of $4.5 billion from the previous record of $3.8 billion in 2015.  The 2017 O-S-D Report forecasts total sensor sales rising by a compound annual growth rate (CAGR) of 7.5% in the next five years, reaching $10.5 billion in 2021, while actuator dollar volumes are expected to increase by a CAGR of 8.4% to nearly $6.8 billion in the same timeframe.  Figure 1 shows the relative market sizes of the five main product categories in the sensors/actuator segment, along with the projected five-year growth rates for the 2016-2021 forecast period.

The sensor/actuator market ended four straight years of severe price erosion in 2016 and finally benefitted from strong unit growth.  The average selling price (ASP) of sensors and actuators declined by -0.9% in 2016 versus an annual average of -9.3% during the four previous years (2012-2015), says IC Insights’ new O-S-D Report.  All sensor product categories and the large actuator segment registered double-digit sales growth in 2016.  It was the first time in five years that sales growth was recorded in all sensor/actuator product categories, partly due to the easing of price erosion but also because of continued strong unit demand worldwide.  Sensor/actuator shipments grew 17% in 2016 to a record-high of 20.3 billion units from 17.4 billion in 2015, when the volume also increased 17%.

Figure 1

Figure 1

Strong 2016 sales recoveries occurred in acceleration/yaw-rate motion sensors (+15%), magnetic-field sensors and electronic compass chips (+18%), and the miscellaneous other sensor category (+20%) after market declines were registered in 2015. Sales growth also strengthened in pressure sensors, including MEMS microphone chips, (+10%) and actuators (+19%) in 2016.  The new O-S-D Report forecasts sales of acceleration/yaw sensors growing 9% in 2017 to about $3.0 billion, magnetic-field sensors (and compass chips) rising 8% to nearly $2.0 billion, and pressure sensors increasing 8% to $2.7 billion this year.  Actuator sales are projected to grow 8% in 2017 to about $4.9 billion.

About 82% of the sensors/actuators market’s revenues in 2016 came from semiconductors built with microelectromechanical systems (MEMS) technology—meaning pressure sensors, microphone chips, acceleration/yaw motion sensors, and actuators that use MEMS-built transducer structures to initiate physical action in a wide range of devices, including inkjet printer nozzles, microfluidic chips, micro-mirrors, and surface-wave filters for RF signals.  MEMS-built products represented 48% of total sensor/actuator shipments in 2016, or about 9.8 billion units last year.

MEMS-based product sales climbed 15.4% in 2016 to a record-high $9.7 billion after rising 5.1% in 2015 and 5.8% in 2014.   Some inventory corrections and steep ASP erosion in MEMS-built devices have suppressed revenue growth in recent years, but this group of products—like the entire sensors/actuator market—is benefitting from increased demand in new wearable systems, IoT, and the rapid spread of intelligent embedded control, such as autonomous automotive features rolling into cars.  MEMS-based sensors and actuator sales are forecast to rise 7.9% in 2017 to $10.5 billion and grow by a CAGR of 8.0% in the 2016-2021 period to $14.3 billion, says the new O-S-D Report.

STMicroelectronics (NYSE: STM) announced today the appointment of Jean-Marc Chery as Deputy CEO, effective July 1, 2017. Chery currently serves as Chief Operating Officer and, in his new role, he will continue to report to Carlo Bozotti, ST’s President and CEO.

In this new role, Chery will hold overall responsibility for Technology and Manufacturing as well as for Sales and Marketing.

A new organization will be also put in place. Its goal is to continue to build on the success of ST’s strategy, focused on Smart Driving and Internet of Things, with a strong market-driven and innovation approach.

ST’s Executive Team members will be:

·         Orio Bellezza, President, Global Technology and Manufacturing
·         Marco Cassis, President, Global Sales and Marketing
·         Claude Dardanne, President, Microcontrollers and Digital ICs Group
·         Carlo Ferro, Chief Financial Officer and President, Finance, Legal, Infrastructure and Services
·         Marco Monti, President, Automotive and Discrete Group
·         Georges Penalver, Chief Strategy Officer and President, Strategy, Communication, Human Resources and Quality
·         Benedetto Vigna, President, Analog, MEMS and Sensors Group.

These appointments and new organization are effective July 1st, 2017, upon shareholder approval of the reappointment of Carlo Bozotti as the sole member of the Managing Board and President and CEO of ST, at the Company’s next Annual General Meeting.

Chery began his career in the Quality organization of Matra, the French engineering group. In 1986, he joined Thomson Semiconducteurs, which subsequently became ST, and held various management positions in product planning and manufacturing, rising to lead ST’s wafer fabs in Tours, France, and later in Rousset, France. In 2005, Chery took charge of ST’s Front-End Manufacturing in Asia Pacific. In 2008, he was promoted Chief Technology Officer and assumed additional responsibilities for Manufacturing and Quality (2011) and the Digital Product Sector (2012). In 2014, he was promoted Chief Operating Officer.

Chery chairs the Board of STS, ST’s manufacturing joint venture in China, and holds board membership at the European microelectronics R&D program AENEAS.
Jean-Marc Chery was born in Orleans, France, in 1960, and graduated with a degree in Engineering from the ENSAM engineering school in Paris, France.