Category Archives: Packaging

GOWIN Semiconductor Corp., a developer of programmable logic devices, announces 2 new additions to the current families of embedded memory FPGA devices, the GW1NR-LV4MG81 and GW1NSR-LX2CQN48.  As computing functions are being distributed to edge locations, the need for silicon to adapt to these new uses is becoming prevalent.  The 2 new embedded FPGA devices were designed with low power, small package size, and low cost in mind.

Adopting an edge to cloud infrastructure is challenging.  Each portion of the chain has its own unique characteristics in design.  For the edge, size of sensor or data gatherer affects product real estate; power consumption affects the power source, especially battery life.  The new embedded memory FPGA devices solve these issues by enhancing the integration of multiple devices into a nice, single package device.

“GOWIN’s vision has always been one of developing new products for customer’s needs,” said Jason Zhu, CEO of GOWIN Semiconductor.  “We saw a lack of product integration at the edge and aimed to fix this with easy to use solutions at cost-effective price points.”

The GW1NR-LV4MG81 is a 4K LUT FPGA fabric with 64Mb internal high-speed memory.  The package size is ultra-small, 4.5mm x 4.5 mm PBGA and .83mm thick.  A great logic device for applications where the thickness is an issue.  Power consumption has been optimized to the lowest possible using TSMC’s 55nm LP process.  And up to 69 user IO’s are available supporting GOWIN’s flexible IO structures.

In a 5mm x 5mm QFN package, the GW1NSR-LX2CQN48 is GOWIN’s first device that combines a 2K LUT FPGA fabric with 32Mb internal high-speed memory and an Arm Cortex M3 microprocessor.  With additional user programmable flash, internal SRAM, ADC, and both USB2.0 and MIPI D-PHY interfaces, this makes the GW1NSR-LX2CQN48 a true SoC to solve low power requirements at the edge and elsewhere.

GOWIN offers a complete all-in-one toolchain for both FPGA fabric programming and Cortex M3 programming.  In addition, a complete library of IP cores and reference designs are available to assist in developing platform solutions.  All of these resources are available for download on GOWIN’s website, www.gowinsemi.com.

The SEMI-THERM Educational Foundation (STEF) announced that the 35thAnnual Thermal Measurement, Modeling and Management Symposium will take place from Monday, March 18thto Friday, March 22nd, 2019.  SEMI-THERM is currently accepting submissions for extended abstracts, peer-reviewed papers and presentation only abstracts. The deadline for each of these submissions types is October 12, 2018.

The SEMI-THERM Conference focuses on a broad range of cooling topics, from component and system level thermal management solutions to advanced cooling techniques and technologies. Applications of interest include Internet of Things, data centers, aerospace systems, drones, digital imaging, wearable and consumer electronics.

Conference committee chairs and presenters are leaders and practitioners from companies including Aavid Thermacore, Advanced Thermal Solutions (ATS), Cisco, Facebook, Google, Huawei, IBM, Intel, Microsoft, Qualcomm, and other organizations and academia dedicated to solving thermal challenges.

“Presenting at SEMI-THERM is the perfect opportunity to educate colleagues and customers of a new technology or application and to gain recognition for your company, organization or university research.,” said Bernie Siegal, co-founder of the conference and recipient of SEMI-THERM’s Lifetime Achievement Award. “This program facilitates interactive communication between representatives of world-class research institutes and international corporations, as well as thermal consultants,” he added.

Symposium Highlights

SEMI-THERM is an international symposium dedicated to the thermal management and characterization of electronic components and systems. See topics below.

In addition to technical sessions and keynote presentations, the conference and exhibition includes technical short courses, embedded tutorials, vendor workshops, how-to courses and panel discussions on current thermal technologies.

For more information and to submit a paper, please visit:

http://semi-therm.org

Mentor, a Siemens business, today announced LightSuite™ Photonic Compiler – the industry’s first integrated photonic automated layout system. This new tool enables companies designing integrated photonic layouts to describe designs in the Python language, from which the tool then automatically generates designs ready for fabrication. The resulting design is “Correct by Calibre” – with the implementation precisely guided by Mentor’s Calibre® RealTime Custom verification tool. LightSuite Photonic Compiler enables designers to generate as well as update large photonic layouts in minutes versus weeks.

With this breakthrough technology, companies can dramatically speed the development of integrated photonic designs that will bring speed-of-light communications directly into high-speed networking and high-performance computing (HPC) systems. It also speeds the development of more cost-effective LiDAR technology, which is seen as essential to enabling the mass deployment of autonomous vehicles.

“Mentor’s LightSuite Photonic Compiler represents a quantum leap in automating what has up to now been a highly manual, full-custom process that required deep knowledge of photonics as well as electronics,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor, a Siemens business. “With the new LightSuite Photonic Compiler, Mentor is enabling more companies to push the envelope in creating integrated photonic designs.”

“LightSuite Photonic Compiler fixes the biggest roadblocks preventing industry-wide adoption of electro-optical design and simulation of photonic chips,” said M. Ashkan Seyedi, Ph.D., senior research scientist, Hewlett Packard Enterprise. “Photonic chips promise amazing performance, but designing circuits today is just too difficult and requires specialized knowledge. LightSuite Photonic Compiler circumvents those challenges and enables scalability. I’m thrilled to have worked with Mentor to develop this tool to make it possible for anyone to design and build photonic circuits as easily as designing electronic circuits.”

Until now, photonic designers have been forced to use analog, full-custom IC tools to create photonic designs. In this flow, designers manually place components from a process design kit (PDK) and then interconnect those components manually. Photonic components must be interconnected with curved waveguides. After they have manually placed and interconnected the components, they typically perform a full Calibre physical verification run to check for design rule violations, as Calibre DRC can find violations even in photonic designs.

Mentor designed the new LightSuite Photonic Compiler specifically for photonic layout so that engineers have complete control of their layouts and can use the tool to automatically perform the placement and interconnecting of both photonic and electrical components. The designers create a Python script that is used to drive the LightSuite Photonic Compiler. Initial placement can also be defined in Python, or come from a pre-placed OpenAccess design. Next, the tool interconnects photonics components with curved wave guides. As some of the components might contain built-in electrical elements, the tool will route these electrical connections simultaneously along with the curved waveguides.

LightSuite Photonic Compiler uses Calibre RealTime Custom during the inner placement and routing loop, resulting in a layout that is design-rule correct. The tool enables designers to perform “what-if” design exploration for photonics designs, which was prohibitively time consuming with manual layout. With this new level of automation, designers can generate a new layout in minutes versus weeks for large designs.

Mentor will demonstrate LightSuite Photonic Compiler at ECOC in Rome, September 24 – 26 at Stand 436. LightSuite Photonic Compiler will be available on October 1.

Amkor Technology announced on September 10th the opening of its new manufacturing and test plant at Longtan Science Park in Taiwan.

“Demand for Amkor’s advanced assembly and test services in Taiwan continues to increase. The opening of our fourth factory in Taiwan will allow us to keep pace with that demand,” said Steve Kelley, Amkor’s president and CEO. “Our new Longtan facility will focus on wafer probe and die processing, complementing the wafer-level and other advanced packaging capabilities of our other three factories.”

The new facility is Amkor’s first manufacturing plant in Longtan Science Park, which is well known for incubating Taiwanese high-tech businesses, including those in the semiconductor industry. The Science Park has strict environmental protection standards and only companies that are in full compliance are permitted. Amkor is also seeking ISO 15408 Common Site Criteria certification for the Longtan plant to ensure rigorous security protection during the manufacturing process.

“I am pleased to announce the opening of our new factory in Longtan, which enters its production phase this month,” said YongChul Park, Amkor’s executive vice president, Worldwide Manufacturing. “This expansion signifies Amkor’s ongoing commitment to invest globally and showcases our ability to leverage resources internationally.”

Below are photos taken during Monday’s opening ceremony at Amkor’s new Taiwan factory.

Japan is at the heart of the semiconductor industry as the era of artificial intelligence (AI) dawns. SEMICON Japan 2018 will highlight AI and SMART technologies in Japan’s industry-leading event. Registration is now open for SEMICON Japan, Japan’s largest global electronics supply chain event, December 12-14 at Tokyo Big Sight in Tokyo.

Themed “Dreams Start Here,” SEMICON Japan 2018 reflects the promise of AI, Internet of Things (IoT) and other SMART technologies that are shaping the future. Japan is positioned to help power a semiconductor industry expansion that is enabling this new path ahead, supplying one-third of the world’s semiconductor equipment and half of its chip IC materials.

According to VLSI Research, seven of the world’s top 15 semiconductor equipment manufacturers in 2017 are headquartered in Japan. In the semiconductor materials market, Japanese companies dominate silicon wafers, photoresists, sputtering targets, bonding wires, lead frames, mold compounds and more. For SEMICON Japan visitors, the event is the ideal platform for connecting with Japan’s leading suppliers.

The SMART Application Zone at SEMICON Japan will once again connect SMART industries with the semiconductor supply chain to foster collaboration across the electronics ecosystem.

SEMICON Japan Keynotes

SEMICON Japan opening keynotes will feature two young leaders of Japan’s information and communications technology (ICT) industry sharing their vision for the industry:

Motoi Ishibashi, CTO of Rhizomatiks, will discuss the latest virtual and mixed reality technologies. Rhizomatiks, a Japanese media art company that staged the Rio Olympic Games closing ceremony, will orchestrate the opening performance at SEMICON Japan 2018. The company is dedicated to creating large-scale commercial projects combining technology with the arts.

Toru Nishikawa, president and CEO at Preferred Networks, will explore computer requirements for enabling deep learning applications. Preferred Networks, a deep-learning research startup, is conducting collaborative research with technology giants including Toyota Motors, Fanuc, NVIDIA, Intel and Microsoft.

Registration

For more information and to register for SEMICON Japan, visit www.semiconjapan.org/en/. Registration for the opening keynotes and other programs will open October 1.

This premier international conference, sponsored by the IEEE Electronics Packaging Society (IEEE EPS), covers a wide spectrum of electronic packaging technology topics, including components, materials, assembly, interconnect design, device and system packaging, wafer level packaging, Si photonics, LED and IoT, optoelectronics, 2.5D and 3D integration technology, and reliability.

The ECTC Program Committee, with more than 200 experts from broad-ranging technical areas, is committed to creating an engaging technical program for all. ECTC typically attracts more than 1,400 attendees from over 25 countries. Last year’s 68th ECTC in San Diego, California, had 1,738 attendees, with 331 papers and interactive presentations featured in 41 sessions.

The 69th ECTC program will include six parallel technical sessions in the mornings and afternoons over three days, along with other special topic panel discussions to present high-level trends and best practices in the industry. Professional Development Courses (PDCs) will also be offered by world-class experts, enabling participants to broaden their technical knowledge base.

The technical program and PDCs will be supplemented by Technology Corner Exhibits, which provide an opportunity for leading companies in the electronic components, materials, and packaging fields to exhibit their latest technologies and products. Last year’s 68th ECTC matched our record number of 106 exhibitors.

Please submit an abstract between 250 and 750 words that describes the scope, content, and key points of your proposed technical paper at www.ectc.net. You are also welcome to submit proposals for PDCs. All abstracts and manuscripts must be original, free of commercial content, and non-confidential.

Deadlines to Remember:

  • 0.08.2018| Abstracts and PDC Proposals Due

12.10-2018| Authors Notified of Acceptance

01.02.2019| Advance Online Registration Opens

  • 02.23.2018| Manuscripts due for inclusion in the Conference Proceedings.

SEMI announced today the October 9 deadline for presenters to submit abstracts for the annual SEMI Advanced Semiconductor Manufacturing Conference(ASMC). ASMC, May 6-9, 2019, in Saratoga Springs, New York, will feature technical presentations of more than 90 peer-reviewed manuscripts covering critical process technologies and fab productivity.

ASMC 2019 will feature keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, and tutorials. The conference will also feature a special student poster session to highlight student projects related to semiconductor manufacturing.

Selected speakers will present to IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. All technical papers will be published by IEEE, and authors also may receive an invitation to publish their papers in a special section for ASMC 2019 to be featured in IEEE Transactions on Semiconductor Manufacturing. Technical abstracts are due October 9, 2018, and can be submitted here. 

ASMC 2019 will cover the following topics:

  • Advanced Equipment Processes and Materials
  • Advanced Metrology
  • Advanced Equipment Processes and Materials
  • Advanced Patterning / Design for Manufacturability
  • Advanced Process Control
  • Contamination Free Manufacturing
  • Big Data Management and Mining
  • Defect Inspection and Reduction
  • Discrete and Power Devices
  • Enabling Technologies and Innovative Devices
  • Equipment Reliability and Productivity Enhancements
  • Factory Automation
  • The Fabless Experience
  • Green Factory
  • Industrial Engineering
  • Lean Manufacturing
  • MOL and Junction Interfaces
  • Smart Manufacturing
  • Yield Enhancement/Learning
  • Yield Methodologies
  • 3D Packaging and Through Silicon Via

ASMC, in its 30th year, continues to fill a critical need for the industry, providing a venue for professionals to network, learn and share knowledge about semiconductor manufacturing best practices.

Details on how to upload abstracts can be found here. To learn more about the conference and the selection process, please contact Margaret Kindling at [email protected] or call 1.202.393.5552.   

Papers co-authored by device manufacturers, equipment or materials suppliers, and/or academic institutions that demonstrate innovative, practical solutions for advancing semiconductor manufacturing are highly encouraged.

ASMC is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing

SEMI and TechSearch International today announced a new edition of the Worldwide OSAT Manufacturing Sites Database – the only outsourced semiconductor assembly and testing (OSAT) supplier database available in the market. The report, an essential business tool for anyone interested in device packaging, tracks facilities that provide packaging and testing services to the semiconductor industry.

The new edition includes more than 80 updates spanning packaging technology offerings, product specialization, new facility announcements, as well as ownership/shareholder updates, bringing the total number of facilities tracked in the report to 320.

Combining the expertise of SEMI and TechSearch International, the Worldwide OSAT Manufacturing Sites Database update also features a new section listing the revenues of the world’s top 20 OSAT companies in 2016 and 2017 and captures changes in technology capabilities and service offerings at various facilities.

The Worldwide OSAT Manufacturing Sites Database is a comprehensive report offering insights into global OSAT facilities in China, Taiwan, Korea, Japan, Southeast Asia, Europe, and the Americas. The report highlights new and emerging packaging offerings by manufacturing location and by companies. Specific details tracked include:

  • Plant site location, technology, and capability: Packaging, Test, and other product specializations, such as sensor, automotive and power devices are highlighted.
  • Packaging assembly service offered: BGA, specific leadframe type such as QFP, QFN, SO, flip chip bumping, WLP, Modules/SIP, and sensors.
  • New manufacturing sites announced, planned or under construction.

Tracking advances in packaging technology, which directly affects chip performance, reliability and cost, requires understanding company offerings by location. Key features of the updated report include:

  • More than 120 companies and 300 facilities
  • Over 90 facilities offering leadframe CSP
  • Over 25 bumping facilities, including 20 with 300mm wafer bumping capacity
  • More than 45 facilities offering WLCSP technology
  • New facilities offering FOWLP and FOPLP
  • 92 facilities in China, 89 in Taiwan, 39 in Southeast Asia

The database findings are based on information gathered and compiled from over 120 companies globally. All information in the Worldwide OSAT Manufacturing Sites Database was gathered by SEMI and TechSearch International. Report licenses are available for single-user and multi-users. SEMI members save 16 percent or more depending on the type of license.

For more information about the Worldwide OSAT Manufacturing Sites Database and to order a sample copy, please click here. For pricing and ordering information, please click here.

By Richard Allen

The arrival of Fan-Out Panel Level Packaging (FO-PLP) appears to be at a perfect time: This technology will leverage processes developed for Three Dimensional Stacked Integrated Circuits (3DS-IC) as well as panel processing technologies developed for industries such as solar panels and large-screen TVs.  In this combination, FO-PLP promised the improved performance of 3DS-IC, without the expense. There was just one problem…

That problem is the size of the panels to be processed. As different companies developed FO-PLP processes, they chose panels sized to meet certain technical or business goals, or chose a size based on familiarity. So, processes were being developed for more than ten sizes, each of which had one or more companies championing them.

For people in the wider semiconductor industry, the development of many processes, each with a unique panel size brought a feeling of déjà vu, reminding them of the 1970s, when each device manufacturer created their own specification for wafer size, forcing them to manufacture their own wafer processing equipment since no external manufacturer was willing to produce tools usable only by a single customer.

SEMI responded by developing an industry consensus silicon wafer standard – which described basic parameters, including diameter and thickness – to resolve the issue. Almost overnight the landscape changed, and new tool manufacturers sprung up, enabling the incredible growth that has persisted over more than 40 years.

Recently, Cristina Chu (TEL NEXX) presented the state of FO-PLP to the North America Chapter of the SEMI Three-Dimensional Packaging and Integration (3DP&I) Technical Committee, suggesting that the Committee develop a single standard dimension that would enable the technology to move into high-volume manufacturing.

The Committee began by surveying the industry to determine the interest level in such a standard as well as its contents.  A key finding came in response to the question “Would you support a standardized panel size?” Overwhelmingly, over 70 percent of the respondents supporting the idea for the standard, with less than 2 percent opposed. The survey also asked if other parameters should be standardized and, if so, which parameters. Majority responses pointed to edge profile, flatness, and warp, prompting the 3DP&I Committee to immediately form the FO-PLP Panel Task Force (TF) to develop such a standard. Chu and Richard Allen (NIST) agreed to chair the TF and respondents to the survey were asked to participate as TF members.

The TF initially decided to follow the model of SEMI M1, Specification for Polished Single Crystal Silicon Wafers, and write the document as a purchase specification. The purchase specification would indicate a limited number of mandatory parameters, identified as those that serve as bottlenecks to the development of a FO-PLP ecosystem. Parameters that were not perceived as bottlenecks but might be useful for implementing a FO-PLP process would be included as optional.

Working under the SEMI Standards umbrella allowed the TF to take advantage of work done in the development of other standards, without having to recreate it from scratch. In particular, Flatness and Shape were repurposed from SEMI M1, ensuring consistent definitions of these parameters.

The TF could not come to consensus on how the other parameters should be categorized, so the decision was made to move the ordering table to a new Appendix as optional.

The TF will be balloting its first specification for panel substrate in the upcoming cycle, which opens September 5, 2018 (Cycle 7). The voting is open to all industry experts. Based on the feedback, the task force will continue to refine and otherwise improve the specification by incorporating other parameters that are critical to making FO-PLP a reality.

SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.

For more information regarding FO-PLP Panel Task Force activities, please contact Laura Nguyen at [email protected].

Richard Allen is a physicist in the Nanoscale Metrology Group in the Engineering Physics Division of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST). 

Originally published on the SEMI blog.

Brewer Science, Inc. today from SEMICON Taiwan introduced the latest additions to its industry-leading BrewerBOND® family of temporary bonding materials, as well as the first product in its new BrewerBUILD™ line of thin spin-on packaging materials. BrewerBUILD delivers an industry-first solution to address manufacturers’ evolving wafer-level packaging challenges.

The BrewerBOND T1100 and BrewerBOND C1300 series combine to create Brewer Science’s first complete, dual-layer system for temporary bonding and debonding of product wafers. The new system was developed for power, memory and chip-first fan-out devices – all of which have stringent requirements with respect to temperature, power and performance. The system can be used with either mechanical or laser debonding methods.

The BrewerBUILD material was specifically created for redistribution-layer (RDL)-first fan-out wafer-level packaging (FOWLP). Developed to meet the needs of chipmakers looking to transition from chip-first FOWLP but not yet ready to tackle 2.5D/3D packaging, the single-layer material is compatible with both wafer- and panel-level temporary bonding/debonding processes.

“As industry requirements advance, Brewer Science continues to push forward the state of the art in our materials offerings,” said Kim Arnold, executive director, Advanced Packaging Business Unit, Brewer Science Inc. “Through close collaboration with our customers, we are driving the technology forward, leveraging our R&D braintrust to create unique solutions like these that are designed to meet customers’ needs – current and future.”