Category Archives: Packaging

A new study by scientists at the National Institute of Standards and Technology (NIST) has uncovered a source of error in an industry-standard calibration method that could lead microchip manufacturers to lose a million dollars or more in a single fabrication run. The problem is expected to become progressively more acute as chipmakers pack ever more features into ever smaller space.

The error occurs when measuring very small flows of exotic gas mixtures. Small gas flows occur during chemical vapor deposition (CVD), a process that occurs inside a vacuum chamber when ultra-rarefied gases flow across a silicon wafer to deposit a solid film. CVD is widely used to fabricate many kinds of high-performance microchips containing as many as several billion transistors. CVD builds up complex 3D structures by depositing successive layers of atoms or molecules; some layers are only a few atoms thick. A complementary process called plasma etching also uses small flows of exotic gases to produce tiny features on the surface of semiconducting materials by removing small amounts of silicon.

The exact amount of gas injected into the chamber is critically important to these processes and is regulated by a device called a mass flow controller (MFC). MFCs must be highly accurate to ensure that the deposited layers have the required dimensions. The potential impact is large because chips with incorrect layer depths must be discarded.

“Flow inaccuracies cause nonuniformities in critical features in wafers, directly causing yield reduction,” said Mohamed Saleem, Chief Technology Officer at Brooks Instrument, a U.S. company that manufactures MFCs among other precision measurement devices. “Factoring in the cost of running cleanrooms, the loss on a batch of wafers scrapped due to flow irregularities can run around $500,000 to $1,000,000. Add to that cost the process tool downtime required for troubleshooting, and it becomes prohibitively expensive.”

Modern nanofabrication facilities cost several billion dollars each, and it is generally not cost-effective for a company to constantly fine tune CVD and plasma etching. Instead, the facilities rely on accurate gas flows controlled by MFCs. Typically, MFCs are calibrated using the “rate of rise” (RoR) method, which makes a series of pressure and temperature measurements over time as gas fills a collection tank through the MFC.

“Concerns about the accuracy of that technique came to our attention recently when a major manufacturer of chip-fabrication equipment found that they were getting inconsistent results for flow rate from their instruments when they were calibrated on different RoR systems,” said John Wright of NIST’s Fluid Metrology Group, whose members conducted the error analysis.

Wright was particularly interested because for many years he had seen that RoR readings didn’t agree with results obtained with NIST’s “gold standard” pressure/volume/temperature/time system. He and colleagues developed a mathematical model of the RoR process and conducted detailed experiments. The conclusion: conventional RoR flow measurements can have significant errors because of erroneous temperature values. “The gas is heated by flow work as it is compressed in the collection tank, but that is not easily accounted for: it is difficult to measure the temperature of nearly stationary gas.”

Wright and colleagues found that without corrections for these temperature errors, RoR readings can be off by as much as 1 percent, and perhaps considerably more. That might not seem like a lot, but low uncertainty is critical to attaining uniformity and quality in the chip manufacturing process. And the challenge is growing. Current low-end flow rates in the semiconductor industry are in the range of one standard cubic centimeter (1 sccm)–about the volume of a sugar cube–per minute, but they will soon shrink by a factor of 10 to 0.1 sccm.

Precise flow measurement is a particularly serious concern for manufacturing processes that use etching of deposited layers to form trench-like features. In that case, the MFC is often open for no more than a few seconds.

“A tiny amount of variation in the flow rate has a profound effect on the etch rate and critical dimensions of the structures” in very large-scale integrated circuits, said Iqbal Shareef of Lam Research, a company headquartered in California that provides precision fabrication equipment to microchip manufacturers.

“So, we are extremely concerned about flow rates being accurate and consistent from chamber to chamber and wafer to wafer,” Shareef said. “Our industry is already headed toward very small flow rates.”

“We are talking about wafer uniformity today on the nanometer and even subnanometer scale,” Shareef said.

That’s very small. But it’s what the complexity of three-dimensional chip manufacturing increasingly demands. Not so long ago, “a 3D integrated circuit used to have four layers of metals,” said William White, Director of Advanced Technology at HORIBA Instruments Incorporated, a global firm that provides analytical and measurement systems. “Now companies are regularly going to 32 layers and sometimes to 64. Just this year I heard about 128.” And some of those chips have as many as 3,000 process steps.

“Each 300 mm wafer can cost up to $400, and contains 281 dies for a die size of 250 to 300 mm2,” Brooks’ Saleem said. “Each die in today’s high-end integrated circuits consists of about three to four billion transistors. Each wafer goes through 1 or 2 months of processing that includes multiple runs of separate individual processes,” including chemical vapor deposition, etch, lithography and ion implantation. All those processes use expensive chemicals and gases.

Many companies are already re-examining their practices in light of the NIST publication, which provides needed theoretical explanations for the source of RoR flow measurement errors. The theory guides designers of RoR collection tanks and demonstrates easy-to-apply correction methods. RoR theory shows that different temperature errors will occur for the different gases used in CVD processes. The NIST publication also provides a model uncertainty analysis that others can use to know what level of agreement to expect between MFCs calibrated on different RoR systems.

“NIST serves as a reliable reference for knowledge and measurement where industry can assess agreement between their systems,” Wright said. “As manufacturers’ measurement needs push to ever lower flows, so will NIST calibration standards.”

Global semiconductor industry revenue grew 4.4 percent, quarter over quarter, in the second quarter of 2018, reaching a record $120.8 billion. Semiconductor growth occurred in all application markets and world regions, according to IHS Markit (Nasdaq: INFO).

“The explosive growth in enterprise and storage drove the market to new heights in the second quarter,” said Ron Ellwanger, senior analyst and component landscape tool manager, IHS Markit. “This growth contributed to record application revenue in data processing and wired communication markets as well as in the microcomponent and memory categories.”

Due to the ongoing growth in the enterprise and storage markets, sequential microcomponent sales grew 6.5 percent in the second quarter, while memory semiconductor revenue increased 6.4 percent. “Broadcom Limited experienced exceptional growth in its wired communication division, due to increased cloud and data-center demand,” Ellwanger said.

Memory component revenue continued to rise in the second quarter, compared to the previous quarter, reaching $42.0 billion dollars. “This is the ninth consecutive quarter of rising revenue from memory components, and growth in the second quarter of 2018 was driven by higher density in enterprise and storage,” Ellwanger said. “This latest uptick comes at a time of softening prices for NAND flash memory. However, more attractive pricing for NAND memory is pushing SSD demand and revenue higher.”

Semiconductor market share

Samsung Electronics continued to lead the overall semiconductor industry in the second quarter with 15.9 percent of the market, followed by Intel at 13.9 percent and SK Hynix at 7.9 percent. Quarter-over-quarter market shares were relatively flat, with no change in the top-three ranking. SK Hynix achieved the highest growth rate and record quarterly sales among the top three companies, recording 16.4 percent growth in the second quarter.

Integrated Device Technology, Inc. (IDT) (NASDAQ :IDTI ) announced today a strategic partnership with Steradian Semiconductor Pvt. Ltd. to deliver ultra-high resolution 4D mmWave imaging RADAR for emerging industrial, security, medical, and autonomous vehicle markets.

Steradian Semiconductor is a fabless semiconductor company based out of Bangalore, India. Steradian is founded by industry experts with decades of experience in designing cellular/RF and microwave transceiver ICs. Their unique IP has enabled IDT to offer highly differentiated “SenseVerse” series of RADAR transceiver ICs to our customers.

The IDT® SenseVerse SVR4410 IC is a multi-channel high resolution MIMO RADAR device that operates in the 76-81 GHz frequency band offering superior interference performance and the highest number of channels per device in the industry. With integrated beamforming and support for multi-device aggregation, the SVR4410 provides best-in-class angular resolution, range, and power consumption in a very small form factor. The two companies are collaborating on a series of roadmap ICs with increasing levels of integration and enable customers’ adoption by means of providing radar modules with integrated antennas, SVR transceiver ICs, radar processing IC and DSP algorithms.

“IDT’s SenseVerse RADAR family will add new dimension to sensing and vision, causing a disruptive change in Industry 4.0 and similar end markets needing high resolution solutions,” stated Sailesh Chittipeddi, executive vice president, global operations and chief technology officer at IDT. “IDT’s novel imaging RADAR architecture based on mmWave technology will be key to reliable and autonomous operation in various climatic conditions and continues IDT’s tradition of delivering high value-added solutions for its customers.”

“IDT’s SenseVerse RADAR family offers all weather high resolution sensing and will enhance and complement human and computer vision,” said Gireesh Rajendran, CEO of Steradian Semiconductor. “IDT’s SVR4410 and roadmap ICs together with Steradian’s RF expertise will offer exceptional value to a wide variety of application spaces.”

IDT’s SenseVerse RADAR products are currently sampling at selected customers.

A team of researchers led by the University of Minnesota has developed a new material that could potentially improve the efficiency of computer processing and memory. The researchers have filed a patent on the material with support from the Semiconductor Research Corporation, and people in the semiconductor industry have already requested samples of the material.

The findings are published in Nature Materials, a peer-reviewed scientific journal published by Nature Publishing Group.

This cross-sectional transmission electron microscope image shows a sample used for the charge-to-spin conversion experiment. The nano-sized grains of less than 6 nanometers in the sputtered topological insulator layer created new physical properties for the material that changed the behavior of the electrons in the material. Credit: Wang Group, University of Minnesota

“We used a quantum material that has attracted a lot of attention by the semiconductor industry in the past few years, but created it in unique way that resulted in a material with new physical and spin-electronic properties that could greatly improve computing and memory efficiency,” said lead researcher Jian-Ping Wang, a University of Minnesota Distinguished McKnight Professor and Robert F. Hartmann Chair in electrical engineering.

The new material is in a class of materials called “topological insulators,” which have been studied recently by physics and materials research communities and the semiconductor industry because of their unique spin-electronic transport and magnetic properties. Topological insulators are usually created using a single crystal growth process. Another common fabrication technique uses a process called Molecular Beam Epitaxy in which crystals are grown in a thin film. Both of these techniques cannot be easily scaled up for use in the semiconductor industry.

In this study, researchers started with bismuth selenide (Bi2Se3), a compound of bismuth and selenium. They then used a thin film deposition technique called “sputtering,” which is driven by the momentum exchange between the ions and atoms in the target materials due to collisions. While the sputtering technique is common in the semiconductor industry, this is the first time it has been used to create a topological insulator material that could be scaled up for semiconductor and magnetic industry applications.

However, the fact that the sputtering technique worked was not the most surprising part of the experiment. The nano-sized grains of less than 6 nanometers in the sputtered topological insulator layer created new physical properties for the material that changed the behavior of the electrons in the material. After testing the new material, the researchers found it to be 18 times more efficient in computing processing and memory compared to current materials.

“As the size of the grains decreased, we experienced what we call ‘quantum confinement’ in which the electrons in the material act differently giving us more control over the electron behavior,” said study co-author Tony Low, a University of Minnesota assistant professor of electrical and computer engineering.

Researchers studied the material using the University of Minnesota’s unique high-resolution transmission electron microscopy (TEM), a microscopy technique in which a beam of electrons is transmitted through a specimen to form an image.

“Using our advanced aberration-corrected scanning TEM we managed to identify those nano-sized grains and their interfaces in the film,” said Andre Mkhoyan, a University of Minnesota associate professor of chemical engineering and materials science and electron microscopy expert.

Researchers say this is only the beginning and that this discovery could open the door to more advances in the semiconductor industry as well as related industries, such as magnetic random access memory (MRAM) technology.

“With the new physics of these materials could come many new applications,” said Mahendra DC (Dangi Chhetri), first author of the paper and a physics Ph.D. student in Professor Wang’s lab.

Wang agrees that this cutting-edge research could make a big impact.

“Using the sputtering process to fabricate a quantum material like a bismuth-selenide-based topological insulator is against the intuitive instincts of all researchers in the field and actually is not supported by any existing theory,” Wang said. “Four years ago, with a strong support from Semiconductor Research Corporation and the Defense Advanced Research Projects Agency, we started with a big idea to search for a practical pathway to grow and apply the topological insulator material for future computing and memory devices. Our surprising experimental discovery led to a new theory for topological insulator materials.

“Research is all about being patient and collaborating with team members. This time there was a big pay off,” Wang said.

MRSI Systems (Mycronic Group), is expanding its high speed MRSI-HVM3 die bonder platform with the launch of the MRSI-HVM3P to offer configurations for active optical cable (AOC), gold-box packaging, and other applications in addition to chip-on-carrier (CoC).

This expansion is in response to our customer’s request to take advantage of the field-proven performance of the flexible high speed MRSI-HVM3 platform, for their other essential packaging applications in photonics manufacturing which are high volume and high mix by nature.

The new MRSI-HVM3P is the first major extension to the HVM3 family, equipped with inline conveyor for single fixture or multiple cassette inputs that can automatically transport large forms of carriers of the dies. This configuration is targeted at AOC or similar die-to-printed circuit board (PCB) applications, gold-box packaging, and CoC in fixture. The processes include eutectic, epoxy stamping, UV epoxy dispensing, and in-situ UV curing.

“With these extensions to our successful HVM3 platform, MRSI Systems is now able to offer flexible high volume die bonding solutions, not just for CoC, but also for PCB and box levels of packaging to our customers in photonics, sensors and other advanced technology fields,” said Dr. Yi Qian, Vice President of Product Management of MRSI Systems. “This is another demonstration of MRSI’s commitment to provide critical solutions promptly in response to our customers’ needs,” concluded Mr. Michael Chalsen, President of MRSI Systems.

Both MRSI-HVM3 and MRSI-HVM3P now carry the following options inherited from our long proven MRSI-M3 family:  localized heating, flip-chip bonding, and co-planarity bonding. These options are increasingly critical for new applications such as 400G transceivers and silicon photonics.

The MRSI-HVM3 product family delivers industry-leading speed, future-proof high precision (<3mm), and superior flexibility for true multi-process, multi-chip, high-volume production.

The launch of the MRSI-HVM3P builds on the success of our first configuration launched last year, the MRSI-HVM3 for CoC, Chip-on-Submount (CoS), and Chip-on-Baseplate (CoB) assembly using eutectic and/or epoxy stamping die bonding, which has proved to be the best-in-class die bonder with the leading speed, zero-time tool change between dies, and <3mm accuracy. The superior performance was enabled by dual head, dual stage, integrated “on-the-fly” tool changer, ultrafast eutectic stage, and multi-levels of parallel processing optimizations (see product launch press release August 14, 2017).

MRSI Systems is exhibiting at China International Optoelectronic Expo (CIOE) with our partner CYCAD Century Science and Technology (Booth #1C66) in Shenzhen, September 5-8, 2018 and ECOC (Booth #577) in Rome, Italy, September 24-26, 2018.

Soitec (Euronext Paris), a designer and manufacturer of semiconductor materials, and MBDA, announce the joint acquisition of Dolphin Integration.

Dolphin Integration is an industry recognized provider of semiconductor design, silicon IP and SoC (System-On-Chip) solutions for low power applications. Headquartered in Grenoble, Dolphin Integration was founded in 1985. It currently employs 155 people, including 130 design engineers. For the fiscal year ended March 31th, 2018, the company generated revenues of 17 million Euros.

The joint venture formed by Soitec and MBDA acquires Dolphin Integration, including all employees. The resulting ownership of the joint venture is as follows: Soitec at 60% and MBDA at 40%.

The transaction was authorized today by the Commercial Court of Grenoble. It comes as a prompt and positive outcome of Dolphin Integration insolvency proceedings. The company went into receivership on July 24, 2018.

Soitec and MBDA each provide complementary strategic support to Dolphin Integration.

Soitec brings its engineered substrates expertise and unique low-power design methodology (body biasing) to accelerate Dolphin Integration design activities in low-power electronic devices, where a growing number of critical chips are built on FD-SOI technology. In addition, Soitec will strengthen Dolphin Integration’s position within the entire semiconductor ecosystem, to develop and promote products and services in several strategic markets, including mobile devices and infrastructure, data centers, and space and industrial applications.

MBDA, a strategic customer of Dolphin Integration for defense applications since 2004, strengthens its existing industrial collaboration and long-term commercial pipeline for ASIC (Application Specific Integrated Circuit) and SoC (System on Chip) products. With the support of MBDA, Dolphin Integration will be able to advance its positions in aerospace and defense design.

Soitec and MBDA confident in Dolphin Integration profitable growth.

Soitec and MBDA together committed to a financial investment of around 6 million Euros including the acquisition of most of Dolphin Integration’s assets, the payment of certain liabilities and a significant cash injection to finance Dolphin Integration’s working capital requirements.

Soitec and MBDA are confident in their ability to turnaround the financial position of Dolphin Integration. Dolphin Integration is expected to be fully consolidated into Soitec’s financial statements as of September 2018.

“Dolphin Integration represents a strategic opportunity for Soitec to reinforce a full IP and service offering related to energy efficient solutions for chip design on FD-SOI. This is a major differentiating factor for FD-SOI and a key accelerator of FD-SOI adoption in major market segments,” highlighted Paul Boudre, CEO of Soitec.

“MBDA investment will strengthen the French defense industrial base since it will provide Dolphin Integration with a more stable flow of defense related revenues and a closer technological collaboration that will allow it to enhance the access of its specialized microelectronics offering to the entire French and European defense industry,” said Antoine Bouvier, CEO of MBDA.

Toshiba Electronic Devices & Storage Corporation (“Toshiba”) has launched a new series of next-generation 650V power MOSFETs that are intended for use in server power supplies in data centers, solar (PV) power conditioners, uninterruptible power systems (UPS) and other industrial applications.

The first device in the DTMOS VI series is the TK040N65Z, a 650V device that supports continuous drain currents (ID) up to 57A and 228A when pulsed (IDP). The new device offers an ultra-low drain-source on-resistance RDS(ON) of 0.04Ω (0.033Ω typ.) which reduces losses in power applications. The enhancement mode device is ideal for use in modern high-speed power supplies, due to the reduced capacitance in the design.

Power supply efficiency is improved as a result of reductions in the key performance index / figure-of-merit (FoM) – RDS(ON) x Qgd. The TK040N65Z shows a 40% improvement in this important metric over the previous DTMOS IV-H device, which represents a significant gain in power supply efficiency in the region of 0.36%[1] – as measured in a 2.5kW PFC circuit.

The new device is housed in an industry-standard TO-247 package, ensuring compatibility with legacy designs as well as suitability for new projects.

Toshiba will continue to expand their product lineup to meet market trends and help improve the efficiency of power supplies and systems.

The new device enters mass production today and shipments begin immediately.

The Trump administration’s consideration of tariffs on Chinese printed circuit assemblies and connected devices would cost the economy $520.8 million and $2.4 billion annually for the 10 percent and 25 percent tariffs, respectively, according to a new study commissioned by the Consumer Technology Association (CTA).

“With the economy thriving under President Trump – we’ve seen remarkably low unemployment and a booming stock market – the administration shouldn’t jeopardize America’s global standing with tariffs,” said Gary Shapiro, CEO and president, CTA. “Foreign governments don’t pay the cost of tariffs, Americans do – and for that reason, U.S. trade policy needs to steer clear of tariffs that act like taxes on American manufacturers and consumers. The danger we face – the unintended consequence – is that tariffs mean Americans will pay more for all the devices they use every day to access the internet.”

The economic impact study shows American shoppers will have to pay between $1.6 billion and $3.2 billion more for connected devices such as gateways, modems, routers, smart speakers, smartwatches and other Bluetooth enabled products. The price of connected devices from China will increase by between 8.5 and 22 percent. And prices for these products from all sources will rise between 3.2 and 6.2 percent.

Similarly, the price of printed circuit assemblies from China –– will increase by between nine and 23 percent, while an alternative supply from U.S. manufacturers will cost two to three percent higher. As a result of higher input costs, totaling an additional $900 million to $1.8 billion, American manufacturers of products that contain printed circuit assemblies will purchase between six and 12 percent less from suppliers overall.

“When our government begins to charge its own companies and people with more taxes in the form of tariffs, we have put in jeopardy not just the American Dream of many small and mid-size businesses, but you put in jeopardy the people that work for them too,” said Win Cramer, CEO, JLab Audio, a California based company and CTA member. “These people support a growing economy, support a growing business and, most importantly, pay taxes. Pre-tariffs, JLab Audio was planning to scale up with new hires and programs to push our company’s growth to another level, but now we’ve put all of that on hold as we need to see how everything shakes out.”

Based on CTA’s most recent U.S. Consumer Technology Sales and Forecasts report, if the administration enacts tariffs of 10 and 25 percent, CTA projects 2019 U.S. unit shipments of connected devices such as fitness trackers, smartwatches, wireless headphones, modems/broadband gateways, wireless earbuds and smart speakers would decline by as much as 12 percent. Also, U.S. shipment revenues for these devices would decrease by as much as 6.5 percent in 2019.

pSemi Corporation (formerly Peregrine Semiconductor), a Murata company focused on semiconductor integration, introduces the world’s first monolithic, silicon-on-insulator (SOI) Wi-Fi front-end module (FEM)—the PE561221. Ideal for Wi-Fi home gateways, routers and set-top boxes, this high-performance module uses a smart bias circuit to deliver a high linearity signal and excellent long-packet error vector magnitude (EVM) performance. The PE561221 combines the intelligent integration capabilities of pSemi’s SOI technology and Murata’s expertise in Wi-Fi connectivity solutions and advanced packaging. This 2.4 GHz Wi-Fi FEM integrates a low-noise amplifier (LNA), a power amplifier (PA) and two RF switches (SP4T, SP3T). The monolithic die uses a compact 16-pin, 2 x 2 mm LGA package ideal for either stand-alone use or in 4 x 4 MIMO and 8 x 8 MIMO modules.

“The new IEEE 802.11ax standard is utilizing high-order modulation schemes (1024 QAM) with demanding EVM requirements,” says Colin Hunt, vice president of worldwide sales at pSemi. “Traditional process technologies struggle to keep up with both performance and integration requirements, and only SOI can offer the ideal combination of integration and high performance. This new monolithic Wi-Fi module is a great example of the types of technology and product advancements pSemi and Murata can accomplish together.”

The 2.4 GHz Wi-Fi FEM is based on pSemi’s UltraCMOS® technology platform—a patented, advanced form of SOI. With its outstanding RF and microwave properties, SOI is an ideal substrate for integration. When paired with high-volume CMOS manufacturing—the most widely used semiconductor technology—the result is a reliable, repeatable technology platform that offers superior performance compared to other mixed-signal processes. UltraCMOS technology also enables intelligent integration—the unique design ability to integrate RF, digital and analog components on a single die.

Features, Packaging and Availability 

The PE561221 leverages the intelligent integration capabilities of UltraCMOS technology to deliver exceptional performance, low power consumption and high reliability with 2 kV HBM ESD rating. Through advanced analog and digital design techniques, the Wi-Fi FEM delivers excellent long-packet EVM performance with less than 0.1 dB of gain droop while operating across the entire -40°C to 85°C temperature range. At -40 dB EVM (MCS9), the output power is +19 dBm with less than 0.05 dBm droop in power output after a 4 milliseconds packet. The IC delivers best-in-class dynamic error vector magnitude (DEVM) and current consumption without requiring digital pre-distortion (DPD), and it has excellent MCS11 performance for 802.11ax applications.

Volume-production parts and samples of the PE561221 are available from pSemi. For sales information, please contact [email protected].

The PE561221 is the first product in the pSemi Wi-Fi FEM portfolio; the product roadmap includes 5 GHz Wi-Fi FEM solutions.

SEMI today announced that all legal requirements have been met for the ESD (Electronic Systems Design) Alliance to become a SEMI Strategic Association Partner.

Full integration of the Redwood City, California-based association representing the semiconductor design ecosystem is expected to be complete by the end of 2018. The integration will extend ESD Alliance’s global reach in the electronics manufacturing supply chain and strengthen engagement and collaboration between the semiconductor design and manufacturing communities worldwide.

As a SEMI Strategic Association Partner, the ESD Alliance will retain its own governance and continue its mission to represent and support companies in the semiconductor design ecosystem.

The ESD Alliance will lead its strategic goals and objectives as part of SEMI, leveraging SEMI’s robust global resources including seven regional offices, expositions and conferences, technology communities and activities in areas such as advocacy, international standards, environment, health and safety (EH&S) and market statistics.

With the integration, SEMI adds the design segment to its electronics manufacturing supply chain scope, connecting the full ecosystem. The integration is a key step in streamlining SEMI members’ collaboration and connection with the electronic system design, IP and fabless communities. The Strategic Association Partnership will also enhance collaboration and innovation across the collective SEMI membership as ESD Alliance members bring key capabilities to SEMI’s vertical application platforms such as Smart Transportation, Smart Manufacturing and Smart Data as well as applications including AI and Machine Learning.

“The addition of ESD Alliance as a SEMI Strategic Association Partner is a milestone in our mission to drive new efficiencies across the full global electronics design and manufacturing supply chain for greater collaboration and innovation,” said Ajit Manocha, president and CEO of SEMI. “This partnership provides opportunities for all SEMI members for accelerated growth and new business opportunities in end-market applications. We welcome ESD Alliance members to the SEMI family.”

“Our members are excited about becoming part of SEMI’s broad community that spans the electronics manufacturing supply chain,” said Bob Smith, executive director of the ESD Alliance. “Global collaboration between design and manufacturing is a requirement for success with today’s complex electronic products. Our new role at SEMI will help develop and strengthen the connections between the design and manufacturing communities.”

All ESD Alliance member companies, including global leaders ARM, Cadence, Mentor, a Siemens business, and Synopsys, will join SEMI’s global membership of more than 2,000 companies while retaining ESD Alliance’s distinct self-governed community within SEMI.