Category Archives: Packaging

Texas Instruments Incorporated (TI) (NASDAQ: TXN) today announced the resignation of Brian Crutcher as president, CEO and a member of the TI board. The board has named Rich Templeton, the company’s chairman, to reassume the roles of president and CEO on an ongoing, indefinite basis, in addition to continuing as chairman. Templeton’s appointment is not temporary, and the board is not searching for a replacement.

Crutcher resigned due to violations of the company’s code of conduct.  The violations are related to personal behavior that is not consistent with our ethics and core values, but not related to company strategy, operations or financial reporting.

“For decades, our company’s core values and code of conduct have been foundational to how we operate and behave, and we have no tolerance for violations of our code of conduct,” said Mark Blinn, lead director of the TI Board. “Over the past 14 years, Rich has successfully led TI to become the company it is today, and we have great confidence in his values and ability to continue to lead this company forward.”

“I have tremendous pride in this company, and passion for continuing to make TI even stronger and better,” said Rich Templeton, TI chairman, president and CEO. “I remain dedicated to moving TI forward with an unwavering commitment to operate ethically and conduct ourselves professionally in everything we do.”

TI also reported second-quarter revenue of $4.02 billion, up 9 percent from the same quarter a year ago, and earnings per share of $1.40. EPS included a 3 cent discrete tax benefit not in the company’s original guidance. TI will provide full second-quarter results and third-quarter guidance in its earnings release and conference call on July 24.

Amkor Technology, Inc. (Nasdaq: AMKR), a provider of outsourced semiconductor packaging and test (OSAT) services, today announced it has partnered with Mentor to release Amkor’s SmartPackage™ Package Assembly Design Kit (PADK), the first in the industry to support Mentor’s High-Density Advanced Packaging (HDAP) design process and tools. Amkor’s award-winning High-Density Fan Out (HDFO) process can now be used in conjunction with Mentor’s software to deliver early, rapid and accurate verification results of advanced packages required for Internet-of-Things, automotive, high-speed communications, computing and artificial intelligence applications.

“Amkor leads the way in HDFO technology for OSAT companies, and with the rise of complex ICs with multi-die packages, we prioritized the creation of Mentor-based PADKs to significantly reduce cycle time,” said Ron Huemoeller, corporate vice president, Research & Development, Amkor Technology. “Since the Mentor flow includes Calibre, the golden sign-off tool for the fabless ecosystem, our customers can easily close any physical verification issued for their entire solution.”

The complex and compact design of devices for today’s smart applications is driving the need for sophisticated packaging techniques such as heterogeneous integration and Advanced System-in-Package. These solutions combine one or more ICs of different functionality with increased I/O and circuit density in 2.5D (side-by-side) and 3D constructions. With Amkor’s SmartPackage PADK and Mentor’s proven HDAP tool flow, mutual customers of Amkor and Mentor have the ability to create and review multiple assemblies and LVS (layout vs. schematic), connectivity, geometry and component spacing scenarios using Amkor’s HDFO process. The graphic environment features robust data and is straightforward to use before and during the implementation of physical design, resulting in faster sign-off and fewer verification cycles.

“Amkor was the first OSAT company to join the Mentor OSAT Alliance program, and now the first to build and make available a PADK for its customers,” said AJ Incorvaia, vice president and general manager of Mentor’s BSD division. “By providing a fully validated PADK for Amkor’s HDFO process for Mentor’s proven HDAP tool flow, customers can more easily transition from classic chip design to 2.5 and 3D solutions.”

The OSAT Alliance program helps promote the adoption, implementation and growth of HDAP throughout the semiconductor ecosystem and design chain, enabling system and fabless semiconductor companies to have a friction-free path for emerging packaging technologies.

Micron (Nasdaq:MU) and Intel today announced an update to their 3D XPoint™ joint development partnership, which has resulted in the development of an entirely new class of non-volatile memory with dramatically lower latency and exponentially greater endurance than NAND memory.

The companies have agreed to complete joint development for the second generation of 3D XPoint technology, which is expected to occur in the first half of 2019. Technology development beyond the second generation of 3D XPoint technology will be pursued independently by the two companies in order to optimize the technology for their respective product and business needs.

The two companies will continue to manufacture memory based on 3D XPoint technology at the Intel-Micron Flash Technologies (IMFT) facility in Lehi, Utah.

“Micron has a strong track record of innovation with 40 years of world-leading expertise in memory technology development, and we will continue driving the next generations of 3D XPoint technology,” said Scott DeBoer, executive vice president of Technology Development at Micron. “We are excited about the products that we are developing based on this advanced technology which will allow our customers to take advantage of unique memory and storage capabilities. By developing 3D XPoint technology independently, Micron can better optimize the technology for our product roadmap while maximizing the benefits for our customers and shareholders.”

“Intel has developed a leadership position delivering a broad portfolio of Optane products across client and data center markets with strong support from our customers,” said Rob Crooke, senior vice president and general manager of Non-Volatile Memory Solutions Group at Intel Corporation. “Intel Optane’s direct connection to the world’s most advanced computing platforms is achieving breakthrough results in IT and consumer applications. We intend to build on this momentum and extend our leadership with Optane, which combined with our high-density 3D NAND technology, offer the best solutions for today’s computing and storage needs.”

Silicon Labs (NASDAQ: SLAB), a provider of silicon, software and solutions for a smarter, more connected world, announces two new executive appointments. Daniel Cooley has been named Senior Vice President and Chief Strategy Officer. In this new role, Mr. Cooley will focus on Silicon Labs’ overall growth strategy, business development, new technologies and emerging markets. Matt Johnson, a semiconductor veteran with more than 15 years of industry experience, joins Silicon Labs as Senior Vice President and General Manager of IoT products. Both executives will report to Tyson Tuttle, CEO.

Mr. Cooley has led Silicon Labs’ IoT business for the past four years. Under his leadership, the company built an industry-leading portfolio of secure connectivity solutions, with IoT revenue now exceeding a $100 million per quarter run rate. Mr. Cooley joined Silicon Labs in 2005 as a chip design engineer developing broadcast audio products and short-range wireless devices. Over the years, he has served in various senior management, engineering and product management roles at the company’s Shenzhen, Singapore, Oslo and Austin sites. The new role leverages Mr. Cooley’s proven talents in strategy and business development.

Mr. Johnson will lead Silicon Labs’ IoT business including the development and market success of the company’s broad portfolio of wireless products, microcontrollers, sensors, development tools and wireless software. Mr. Johnson has a track record of growing revenue and leading large global teams, and he brings a deep understanding of analog, MCU and embedded software businesses to Silicon Labs. Previously, he served as Senior Vice President and General Manager of automotive processing products and software development at NXP Semiconductors/Freescale, as well as SVP and General Manager of mobile solutions at Fairchild Semiconductor.

“With these executive appointments, we are expanding our ability to execute on large and growing market opportunities in the IoT,” said Tyson Tuttle, CEO of Silicon Labs. “Together, these two talented leaders will help Silicon Labs scale the business to the next level and focus on future growth.”

Intel to acquire eASIC


July 16, 2018

The following is an opinion editorial provided by Dan McNamara of Intel Corporation.

Intel is competing to win in the largest-ever addressable market for silicon, which is being driven by the explosion of data and the need to process, analyze, store and share it. This dynamic is fueling demand for computing solutions of all kinds. Of course Intel is known for world-class CPUs, but today we offer a broader range of custom computing solutions to help customers tackle all kinds of workloads – in the cloud, over the network and at the edge. In recent years, Intel has expanded its products and introduced breakthrough innovations in memory, modems, purpose-built ASICs, vision processing units and field programmable gate arrays (FPGAs).

FPGAs are experiencing expanding adoption due to their versatility and real-time performance. These devices can be programmed anytime – even after equipment has been shipped to customers. FPGAs contain a mixture of logic, memory and digital signal processing blocks that can implement any desired function with extremely high throughput and very low latency. This makes FPGAs ideal for many critical cloud and edge applications, and Intel’s Programmable Solutions Group revenue has grown double digits as customers use FPGAs to accelerate artificial intelligence, among other applications.

Customers designing for high-performance, power-constrained applications in market segments like wireless, networking and the internet of things (IoT) sometimes begin deployments with FPGAs for fast time-to-market and flexibility. They then migrate to devices called structured ASICs, which can be used to optimize performance and power-efficiency. A structured ASIC is an intermediary technology between FPGAs and ASICs. It offers performance and power-efficiency closer to a standard-cell ASIC, but with the faster design time and at a fraction of the non-recurring engineering costs associated with ASICs.

Today, I’m excited to announce that Intel plans to expand its programmable solutions portfolio to include structured ASICs by acquiring eASIC®, a leading structured ASICs provider headquartered in Santa Clara, California. eASIC has a proven, 19-year success record, leading products and a world-class team, which will join Intel’s Programmable Solutions Group. The addition of eASIC will help us meet customers’ diverse needs of time-to-market, features, performance, cost, power and product life cycles.

This combination brings together the best-in-class technologies from both companies to provide customers with more choice, faster time-to-market and lower development costs. Specifically, having a structured ASICs offering will help us better address high-performance and power-constrained applications that we see many of our customers challenged with in market segments like 4G and 5G wireless, networking and IoT. We can also provide a low-cost, automated conversion process from FPGAs (including competing FPGAs) to structured ASICs.

Longer term, we see an opportunity to architect a new class of programmable chip that takes advantage of Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology to combine Intel FPGAs with structured ASICs in a system in package solution. Together with partners and customers, Intel and eASIC expect to deliver industry-leading solutions.

We expect to complete the acquisition in the third quarter of 2018 after customary closing conditions are met. We look forward to serving eASIC’s current customers and to offering Intel customers a new solution for unlocking the power of data.

Broadcom Inc. (NASDAQ: AVGO), a semiconductor device supplier to the wired, wireless, enterprise storage, and industrial end markets, and CA Technologies (NASDAQ: CA), one of the world’s leading providers of information technology (IT) management software and solutions, today announced that the companies have entered into a definitive agreement under which Broadcom has agreed to acquire CA to build one of the world’s leading infrastructure technology companies.

Under the terms of the agreement, which has been approved by the boards of directors of both companies, CA’s shareholders will receive $44.50 per share in cash. This represents a premium of approximately 20% to the closing price of CA common stock on July 11, 2018, the last trading day prior to the transaction announcement, and a premium of approximately 23% to CA’s volume-weighted average price (“VWAP”) for the last 30 trading days. The all-cash transaction represents an equity value of approximately $18.9 billion, and an enterprise value of approximately $18.4 billion.

Hock Tan, President and Chief Executive Officer of Broadcom, said, “This transaction represents an important building block as we create one of the world’s leading infrastructure technology companies. With its sizeable installed base of customers, CA is uniquely positioned across the growing and fragmented infrastructure software market, and its mainframe and enterprise software franchises will add to our portfolio of mission critical technology businesses. We intend to continue to strengthen these franchises to meet the growing demand for infrastructure software solutions.”

“We are excited to have reached this definitive agreement with Broadcom,” said Mike Gregoire, CA Technologies Chief Executive Officer. “This combination aligns our expertise in software with Broadcom’s leadership in the semiconductor industry. The benefits of this agreement extend to our shareholders who will receive a significant and immediate premium for their shares, as well as our employees who will join an organization that shares our values of innovation, collaboration and engineering excellence. We look forward to completing the transaction and ensuring a smooth transition.”

The transaction is expected to drive Broadcom’s long-term Adjusted EBITDA margins above 55% and be immediately accretive to Broadcom’s non-GAAP EPS. On a combined basis, Broadcom expects to have last twelve months non-GAAP revenues of approximately $23.9 billion and last twelve months non-GAAP Adjusted EBITDA of approximately $11.6 billion.

As a global leader in mainframe and enterprise software, CA’s solutions help organizations of all sizes develop, manage, and secure complex IT environments that increase productivity and enhance competitiveness. CA leverages its learnings and development expertise across its Mainframe and Enterprise Solutions businesses, resulting in cross enterprise, multi-platform support for customers. The majority of CA’s largest customers transact with CA across both its Mainframe and Enterprise Solutions portfolios. CA benefits from predictable and recurring revenues with the average duration of bookings exceeding three years. CA operates across 40 countries and currently holds more than 1,500 patents worldwide, with more than 950 patents pending.

Bruker Corporation today announced that it has acquired JPK Instruments AG (JPK), located in Berlin, Germany. In 2017, JPK Instruments had revenue of approximately 10 million Euro. JPK provides microscopy instrumentation for biomolecular and cellular imaging, as well as force measurements on single molecules, cells and tissues. JPK adds in-depth expertise in live-cell imaging, cellular mechanics, adhesion, and molecular force measurements, optical trapping, and biological stimulus-response characterization to Bruker. Financial details of the transaction were not disclosed.

Over the past five years, Bruker has developed a life science microscopy business that specializes in advanced technologies for neuroscience, live-cell imaging, and molecular imaging, which will be further augmented by JPK’s advanced technologies and applications. Bruker’s existing fluorescence microscopy techniques include performance-leading multiphoton microscopy, swept-field confocal microscopy, super-resolution microscopy, and single-plane illumination microscopy.

“We have been making a substantial investment in advanced technologies for life science imaging, and have built up a portfolio of fluorescence microscopy products that enable biologists in research areas that require deep, fast imaging at high resolution and at low phototoxicity,” commented Dr. Mark R. Munch, President of the Bruker NANO Group. “JPK’s products and applications capabilities nicely augment our current techniques.”

Anthony Finbow, Chairman at JPK, added: “The combination of these two businesses will enable further significant advances in life science imaging and drive the state of the industry. I am delighted that we have been able to achieve this result for JPK and for Bruker.”

“The business we have built aligns well with the new strategic direction of Bruker in life science microscopy, and we are very pleased to join them,” said Dr. Torsten Jaehnke, a JPK founder and CTO. “We plan to realize a number of valuable synergies going forward.”

JPK’s BioAFM and optical tweezer product families span a range of techniques, from imaging of biological samples to characterizing biomolecular and cellular force interactions. Its NanoWizard 4 BioScience AFM combines atomic force imaging with advanced optical fluorescence imaging and super-resolution microscopy for the ultimate combination in image resolution for molecules, membranes, and live cells. In addition, the ForceRobot enables single-molecule force spectroscopy for investigating receptor-ligand interactions or small molecule-protein binding interactions. The CellHesion product brings quantitative force measurement to live cells and tissues, enabling insights in cell-substrate and cell-cell interactions. Lastly, JPK’s NanoTracker optical tweezer provides an all-optical means for molecular and cellular force experiments.

JPK’s offerings and life science applications expertise are synergistic with Bruker’s existing portfolio of advanced fluorescence microscopy products. Bruker’s Ultima family of multiphoton microscopes features proprietary photoactivation and photostimulation capabilities and deeper penetration into biological tissues, enabling advanced brain slice and intra-vital studies. Bruker’s Opterra swept-field scanning confocal fluorescence microscope provides unique live-cell imaging capabilities with unsurpassed dynamic observation of fast cellular events. Additionally, the Vutara super-resolution single-molecule localization (SML) microscope utilizes patented Biplane Imaging technology to provide high-speed, 3D super resolution for multicolor live-cell imaging and visualization of chromosome conformation. With a leading series of single plane illumination products, such as the MuVi SPIM and InVi SPIM, Bruker offers unique performance and easiest-to-use light sheet instruments featuring the combination of low phototoxicity and high-speed imaging. The combined microscopy portfolio of the two companies will enable a unique range of correlative measurements for emerging life science applications.

IC Insights will release its 200+ page Mid-Year Update to the 2018 McClean Report later this month. The Mid-Year Update revises IC Insights’ worldwide economic and IC industry forecasts through 2022 that were originally published in The 2018 McClean Report issued in January of this year.

Figure 1 compares the estimated required capex needed to increase NAND flash bit volume shipments 40% per year, sourced from a chart from Micron’s 2018 Analyst and Investor Event in May of this year, versus the annual capex targeting the NAND flash market segment using IC Insights’ data. As shown, Micron believes that the industry capex needed to increase NAND flash bit volume production by 40% more than doubled from $9 billion in 2015 to $22 billion only two years later in 2017! This tremendous surge in required capital was driven by the move to 3D NAND from planar NAND since 3D NAND requires much more fab equipment and additional cleanroom space to process the additional layers of the device as compared to planar NAND.

Most of the five major NAND flash suppliers have stated that they believe that NAND bit volume demand growth will average about 40% per year over the next few years. Figure 1 shows that the capex needed to support a 40% increase in NAND bit volume shipments was exceeded by 27% last year and is forecast to exceed the amount needed by another 41% this year (NAND bit volume shipments increased 41% in 2017 but 1H18/1H17 bit volume shipments were up only 30%). As a result, it is no surprise that NAND flash prices have already softened in early 2018. Moreover, the pace of the softening is expected to pick up in the second half of this year and continue into 2019.

Historical precedent in the memory market shows that too much spending usually leads to overcapacity and subsequent pricing weakness. With Samsung, SK Hynix, Micron, Intel, Toshiba/Western Digital/SanDisk, and XMC/Yangtze River Storage Technology all planning to significantly ramp up 3D NAND flash capacity over the next couple of years (with additional new Chinese producers possibly entering the market), IC Insights believes that the risk for significantly overshooting 3D NAND flash market demand is very high and growing.

Figure 1

By Ed Korczynski

As the commercial IC fabrication industry continues to shrink field-effect transistor (FET) sizes, 2D planar structures evolved into 3D fins which are now evolving into 3D stacks of 2D nano-sheets. While some researchers continue to work on integrating non-silicon “alternate channel” materials into finFETs for next generation logic ICs, published results from labs around the world now show that nano-wires or nano-sheets of silicon will likely follow silicon finFETs in high-volume manufacturing (HVM) fabs. 

Today’s finFETs are formed using self-aligned multi-patterning (SAMP) process flows with argon-fluoride immersion (ArFi) deep ultra-violet (DUV) steppers to provide arrays of equal-width lines. A block-mask can then pattern sets of lines into different numbers of fins per transistor to allow for different maximum current flows across the chip. When considering the next CMOS device structure to replace finFETs in commercial HVM we must anticipate the need to retain different current flows (ION) across the IC.

Gate-all-around (GAA) FETs can provide outstanding ION/IOFFratios, and future logic ICs could be built using either horizontal or vertical GAA devices. While vertical-GAA transistors have been explored for memory chips, their manufacturing process flows are significantly different from  those used to form finFETs. In contrast, horizontal-GAA FETs processing can be seen as a logical extension of flows already developed and refined for fin structuring.

“With a number of scaling boosters, the industry will be able to extend finFET technology to the 7 or even 5nm node,” said An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the finFET process steps.”

The figure shows simplified cross-sections of a finFET with fin height (FH) of 50 nm along with two different stacks of lateral nano-sheets (LNS, also known as horizontal nano-sheets or HNS), where the current flows would be normal to the cross-section. HNS are variations of horizontal nano-wires (HNW) with the wires widened, shown as 11nm and 21nm in the figure. The HNS are epitaxial-silicon grown separated by sacrificial sacrificial silicon-germanium (SiGe) spacer layers.

Cross-sectional schematics of idealized (left) 50nm high finFET, (center) 5nm high by 11nm wide lateral-nano-sheets at 12-18nm vertical pitch, and (right) lateral-nano-sheets 21nm wide. (Source: imec)

In an exclusive interview with Solid State Technology, Steegen discussed a few details of the process extensions needed to convert finFETs into HNS-FETs. The same work-function ALD metals can be used to tune threshold voltages such that one epi-stack process can grow silicon for both n-type and p-type FETs. Happily, no new epitaxial reactors nor precursor materials are needed. Isotropic etch of the SiGe vertical spacers, and then filling the spaces with a dielectric deposition may be the only new unit-processes needed.

Alternate channel wires and sheets

At the 2018 Symposia on VLSI Technology and Circuits, imec presented two papers on germanium as an alternate channel material for nanowire pFET devices. In the first paper they studied the electrical properties of strained germanium nanowire pFETs as high-end analog and high-performance digital solutions. The second paper demonstrated vertically-stacked GAA highly-strained germanium nanowire pFETs.

The commercial IC fab industry has considered use of alternate channels for planar devices and for finFETs, yet so far has found extensions of silicon to work well-enough for pFETs. Likewise, the first generation of HNS will likely use silicon channels for both nFETs and pFETs. Germanium GAA pFETs thus represent the ability to shrink HNS devices for future nodes.

Intel has won SEMI’s 2018 Award for the Americas. SEMI honored the celebrated chipmaker for pioneering process and integration breakthroughs that enabled the first high-volume Integrated Silicon Photonics Transceiver. The award was presented yesterday at SEMICON West 2018.

SEMI’s Americas Awards recognize technology developments with a major impact on the semiconductor industry and the world.

The Intel® Silicon Photonics 100G CWDM4 (Coarse Wavelength Division Multiplexing 4-lane) QSFP28 optical transceiver, a highly integrated optical connectivity solution, combines the power of optics and the scalability of silicon. The small form-factor, high-speed, low-power consumption 100G optical transceivers are used in optical interconnects for data communications applications, including large-scale cloud and data centers, and in Ethernet switch, router, and client telecommunications interfaces.

Dr. Thomas Liljeberg, senior director of R&D for Intel Silicon Photonics, accepted the award on behalf of Intel. Dr. Liljeberg is one of the technologists responsible for bringing Intel’s silicon photonics 100G transceivers to high-volume production.

“Every year SEMI honors key technological contributions and industry leadership through the SEMI Award,” said David Anderson, president, SEMI Americas. “Intel was instrumental in delivering technologies that will influence product design and system architecture for many years to come. Congratulations to Intel for this significant accomplishment.”

“The 2018 Award recognizes the enablement of high-volume manufacturing through technology leadership and collaboration with key vendors in the supply chain,” said Bill Bottoms, chairman of the SEMI Awards Advisory Committee. “Intel’s collaboration is a model for how the industry can accelerate innovation in the future.”

SEMI established the SEMI Award in 1979 to recognize outstanding technical achievement and meritorious contributions in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The SEMI Americas award is the highest honor conferred by the SEMI Americas region. It is open to individuals or teams from industry or academia whose specific accomplishments have a broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of North American-based member companies of SEMI. For a list of past award recipients, visit www.semi.org/semiaward.