Category Archives: Packaging

By Emmy Yi, SEMI Taiwan Marketing

Emboldened by advances in self-driving and Internet of Vehicles (IoV) technologies, Taiwan’s microelectronics sector is investing heavily in manufacturing processes and equipment as engines of innovation and growth for autonomous driving, the world’s next market goldmine. But breaking into the self-driving vehicle industry can be an uphill struggle. Semiconductor players bent on securing their piece of the potentially massive market must know how to navigate the automotive industry’s unique ecosystem of suppliers, not to mention its lofty standards for safety and reliability.

To explore opportunities and challenges in the automotive semiconductor market, SEMI recently organized Mobility Tech Talk – a gathering of invited professionals from Strategy Analysis, Yole Développement, Renesas, X-FAB and IHS Markit to examine the evolution of sensors for autonomous cars, advanced driver-assisted system (ADAS) applications, and new energy vehicles (NEVs) in China. Nearly 200 participants exchanged in-depth, forward-looking insights and perspectives as the event successfully reinforced connections among different segments. Here are four key takeaways from the event.

Lidar: The hottest sensing technology for smart automotive

Lidar, mmWave radar, cameras and inertial measurement units (IMUs) are the most important sensing devices for autonomous cars. As sensor and high-speed computing technologies mature, 2018 may mark the beginning for an era of autonomous cars, with 350,000 self-driving vehicles expected to hit the road by 2027. But before a single car takes to the roadways, self-driving technology must become expert at monitoring a vehicle’s environment.

That’s where Lidar, the hottest of all sensing technologies and the key to the holy grail of safe self-driving, comes into the picture. Lidar’s versatility supports multiple essential functions such as mapping, object detection and object movement, but mass production is still impossible due to its high cost. What’s more, technical issues must still be sorted out with solid-state lidar, mechanical lidar and MEMS. Both startups and traditional tier-1 semiconductor players have aggressively invested in related research and development, all hoping to pre-position themselves for the new opportunity.

Smart automotive sets new quality and safety standards

As cars become smarter, so too must silicon. Chips must support vastly more data generated by in-vehicle connectivity, ADAS, electrification, autonomous driving and a multitude of other functions that rely on advanced automotive electronics components. Demand for smarter silicon is prompting Taiwan companies to directly tap the automotive chip market or serve as OEMs for major automakers.

With quality and safety top priorities for automotive applications, in-vehicle semiconductors must meet strict requirements across areas including vehicle control, robustness, liability, cost and quality management to conform to the automotive specifications necessary to securing certifications. Smart silicon must also pass all AEC-Q liability standards promoted by automakers in North America, and score “zero defect” for the ISO/TS 16949 Automotive Quality Management System.

China’s new energy vehicles to fuel semiconductor growth

To promote NEVs and thus reduce fuel consumption by cars with internal combustion engines (ICEs), late last year the Chinese government introduced the Measures for the Parallel Administration of the Average Fuel Consumption and New Energy Vehicle Credits of Passenger Vehicle Enterprises. With China the world’s largest market for NEVs, the policy is forcing automakers in Japan, the U.S. and Europe to accelerate moves towards NEVs that, in turn, will fuel growth in the semiconductor and automotive battery industries. NEVs in China are expected to number 2 million by 2020 before more than doubling to 4.9 million by 2025. Today, most cars still run on ICEs as environmentally friendly motor drives are still under development. In unit shipments, motor drives are expected to exceed ICEs by 2025.

Cross-field collaboration is the key

The rise of smarter, fully autonomous vehicles – a disruptive “Car 2.0” – is unlikely to happen overnight. The global automotive semiconductor market will continue rapid growth, with safety and powertrain applications driving the strongest chip demand. Meanwhile, automakers are focusing more on innovations from startups and non-traditional suppliers, and some have even started developing their own IP and solutions. These paradigm industry shifts are diversifying the automotive supply chain into a cross-domain collaborative network of suppliers, pushing the closed, one-way automotive supply chain into lesser relevance. In the near future, rivals and partners may become indistinguishable as traditional turf wars begin to wane.

As ADAS and autonomous cars evolve, and the era of electric cars nears, automotive semiconductors are rising as the engine of growth for the global semiconductor industry. The automotive semiconductor market is expected to grow at a CAGR of 5.8 percent, reaching US$48.78 billion by 2022.

To help the semiconductor and automotive industries thrive in the era of self-driving vehicles, SEMI has established the Smart Automotive special interest group, a platform for better connecting elite professionals from the microelectronics and automotive sectors. Focusing on trends and innovation in the global autonomous semiconductor industry, the SEMI Smart Automotive SIG promotes industry development and cross-domain collaboration so members can create more business opportunities.

Originally published on the SEMI blog.

To meet growing market demand for high-density 2.5D and 3D stacked semiconductor solutions, Silicon Valley-based ALLVIA, Inc. has expanded its in-house capabilities to include the formation of through-quartz vias (TQV) ranging from 15 microns in diameter and 100 microns deep to 50 microns in diameter and 250 microns deep. ALLVIA’s new TQV solution significantly improves the performance of 3D-ICs by creating IC interconnects with lower parasitic capacitance than can be achieved with the earlier generation of through-silicon via (TSV) technology.

he company had been outsourcing the production of via holes in the fused silica (quartz) that it uses, but its newly added capability brings all via-drilling operations in-house, expanding ALLVIA’s intellectual property and reducing the cost of production. The company will continue to apply its proprietary technology to fill the high-aspect-ratio via holes with copper plating to fabricate finished interposer products.

Sergey Savastiouk, CEO of ALLVIA, said, “Performing our own via drilling in fused silica allows us to improve turnaround times and production volumes for our customers while also delivering better quality using our state-of-the-art technology for copper plating, chemical mechanical polishing and deep via thin-film deposition.”

In addition to providing via foundry services, ALLVIA applies its technology in manufacturing and selling ultra-thin quartz interposers that form the electrical connections between a silicon chip and a printed circuit board.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has started construction work for the next expansion phase of its corporate headquarters. The new building will house EVG’s “Manufacturing III” facility, which will more than double the floor space for the final assembly of EVG’s systems.

“With our innovative manufacturing solutions for the high-tech industry as well as new biomedical applications, we operate in very dynamic markets with great future prospects,” stated Dr. Werner Thallner, executive operations and financial director at EV Group. “In light of the high capacity utilization in all areas of our existing facilities, as well as the positive market outlook, we decided to implement our plans for building our Manufacturing III facility this year. This will support our long-term growth targets at our corporate headquarters in St. Florian am Inn.”

EVG Manufacturing III Photo 1

The new Manufacturing III building, adjacent to the new test room site that was opened just a few months ago, will be built next to the river Inn. The ultramodern building will provide approximately 4,800 square meters of additional space in total, which will benefit not only manufacturing but other departments as well. In addition to an expansion of warehouse space, a new delivery area with a dedicated packaging site designed for cleanroom equipment will be created, along with an airfreight security zone and new truck loading docks for the shipment of the completed systems to EVG’s worldwide customers.

The construction of the new Manufacturing III building is set to be completed in early 2019.

TowerJazz today announced the release of its 300mm 65nm BCD (Bipolar-CMOS-DMOS) process, the most advanced power management platform for up to 16V operation and 24V maximum voltage.  This technology is manufactured in TowerJazz’s Uozu, Japan facility, with best-in-class quality and cycle time, and is based on the Company’s 300mm 65nm automotive qualified flows.

This platform provides significant material competitive advantages for any type of power management chip up to 16V regardless of application, including a wide variety of products such as: PMICs, load switches, DC-DC converters, LED drivers, motor drivers, battery management, analog and digital controllers, and more. IHS Markit Power IC Analyst, Kevin Anderson forecasts a $9.4 billion available market, which this technology addresses, in 2018 with continual growth.

TowerJazz’s 65nm BCD process is leading this low voltage market segment with the highest power efficiency, very small die size, best digital integration capability; and superior cost effectiveness through both the smallest aerial footprint and the lowest mask count.

The process includes four leading edge power LDMOS transistors: 5V, 7V, 12V and 16V operation, each with the best available Rdson and Qgd parameters. In addition to the new aforementioned cost and figure of merit benchmarks, multiple chips can be integrated to a single monolithic IC solution replacing a multiple chip module for an improved system cost structure and system performance.

TowerJazz’s power transistors are fully isolated to withstand high currents, all with an ultra-low Rdson, e.g. less than 1mΩ*mm² for the 5V LDMOS. For products which operate at the megahertz (MHz) switching frequencies, the 65nm BCD power transistors benefit from a very low Qgd down to 2.6mΩ*nC. In addition, very low metal resistance is achieved using a single or dual 3.3um top thick copper. The 65nm BCD also offers aggressive 113Kgate/mm² 5V digital density and an 800Kgate/mm² 1.2V digital library.

“This new 65nm BCD platform establishes TowerJazz as a technology leader in the related growing markets for up to 16V power applications,” said Shimon Greenberg, Vice President and General Manager of Power Management & Mixed-Signal/CMOS Business Unit, TowerJazz. “Best addressing the vast low voltage power management market segment, we are experiencing very high interest from early adopter customers and plan a mass production ramp by the fourth quarter of 2018.”

TowerJazz will be exhibiting at ISPSD, the 30th IEEE International Symposium on Power Semiconductor Devices and ICs on May 13-17, 2018 in Chicago, USA.

Mentor, a Siemens business, has announced that several tools in its Calibre® nmPlatform and Analog FastSPICE (AFS™) Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes. Mentor also announced it has updated its Calibre nmPlatform tools in support of TSMC’s Wafer-on-Wafer (WoW) stacking technology. These Mentor tools and TSMC’s new processes will enable mutual customers to more quickly deliver silicon innovations in high-growth markets.

“Mentor continues to increase its value to the TSMC ecosystem by offering more features and solutions in support of our most advanced processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By continuing to innovate leading-edge electronic design automation (EDA) technologies for our new processes, Mentor is again proving its commitment to TSMC and our mutual customers.”

Mentor’s enhanced tools for TSMC 5nm FinFET and 7nm FinFET Plus processes

Mentor worked closely with TSMC to certify various tools in Mentor’s Calibre nmPlatform – including Calibre nmDRC™, Calibre nmLVS™, Calibre PERC™, Calibre YieldEnhancer, and Calibre xACT™ – for TSMC’s 5nm FinFET and 7nm FinFET Plus processes. These Calibre solutions now have new measurements and checks including, but not limited to, supporting extreme ultraviolet (EUV) lithography requirements jointly defined with TSMC. Mentor’s Calibre nmPlatform team is also working with TSMC to address physical verification runtime performance by enhancing scalability of multi-CPU runs to improve productivity. Mentor’s AFS platform, including the AFS Mega circuit simulator, is also now certified for TSMC’s 5nm FinFET and 7nm FinFET Plus processes.

Mentor’s enhanced tools for TSMC’s WoW stacking technology

Mentor made enhancements to its Calibre nmPlatform tools in support of the WoW packaging. Enhancements include DRC and LVS signoff for dice with backside through-silicon vias (BTSV), interface alignment and connectivity checks for die-to-die as well as die-to-package stacking. Further enhancements include parasitic extraction on backside routing layers, interposers with through-silicon vias (TSVs), and interface coupling.

Calibre Pattern Matching for TSMC’s 7nm SRAM Array Examination Utility

Mentor worked closely with TSMC to integrate Calibre Pattern Matching into TSMC’s 7nm SRAM Array Examination Utility. This flow helps customers to ensure their SRAM implementations are constructed to meet process requirements. This automation enables customers to tape out successfully. The SRAM Array Examination Utility is available to TSMC’s customers for 7nm production.

“TSMC continues to develop innovative silicon processes that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor, a Siemens business. “We, at Mentor, are proud to not only lead the way in certifying our platforms for TSMC’s latest processes, we are also proud of our close partnership with TSMC in developing new technologies that help customers achieve production silicon faster.”

To learn more, visit Mentor at booth #408 at TSMC’s Technology Symposium on May 1, 2018 at the Santa Clara Convention Center in Santa Clara, California.

 

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms. The Cadence® digital, signoff and custom/analog tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the TSMC 5nm and 7nm+ processes. The corresponding process design kits (PDKs) are now available for download.

5nm and 7nm+ Digital and Signoff Tool Certification

Cadence provides a fully integrated digital flow from implementation to final signoff that has been certified by TSMC for the latest versions of the 5nm and 7nm+ processes. For the 7nm+ process, the Cadence full-flow includes the Innovus™ Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS) and Layout-Dependent Effect (LDE) Electrical Analyzer. For the 5nm process, the Cadence certified tools include the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, the layout vs. schematic (LVS) function in PVS and LDE Electrical Analyzer.

Cadence digital and signoff features available for the 7nm process are also available for the 5nm and 7nm+ process. Some of these features include cut-metal handling throughout the design flow, via-pillar support, clock mesh and bus-routing. These capabilities can enable customers to successfully design mobile and HPC systems with improved power, performance and area (PPA) while reducing iterations and achieving their cost and performance objectives.

In addition, Cadence has delivered new enhancements focused on EUV support at key layers and associated new design rules that specifically support the 5nm and 7nm+ processes. Some of the other newest enhancements for the 7nm+ process include cell pin support, Self-Heating Effect (SHE) and heatsink support.

Specifically for the 5nm process, Cadence digital and signoff tools offer high-resistance resistor support, router compliance for new rules and new extraction support including additional resistor layer modeling and other middle end-of-line (MEOL) features.

5nm and 7nm+ Custom/Analog Tool Certification

The certified custom/analog tools include the Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF, and Spectre Circuit Simulation, as well as the Virtuoso® product suite, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment.

By using the latest capabilities and design methodologies included with the Virtuoso Advanced-Node Platform, customers can achieve an improvement in custom physical design throughput versus traditional non-structured design methodologies, while maintaining a similar effort and cycle time via the advanced capabilities in the Virtuoso and Spectre tools.

Cadence delivered several custom/analog enhancements specifically to support the TSMC 5nm and 7nm+ process technologies. For example, Cadence introduced an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet their power, multiple patterning, density and EM requirements. In addition, Cadence introduced universal poly grid snapping, asymmetric coloring support and voltage-dependent rule support for power/ground rails specifically for the 5nm process.

5nm and 7nm+ Library Characterization Tool Flow

The Virtuoso Liberate™ Characterization Solution and the Virtuoso Variety™ Statistical Characterization Solution have been validated to deliver Liberty libraries including advanced timing, noise and power models. The solutions utilized innovative methods to characterize Liberty Variation Format (LVF) models, enabling accurate process variation signoff for low-voltage applications and the ability to create EM models enabling signal EM optimizations and signoff.

“Using the latest design rules and PDKs, our customers have started designing complex SoCs on our most advanced process technologies,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Through the continuation of our collaboration with Cadence, we’ve certified their tools and flows for 5nm and 7nm+ designs, which can enable our customers to achieve their design goals within a fast, predictable timeline.”

“Over the past few years, Cadence has taken on a broader role in facilitating advanced-node adoption due to the optimizations and performance improvements across our digital and signoff and custom/analog tool suites,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “We’ve expanded our collaboration with TSMC by developing tools and flows that support their 5nm and 7nm+ process technologies, and our latest TSMC certifications are enabling us to support customers using the most advanced process nodes.”

Synopsys, Inc. (Nasdaq: SNPS) today announced certification of the Synopsys Design Platform with TSMC’s latest Design Rule Manual (DRM) for advanced 7-nanometer (nm) FinFET Plus process technology. With several test chips taped out and production designs currently under development by multiple customers, this certification by TSMC enables a wide range of designs from high-performance computing and high-density to low-power mobile applications using the Synopsys Design Platform.

This certification is a milestone for TSMC’s extreme ultraviolet lithography (EUV) process that enables significant area savings while maintaining high performance when compared to non-EUV process nodes.

The Synopsys Design Platform, anchored by Design Compiler Graphical synthesis and IC Compiler™ II place-and-route tools, has been enhanced to take full advantage of TSMC’s 7-nm FinFET Plus for high-performance designs. Design Compiler Graphical is capable of automatically inserting via pillar structures to boost performance and prevent signal electromigration (EM) violations, and can pass the information to IC Compiler II for further optimization. It also automatically applies non-default rules (NDR) during synthesis and performs layer-aware optimization to improve design performance. These optimizations, including IC Compiler II bus routing, continue throughout the place-and-route flow to meet stringent delay-matching requirements of high-speed network.

PrimeTime® timing analysis advanced waveform propagation (AWP) and parametric on-chip variation (POCV) technologies have been optimized to address increased waveform distortion and non-Gaussian variation effects of higher performance and lower voltage operation. In addition, PrimeTime’s physically-aware signoff has been expanded to support via-pillars.

Synopsys has enhanced the Design Platform to perform physical implementation, parasitic extraction, physical verification, and timing analysis to support TSMC’s WoW technology. The physical implementation flow with IC Compiler II provides full support for wafer staking designs, from initial die floorplan preparation to placement and assignment of bumps to implementation of die routing. Verification is done by IC Validator for DRC/LVS checks, and Synopsys’ StarRC tool performs parasitic extraction.

“Ongoing collaboration with Synopsys and early customer engagements on TSMC’s 7-nanometer FinFET Plus process technology are delivering differentiated platform solutions that help our mutual customers bring innovative new products to market faster,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “Certification of the Synopsys Design Platform enables our mutual customers’ designs in our first mass-production, EUV-enabled technology.”

“Our collaboration with TSMC on their mass-production 7-nanometer FinFET Plus process allows companies to confidently begin designing their increasingly large SoC and multi-die chips with the highly-differentiated Synopsys Design Platform,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “Certification on TSMC’s 7-nanometer FinFET Plus process enables our customers to benefit from significant power, performance, and area improvements of an advanced EUV process, while accelerating time-to-market for their differentiated products.”

Spin Transfer Technologies, Inc., the developer of advanced STT-MRAM for embedded SRAM and stand-alone DRAM applications, today announced results of its unique Precessional Spin Current (PSC™) structure. The results from advanced testing of the PSC structure confirm that it will increase the spin-torque efficiency of any MRAM device by 40-70 percent — enabling dramatically higher data retention while consuming less power. This gain translates to retention times lengthening by a factor of over 10,000 (e.g., 1 hour retention becomes more than 1 year retention) while reducing write current. Improved efficiency is critical for enabling MRAM to replace SRAM and DRAM in mobile, datacenter and AI applications, as well as for improving retention and performance in high-temperature automotive applications. The company reported these results at the prestigious Intermag 2018 Conference.

Spin-torque efficiency is one of the core performance metrics of the pMTJ (perpendicular magnetic tunnel junction — the “bit” that stores the memory state in an MRAM memory) and is defined by the ratio between the thermal retention barrier, measuring how long data can be reliably stored in the memory, and the switching current necessary to change the value of the bit. In previous MRAM implementations, increasing the energy barrier to increase retention would require a proportional increase in write current — leading to higher power consumption and much faster wear-out of the pMTJ devices (lower endurance). The PSC structure is a breakthrough because it effectively decouples the static energy barrier that determines retention from the dynamic switching processes that govern the switching current. As a result, when the PSC structure is added to any pMTJ, benefits include:

  • A higher energy barrier when the pMTJ does not have current flowing through it, which is ideal for retaining data for long periods
  • An increased spin polarization when current is flowing and the device is writing a new state, which is ideal for minimizing switching current and extending the life of the device by many orders of magnitude

The PSC structure was designed from the outset to be modular and fabricated with any pMTJ — either the company’s own pMTJs, or a pMTJ from other sources. The PSC structure is fabricated during the pMTJ deposition process and adds approximately 4nm to the height of the pMTJ stack. The structure is compatible with a wide range of standard MRAM manufacturing processes, materials and tool sets — enabling any foundry to readily incorporate the PSC structure into existing pMTJ stacks without adding significant complexity or manufacturing costs.

“MRAM is attracting a lot of attention as an embedded memory for ASICs and MCUs, but issues of write current and data retention have caused concern,” said Jim Handy, general director of Objective Analysis. “Spin Transfer Technologies’ new PSC structure shows a lot of promise to solve a number of those issues and pave the path for MRAM to take a significant share of the embedded memory market.”

Spin Transfer Technologies’ testing of the PSC structure involved comparing the performance of the same pMTJ devices with and without PSC for a large number of devices within CMOS test chip arrays at various temperatures and device diameters. The tests exhibited a robust performance advantage due to the PSC structure, both during writing of the low-resistance (“0”) and the high-resistance (“1”) memory states. Some specific examples of the advantages that the data have shown are as follows:

  • Increase of the spin-torque efficiency by up to 70 percent
  • Demonstration of the efficiency gain across a range of sizes (40-60nm) and temperatures (30°C to 125°C)
  • Increase of the thermal energy barriers by 50 percent corresponding to an increase in data retention time of greater than four orders of magnitude while reducing the switching current
  • Reduction of read disturb error rate up to five orders of magnitude

These advantages have come without degradation to other performance parameters. The data for the PSC structure indicate significant potential for enabling high-speed applications as well as high-temperature automotive and other applications. Furthermore, since the data shows that the PSC structure’s efficiency gains actually increase as the pMTJ get smaller, the PSC structure opens new pathways to achieving embedded SRAMs in the latest 7nm and 5nm generations.

“There is a huge demand for a memory with the endurance of SRAM, but with higher density, lower operating power and with non-volatility. We believe the improvements the PSC structure brings to STT-MRAM technology will make it a highly attractive alternative to SRAM for these reasons,” said Mustafa Pinarbasi, CTO and SVP of Magnetics Technology at Spin Transfer Technologies. “We are excited to enable the next generation of STT-MRAM and to shake up the status quo of the memory industry through our innovation.”

Samsung Electronics Co., Ltd. today announced that it has begun mass producing 10-nanometer (nm)-class* 16-gigabit (Gb) LPDDR4X DRAM for automobiles. The latest LPDDR4X features high performance and energy efficiency while significantly raising the thermal endurance level for automotive applications that often need to operate in extreme environments. The 10nm-class DRAM will also enable the industry’s fastest automotive DRAM-based LPDDR4X interface with the highest density.

“The 16Gb LPDDR4X DRAM is our most advanced automotive solution yet, offering global automakers outstanding reliability, endurance, speed, capacity and energy efficiency,” said Sewon Chun, senior vice president of memory marketing at Samsung Electronics. “Samsung will continue to closely collaborate with manufacturers developing diverse automotive systems, in delivering premium memory solutions anywhere.”

Moving a step beyond its 20nm-class ‘Automotive Grade 2’ DRAM, which can withstand temperatures from -40°C to 105°C, Samsung’s 16Gb LPDDR4X is Automotive Grade 1-compliant, raising the high-end threshold to 125°C. By more than satisfying the rigorous on-system thermal cycling tests of global auto manufacturers, the 16Gb LPDDR4X has enhanced its reliability for a wide variety of automotive applications in many of the world’s most challenging environments.

Adding to the degree of reliability under high temperatures, production at an advanced 10nm-class node is key to enabling the 16Gb LPDDR4X to deliver its leading-edge performance and power efficiency. Even in environments with extremely high temperatures of up to 125°C, its data processing speed comes in at 4,266 megabits per second (Mbps), a 14 percent increase from the 8Gb LPDDR4 DRAM that is based on 20nm process technology, and the new memory also registers a 30 percent increase in power efficiency.

Along with a 256 gigabyte (GB) embedded Universal Flash Storage (eUFS) drive announced in February, Samsung has expanded its advanced memory solution lineup for future automotive applications with the 10nm-class 16Gb LPDDR4X DRAM, commercially available in 12Gb, 16Gb, 24Gb and 32Gb capacities. While extending its 10nm-class DRAM offerings, the company also plans on bolstering technology partnerships for automotive solutions that include vision ADAS (Advanced Driver Assistance Systems), autonomous driving, infotainment systems and gateways.

Siemens Corporation today announced that Barbara Humpton has been appointed CEO for the United States, effective June 1, 2018. Humpton (57) is currently CEO of Siemens Government Technologies, Inc. (SGT), a Federally-compliant U.S. organization structured to help address national imperatives in energy, infrastructure, automation and marine platforms.

“Barbara has broad knowledge of Siemens’ entire portfolio that will serve us well as we continue to grow the U.S. business,” said Lisa Davis, CEO of Siemens Corporation and Americas Region and Member of the Siemens AG Managing Board.

Humpton joined Siemens Government Technologies in 2011 as Senior Vice President for Business Development and was appointed to lead the company’s approach to the federal market in 2015. Prior to joining Siemens, Humpton held senior leadership positions at Lockheed Martin and Booz Allen Hamilton, where she was a Vice President at both firms.

“I am honored to work with the 50,000 Siemens employees in the U.S. to address the market’s needs in electrification, automation and digitalization. It’s an exciting time to be at Siemens as we develop products and services that are shaping the future,” said Humpton.

Siemens has been in the U.S. for more than 160 years and has invested $35 billion in America in the last 15 years alone. With 50,000 U.S. employees and more than 60 manufacturing sites, Siemens in the U.S. is using its global leadership in engineering and technology innovation to meet America’s toughest challenges, delivering solutions for industry, hospitals, utilities, cities, and manufacturers: from efficient power generation, to digital factories and oil and gas fields, to medical diagnostics, to locomotives, to next-generation software used in every phase of product development.

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Siemens AG (Berlin and Munich) is a global technology powerhouse that has stood for engineering excellence, innovation, quality, reliability and internationality for 170 years.