Category Archives: Semicon West

Leti, a CEA Tech institute, today announced it has developed a new on-chip communications system to improve high-performance computing (HPC) that is faster and more energy efficient than current solutions and is compatible with 3D architectures.​

Leti researchers, working in the frame of IRT Nanoelec, boosted computing power and slashed energy consumption by stacking chips on top of each other in a single enclosure, or by placing the chips side by side on a silicon interposer. The chips, which have progressed from demonstrator to fabrication-ready, exchange data via a new communications network that is part of the network on chip (NoC) called 3D-NoC.

3D-NoC technology has been demonstrated with a homogeneous 3D circuit that is comprised of regular tiles assembled using a 4x4x2 NoC. It also features robust and fault-tolerant asynchronous 3D links, and provides 326 MFlit/s @ 0.66 pJ/bit. It was fabricated in a CMOS 65nm technology using 1,980 TSVs in a Face2Back configuration.

This second generation 3D-NoC technology has been integrated in the INTACT circuit developed in the frame of IRT Nanoelec. The 3D circuit, currently in foundry, combines a series of chiplets fabricated at the FDSOI 28nm node and co-integrated on a 65nm CMOS interposer.  The active interposer embeds several lower-cost functions, such as communication through the NoC and system I/Os, power conversion, design for testability and integrated passive components.

Moreover, the chip requires 20 times less energy for data transmission than chips placed on an electronic circuit board. This new IP is compatible with standard remote direct-memory-access-type software used for data transmission and has likely industrial uses in virtual-server migration applications.

“The steady rise in the number of applications that require high-performance computing creates a demand for new hardware-plus-software communications solutions that improve both performance and energy consumption,” said Denis Dutoit, Leti strategic marketing manager. “This new technology brick makes it possible to transfer data between processors via a network-on-chip delivering more powerful, energy-efficient computing.”

Leti will host its annual workshop during Semicon West on “Sensing your Future with Leti” at 5 p.m., July 12, at the W Hotel.  Registration is here.

Leti scientists will be available at booth #2028 in the South Hall during Semicon West to discuss this announcement and other recent research developments and initiatives.

SEMI projects that the worldwide semiconductor equipment market will be flat this year and will rebound in 2017 according to the mid-year edition of the SEMI Capital Equipment Forecast, released today at the SEMICON West exposition. SEMI forecasts that the total semiconductor equipment market will grow 1 percent in 2016 (reaching $36.9 billion) after contracting 3 percent in 2015. An increase of 11 percent is expected in 2017 for the market to reach $41.1 billion.

The following results are given in terms of market size in billions of U.S. dollars and percentage growth over the prior year:

SEMI® 2016 Mid-Year Equipment Forecast by Market Region

By EQUIPMENT TYPE

year-over-year

year-over-year

2015

2016F

% Change

2017F

% Change
Wafer Processing

28.78

29.33

1.9%

33.09

12.8%
Test

3.33

3.36

0.9%

3.46

3.0%
Assembly & Packaging

2.51

2.39

-5.0%

2.48

4.0%
Other Front End

1.90

1.86

-2.1%

2.05

10.2%

Total 

36.52

36.94

1.1%

41.08

11.2%

 

By REGION year-over-year year-over-year

2015

2016F

% Change

2017F

% Change
China

4.90

6.41

30.8%

7.24

12.9%
Europe

1.95

2.07

6.2%

2.46

18.8%
Japan

5.49

5.08

-7.6%

4.72

-7.0%
Korea

7.46

6.17

-17.3%

7.99

29.5%
North America

5.12

4.62

-9.8%

4.97

7.6%
ROW

1.97

3.13

58.9%

3.68

17.6%
Taiwan

9.63

9.46

-1.8%

10.02

5.9%

Total

36.52

36.94

1.1%

41.08

11.2%

*Totals may not add due to rounding; Source: SEMI, July 2016; Equipment Market Data Subscription (EMDS)

Equipment spending had a slow start in the beginning of the year and is expected to accelerate in the second half of the year. Spending growth will continue into 2017 driven by foundries, memory (both 3D NAND and DRAM), MPU, Power, and investments in China. Front-end wafer processing equipment is forecast to grow 2 percent in 2016 to total $29.3 billion, up from $28.8 billion in 2015.  The Test equipment segment is expected to total $3.4 billion, essentially flat when compared to last year. Assembly and packaging equipment and Other Front End equipment are forecast to contract this year, falling to $2.4 billion (-5 percent) and $1.9 billion (-2 percent), respectively.

“After a tepid 2015, device manufacturers are beginning to ramp their investments in key industry segments,” said Denny McGuirk, president and CEO of SEMI. “We expect capital spending to improve for the remainder of 2016 and into 2017.”

Taiwan is forecast to continue as the world’s largest spender with $9.5 billion estimated for 2016 and $10.0 billion for 2017. In 2016, China is projected to be the second largest spender at $6.4 billion, followed by Korea at $6.2 billion. For 2017, Taiwan is projected to maintain its leading position while the market in Korea will nudge past the market in China.

In 2016, year-over-year increases are expected to be largest for Rest of World (59 percent), China (31 percent), and Europe (6 percent). Projected year-over-year percentage increases for 2017 are forecast to be largest for Korea (30 percent increase), Europe (19 percent), Rest of World (18 percent) and China (13 percent). Visit www.semi.org/en/MarketInfo for more information.

By Pete Singer, Editor-in-Chief

On Monday, imec – the Leuven Belgium-based research consortium – hosted its annual imec Technology Forum (ITF) USA, a half-day conference at the Marriott Marquis. With the theme ‘Towards the Ultimate System’, imec’s speakers and industrial keynote speakers looked at the co-optimization of design and new technology, and how technology innovation can deliver the right building blocks to build these systems.

Delivering the keynote address at the event was Luc Van den hove, President and CEO of imec. He talked about how the world was in the middle of a decade of digital disruption brought about by integrated circuit innovation. He then provided an outlook of how the industry could continue to stay on the path defined by Moore’s Law by moving to nanowires and the 3rd dimension.

Luc van den hove, president and CEO of imec, tipped his hat to Gordon Moore, showing a short video clip and describing a future where Moore’s Law will live on through 3D integration.

Luc van den hove, president and CEO of imec, tipped his hat to Gordon Moore, showing a short video clip and describing a future where Moore’s Law will live on through 3D integration.

Van den hove noted what he said were obvious example of disruption today: Uber, the world’s largest taxi company that doesn’t own any taxis. Airbnb, the world’s largest accommodation provider that doesn’t own any real estate. Facebook, the world’s largest media provider, that doesn’t generate any media content.

“These are just a few examples, but we will see this kind of disruption everywhere, in every market and every segment,” he said. “Companies will have to adapt. They will have to reposition themselves in the value chain and come up with new business models. This is just the beginning.”

What’s made this disruption possible is IC technology and ubiquitous mobile computing. What’s been particularly beneficial over the last 50 years is that, in addition to the increased functionality that comes with scaling, there were advantages of faster operation at lower power. “This combination of effects that occurs simultaneously with scaling has resulted in the phenomenal evolution,” he said.
After a short video clip of Gordon Moore talking about the benefits of microprocessors, Van den hove give a realistic view of the future.

“Today, there is a lot of debate about the continuity of Moore’s Law. Yes, we’re faced with several tradeoffs. It’s getting harder and harder (to scale) and when we scale down our transistors we do not automatically the performance improvement that we used to with previous generations,” he said. “But we are sure there are sufficient solutions out there that will allow us to continue Moore’s legacy for several more decades. I am convinced that scaling will not only continue, it has to continue. If you want to enable the IoT wave, we will have to succeed in extending Moore’s law to generate the required compute power and storage capacity.”

Van den hove added that Moore’s Law is on the verge of morphing. “We will need other techniques in order to realize this complexity increase,” he said. “We will continue 2D scaling. It will evolve from the FinFET that is in mass production today towards horizontal nanowires, towards most likely vertical nanowires. This will bring us to at least the 3nm generation if not one or two generations more. This will keep us busy for the next 10-15 years.”

He stood by his past comments on the production-worth status of EUV. “To enable this, we will need a cost-effective lithography. We absolutely need EUV lithography to make this happen. I’m sure, based on the progress I’ve seen over the last 12 months, that EUV is ready to enter manufacturing. But we have to be realistic. Eventually, 2D scaling will slow down. I’m not saying it’s going to stop. But it’s getting harder and harder and hence it will require more time to transition from one geometry-based node to the next geometry node. We will need other ways to compensate for this gradual slowdown. One of the obvious ways to do so is to start using more extensively the third dimension, as the memory guys have started to do already,” he said.

Van den hove presented a future where devices are stacked on top of one another like Lego blocks. “Once we are using these vertical nanowires, it’s not so difficult to imagine that we may be stacking those transistors on top of each other – stack an n-FET on top of a p-FET and realize an SRAM cell. It’s obvious that such a 3D version of an SRAM cell has a much smaller footprint than its 2D equivalent. Once we can do that, we can even imagine that we may start stacking some of these building blocks on top of each other,” he said.

“It’s more straightforward to imagine that this can be done with a regular structure such as an SRAM design, but also FPGAs are very regular structures. We can even imagine that we could design random logic and design standard cells within the constraints of such a 3D Lego block and build up a logic circuit with these Lego blocks in a 3D fabric,” he continued.

Heterogeneous integration with photonics is also on the drawing board. “We will combine this also with 3D heterogeneous integration where we will be using chip stacking technology with high bandwidth, high density through silicon vias. We can then combine all these layers with 3D stacking and through-silicon vias, integrate all of this on an interposer, which can also be the substrate to integrate these 3D cubes,” he said. “By adding also photonics on such an interposer, we can also realize optical IOs. This is just another rendition of Moore’s Law which will allow more complexity in a smaller form factor.”

By Ed Korcynzski, Sr. Technical Editor

The near-term outlook for semiconductor manufacturing is challenging, with revenues down slightly but equipment spending up a bit, as reported by experts during the SEMI/Gartner Market Symposium held yesterday afternoon. The global economy is facing extreme uncertainty and is still recovering from the 2008/2009 financial crisis. Duncan Meldrum, Chief Economist with Hilltop Economics, explained why the after-shocks of the 2008/2009 global financial crisis combined with current political uncertainties result in a difficult investment environment. Compared to the 1993-2007 era when world real GDP was +3.2%, there are many indicators that the current ~2.3% GDP growth is the ‘new normal.’

“Rolling recessions in different regions have been pulling down global growth,” explained Meldrum. “Before the financial crisis, all the growth rates tended to be together in a coordinated global market. We’re actually seeing potential growth cut in half compared to what it was before the recession. That will create a new speed limit on the global economy, so it’ll be a tougher world than we’re used to.” These are high level macro-economic global investment numbers, but there’s a high correlation between these numbers and semiconductor industry silicon wafer processing in Millions of Square Inches (MSI).

Capital equipment forecast

Bob Johnson, Gartner research vice president, presented the outlook for semiconductor capital equipment, based on Garner’s economic model assumptions:

  • Consumer demand will remain weak,
  • High inventory of chips in all channels,
  • NAND and DRAM in oversupply for the rest of 2016,
  • Demand weakness continues longer term,
  • No new significant demand driver, and
  • Uncertain global economic climate post-Brexit.

Gartner is not bullish on the Internet-of-Things (IoT) to provide a next wave of demand. Premium smart-phones are expected to soon saturate global markets, and PC markets see weak consumer demand. In emerging markets, smartphones will take the majority of disposable income, which lowers new PC and tablet purchases by 10% through 2020.

NAND Flash is the long-term bright spot in the industry, with most of the growth driven by solid-state drives (SSD). However short-term oversupply in the second-half of 2016 is expected due to weak end markets, and increased output of planar 3bit/cell products. 3D-NAND represents 19% of the PetaBytes (PB) of total demand in 2016, increasing dramatically to 70% by 2020. SSDs are not just for PCs and mobile devices, but are moving into the enterprise segment and data centers, and 84% of SSDS will use 3D-NAND by 2020.

“3D-NAND manufacturing represents a major shift from litho-centric to etch-centric processing,” reminded Johnson. “The cost structures is still not competitive with 2D-NAND, but there will still be ~300k wafer-starts-per-month in the fourths quarter of 2016. By 2018, 3D-NAND will be half of the total NAND bits produced.” In response to 3D-NAND competition, 2D-NAND suppliers will likely do another shrink using their fully depreciated fabs, which will contribute to short-term oversupply.

Chinese foundry plans

Sam Wong, Gartner research vice president, discussed challenges of the foundry market related to China’s plans to develop domestic IC fab capability that is globally competitive. “Believe that China is really serious this time, with $140B investment,” said Wong. “The SOC capability of China is world-standard.”

For foundry markets in general, with increases in the number of mask layers with successive nodes the selling prices for finished wafers has to continue increasing. Wafer costs for fabless customers buying from foundries are now <$4K for 28nm-node, and <$7K for 14nm-node. TSMC ramped 14nm in one-half-year, and reports unprecedentedly low defects per mask layer to allow them to produce large Apple chips with high yield.

Packaging trends and china

Jim Walker, Gartner vice president of research, presented on “Semiconductor Packaging: the crucial growth component in China’s electronics supply chain.” IC manufacturing is critical to the economic growth and national security of China, and it is part of the ‘made in China 2015’ plan issued by China’s State Council.

China todays has already invested sufficient resources to now have ~1/3 of the global floor-space in Outsourced Semiconductor Assembly and Test (OSAT) facilities, while the percent of global revenue taken by Chinese companies is still much less. Since China has updated investment plans earlier this year, both South Korea and Taiwan industry organizations issued public statements of the need for strategic counter-investments. The semiconductor industry production in Taiwan represents ~13% of its total GDP, so China’s investment into this market is seen as a major threat.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the EVG50 automated metrology system. Designed to support the increasingly stringent manufacturing requirements for advanced packaging, MEMS and photonics applications, the EVG50 performs high-resolution non-destructive multi-layer thickness and topography measurement, as well as void detection, in bonded wafer stacks and in photoresists used in optical lithography. The system measures layers down to two microns in thickness, can inspect up to one million points, and achieves throughputs of up to 55 300-mm wafers per hour. This combination of extremely high resolution and high throughput provides cost-efficient full-wafer inspection that enables device manufacturers to improve their wafer bonding and lithography processes, as well as achieve higher yields.

The EVG 50 Automated Metrology System from EV Group performs high-throughput, high-resolution measurements of critical wafer bonding and lithography process parameters.

The EVG 50 Automated Metrology System from EV Group performs high-throughput, high-resolution measurements of critical wafer bonding and lithography process parameters.

Dr. Thomas Glinsner, corporate technology director at EV Group, noted, “The semiconductor industry is witnessing a trend toward total control and monitoring of all production processes. Mid-end-of-line and back-end packaging processes face tighter process constraints at levels previously seen only in front-end-of-line wafer processing. This is creating an urgent need for highly accurate in-line metrology that can provide critical process data quickly and cost-effectively. The EVG50 is an important addition to our suite of metrology solutions that achieves these goals at speeds and resolutions that far surpass those of competitive systems.”

Building on a legacy of widely adopted metrology solutions

The standalone EVG50 system was developed based on the company’s existing in-line metrology module (IMM), which is available as an option in EVG’s line of 300-mm process equipment and has been widely implemented in high-volume manufacturing. The EVG50 complements the company’s versatile EVG40NT measurement system, which is the industry standard for bond overlay inspection, to meet increased customer demand for full-area layer thickness and topography measurement in critical applications. The EVG50’s high throughput and unparalleled accuracy and repeatability, even at ultra-high resolutions, enables cost-effective, 100-percent inspection of production wafers, resulting in improved process control.

The EVG50’s versatility allows it to measure coating thickness for lithography as well as wafer bow and warpage, and make void inspections for a bonded wafer stack on the same system, while its low-contact edge handling enables particle-free, full-area wafer inspection. Another key benefit of the EVG50 is its flexibility. Leveraging a multi-sensor measurement mount, the system can be customized for different thickness ranges and substrates to address a wide variety of customer requirements. Its self-calibration capability also allows for better system reproducibility and productive uptime.

Media, analysts and potential customers interested in learning more about EVG’s suite of metrology solutions, including the EVG50, are invited to visit the company’s booth #1017 in the South Hall of the Moscone Convention Center in San Francisco, Calif., at the SEMICON West show on July 12-14.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced new capabilities on the EVG ComBond automated high-vacuum wafer bonding platform specifically designed to support high-volume manufacturing (HVM) of advanced MEMS devices. These capabilities include a new vacuum bond alignment module that provides sub-micron face-to-face alignment accuracy essential for wafer-level MEMS packaging, and a new bake module that performs critical process steps to achieve outstanding bond quality and performance of encapsulated MEMS devices.

The addition of these two new modules–coupled with existing capabilities on the highly configurable EVG ComBond platform such as room-temperature covalent bonding of engineered substrates–enables customers to meet the wafer bonding requirements for both current and emerging types of MEMS devices. Examples include gyroscopes, microbolometers, and advanced sensors for autonomous cars, virtual reality headsets and other applications.

“When EV Group introduced the EVG ComBond platform, we set a new standard in high-vacuum wafer bonding by building the product around a modular, highly customizable cluster design concept. This has enabled us to continually expand the capabilities of the platform over time, with applications ranging from advanced engineered substrates, power devices and solar cells to high-performance logic and ‘Beyond CMOS’ devices,” stated Paul Lindner, executive technology director,
EV Group. “With the addition of new vacuum alignment and bake modules, those wafer bonding capabilities have been expanded yet again to address the volume manufacturing needs for high-end MEMS devices.”

Challenges of scaling MEMS wafer bonding into production

Many MEMS devices have extremely small moving parts, which must be protected from the external environment. Wafer-level capping can seal a wafer’s worth of MEMS devices in one operation, and these capped devices can then be packaged into much simpler and lower-cost packages. Metal-based aligned wafer bonding is the preferred approach to MEMS wafer bonding, but is challenging to implement due to the high process temperatures involved as well as the presence of oxides that form on the bonding metal layers. As MEMS die and feature sizes decrease, achieving tighter wafer alignment accuracy also becomes increasingly important.

At the same time, vacuum encapsulation is increasingly needed for certain MEMS devices in order to reduce power consumption caused by parasitic drag, reduce convection heat transfer, or prevent oxide corrosion. Maintaining the required vacuum level for the entire wafer bonding process has been a key challenge for ramping these devices into high-volume production.

The EVG ComBond platform provides a complete end-to-end high-vacuum environment (10-8 mbar range) throughout all wafer handling, pre-bonding and bonding processes. This modular configuration significantly improves serviceability, as modules can be swapped out without breaking the vacuum level within the cluster or modules and interrupting tool operation.

New MEMS wafer bonding capabilities

New to the EVG ComBond platform is the vacuum alignment module (VAM) with wafer clamping, which enables sub-micron face-to-face alignment accuracy based on EVG’s proprietary SmartView alignment process, as well as backside and IR alignment, in a high-vacuum environment. Also new is the programmable dehydration bake and getter activation module, which accelerates the removal of sticking gas molecules prior to bonding the substrates–resulting in improved bond quality as well as reduced gas pressure in device cavities.

In addition, the EVG ComBond platform features an optional ComBond Activation Module (CAM), which enables covalent and oxide-free wafer bonding processes at room temperature or low temperatures. Integrated into the ComBond platform, the CAM allows low-temperature bonding of metals, such as aluminum, that re-oxidize quickly in ambient environments–enabling customers to reduce production costs and achieve higher wafer-bonding throughputs.

The EVG ComBond platform with the new alignment and programmable dehydration bake and getter activation modules is currently available and can be demonstrated at EVG’s headquarters.

Media, analysts and potential customers interested in learning more about EVG’s suite of wafer bonding solutions, including the EVG ComBond platform, are invited to visit the company’s booth #1017 in the South Hall of the Moscone Convention Center in San Francisco, Calif., at the SEMICON West show on July 12-14.

AMICRA Microtechnologies, a German-based vendor of advanced back-end assembly processing equipment for advanced packaging applications, has received an order for the AFC Plus System from Fabrinet West. The equipment will be installed in Fabrinet’s optical packaging service facility in Santa Clara, California. AMICRA and Fabrinet have agreed to establish a partnership agreement whereby both companies will work together to provide customers with best support for application and process development activities.

“For AMICRA, this is a strategic partnership to support our existing installed base and to support our rapidly growing USA market,” states AMICRA managing director, Dr. Johann Weinhaendler, on the latest purchase order.

The AFC Plus will provide Fabrinet with the die attach capability to maintain its leadership role in the Opto/Photonic contract manufacturing market, while providing sample build capability for AMICRA’s customers in the USA. The AFC Plus has the flexibility to process most advanced packages especially for in-situ eutectic bonding requiring 0.5µm placement accuracy.  The AFC Plus system which will be delivered in Q3/2016 and supports die placement accuracies down to ±0.5μm @ 3σ for both eutectic and epoxy bonding with cycle times down to 20 to 30 seconds/bond or 180 to 120 UPH making it well suited for processing VCSEL/AOC, Silicon Photonic, Laser Bar and MEMS components.

“Fabrinet is bringing its advanced optical packaging capabilities to Silicon Valley, where a large fraction of our customers are based. AMICRA’s AFC Plus die attach platform sets the industry standard for accuracy, throughput, and robustness. Along with many other capabilities, such as active optical alignment, wire bond, epoxy underfill, laser dicing, and various metrology tools, Fabrinet is planning to offer its customers process/product development services starting in August 2016” states Dr. Hong Hou, Fabrinet’s Executive Vice President and Chief Technical Officer. “The partnership with AMICRA allows Fabrinet to offer the best in class technical support to customers brought by both companies.”

The AMICRA die bonding product line also includes the NOVA Plus, which supports placement accuracies down to ±2.5μm @ 3σ with cycle times down to 3 seconds/bond or 1,200 UPH, and the NOVA FanOut, specifically for the FanOut market, offering a large bonding area of 550mm x 600mm while maintaining die placement accuracies down to ±3.0μm @ 3σ with cycle times down to 1.2 seconds/bond or 3,000 UPH.

Other AMICRA products include the fully automated, high-speed wafer inking system AIS, and the semi-automatic wafer inking system SIS, as well as the fully automated, high-speed precision dispensing system HDS, offered in a quad- or dual-headed configuration to support underfill, glob-top, general dispensing applications and more.

AMICRA will be exhibiting and available for equipment and technical application discussions at SEMICON West (July 12-14) and SEMICON Taiwan (Sept 7-9).

AFCPlus

With disruptive changes occurring in the electronics supply chain, 26,000 professionals will converge on SEMICON West 2016 (July 12-14) at Moscone Center in San Francisco to hear insider perspectives on what the future holds for the industry. Keynote speakers and expert panelists will discuss both challenges and opportunities to help companies navigate turbulent times.

On July 12, John Kern, Cisco’s senior VP of Supply Chain Operations, will give the Opening Keynote on “The Digital Supply Chain – The Next Breakthrough Opportunity.”  Kern states, “Of all the disruptive changes in the electronics sector, the biggest impact may come from the digitization of manufacturing and the emergence of the digital supply chain.”

On July 13, Denny McGuirk, president and CEO of SEMI, will moderate the CONNECT Executive Summit, with the theme “Everything Is Changing.”  With widespread mergers and acquisitions and China building more new chip fabs than any other country, the world has changed dramatically. Panelists Bertrand Loy (Entegris), Bridget Karlin (Intel), and Michael Campbell (Qualcomm) will discuss how they are realigning business models, strategies, and technologies to meet the challenges and embrace the opportunities.

On July 14, Atul Mahamuni, VP of IoT Product Management at Oracle, will present the Thursday Keynote on “Internet of Things in Smart Manufacturing: A Three Phase Journey to Operational Excellence,” focusing on how to extend your business applications to the physical devices in manufacturing operations.

In addition to executive events, SEMICON West will present eight business and technology forums, including three new and updated forums:

  • Extended Supply Chain Forum — includes IC Design Summit, Smart Manufacturing and Analog programs
  • Advanced Manufacturing Forum — includes lithography, scaling, MEMS/sensors, power electronics, interconnects, 3D integration, materials, 200mm, 3D printing, and more)
  • Advanced Packaging Forum — includes SiP, photonics, power, and flexible hybrid electronics

Five additional forums —Test, Sustainable Manufacturing, Silicon Innovation, Flexible Hybrid Electronics, and World of IoT — round out the extended electronics supply chain event.

To register for SEMICON West 2016, visit www.semiconwest.org. Learn more about keynotes and the executive summit. For a limited time, register for only $100 (includes admission to keynotes, TechXPOTs, Silicon Innovation Forum, World of IoT Theatre, 700 exhibits, and Intersolar).

By Paula Doe, SEMI

With many disruptive changes occurring in the electronics supply chain, the one with the biggest impact may come from smart manufacturing and the emergence of the digital supply chain.

“The digital supply chain is the next breakthrough opportunity for the industry,” says John Kern, Cisco Systems SVP, Supply Chain, who will give the opening keynote at SEMICON West 2016 (July 12-14) at Moscone Center in San Francisco. “It’s the biggest area of investment for us now because it’s where we see the most potential.” The ability to leverage data, cloud, collaboration and mobility are making it possible to eliminate, simplify and automate processes, orchestrate activities across the supply chain in real time, and empower the workforce to focus on higher value work.

Cisco began its own journey to a digital supply chain with an update of its enterprise resource planning (ERP) system.It targeted several use cases to improve processes, such as using data to manage energy consumption within a factory to drive productivity and improve sustainability. Another was automating test processes to improve quality and reduce capital costs. But now Cisco has moved on to a broader view, of automating systems so employees don’t have to spend time gathering the information, but instead can focus on analyzing the information presented to them. “That will be the big game changer,” Kern contends.

Another example is the Cisco Supplier Collaboration Platform, which allows suppliers to see directly into their supply chain data so they can fix issues that arise, such as over or under supply directly ─ without all the usual escalations, email exchanges and delays. “There’s one single source of truth for ‘supply and demand’ that everyone can see, minimizing ‘the bull whip’ effect and enabling real-time response,” he notes.

This Supply Chain digitization is happening in concert with a disruption in business models all across the sector, as users shift from buying physical assets to buying outcomes, and paying as they receive the benefits. “The impact of the cloud and the service model is changing the way we think about supply chains,” say Kern. “We need to be able to offer any options our customers want, whether it’s hardware, software or solutions, and in any way they want to consume. Our supply chain has to adapt rapidly to enable these multiple business models.” Kern will elaborate on the topic at SEMICON West on July 12 as part of the executive events. SEMICON West also will be presenting eight business and technology forums. To register for SEMICON West 2016, visit www.semiconwest.org. For a limited time, register for only $100 (includes admission to keynotes, TechXPOTs, Silicon Innovation Forum, World of IoT Theater, 700 exhibits, and Intersolar).

By Paula Doe, SEMI

Emerging opportunities for advanced packaging solutions for heterogeneous integration include a lot more than logic, memory and sensors. There’s also the challenges of packaging integrated photonics, flexible electronics, and high-voltage, high-temperature wide-bandgap power devices. Speakers from the National Network for Manufacturing Innovation Institutes targeting these new growth markets will update the SEMICON West 2016 audience on their efforts to cut the time and cost of moving from R&D to volume production for U.S. companies by supporting development of key technologies, U.S.-based facilities for fabrication and packaging, and education of the workforce.

ap forum 2016-1

Integrating silicon with optics

The new American Institute for Manufacturing Integrated Photonics (AIM Photonics) is ramping up its program to spur development of U.S. technology and manufacturing capability for integrated photonics, for next-generation high performance computing, telecommunications, and sensors. In the packaging space, first steps will be a university-industry effort to develop passive fiber-to-silicon assembly technology and automated test equipment, with a manufacturing facility targeted for 2017.

“We’re focusing on packaging, assembly and test since it accounts for most of the cost of integrated photonics,” says CEO Michael Liehr, who will update on the plans to facilitate U.S. manufacturing in this emerging sector in the Packaging Photonics session at SEMICON West on July 12.

Attaching an optical fiber of 120µm diameter to a waveguide of only several thousand angstroms remains a major challenge, typically requiring active alignment.  Volume production will need a passive alignment solution, which will require some combination of major improvement in precision of current placement tools (such as with image recognition) with some way to make the coupling more fault tolerant ─ such as by using an interposer to bridge the gap. Tool makers will need standard package interfaces to make common, not custom equipment. The institute will also work on the packaging issues of integrating the laser with the waveguides and other optical features on silicon.

“Key elements are also missing for test,” Liehr notes. “The in-line part is missing. No one has put together a commercially available system that includes the prober, the optical detection, and the coupler needed.”  The institute is putting together a university and industry team to develop solutions, and then will equip a facility to do the test, assembly and packaging of these photonic integrated circuits.

AIM Photonics also targets a Process Design Kit (PDK) design kit by the end of the year for its multi-project photonic wafers run in its front-end fab. Besides data center and telecommunications applications of integrated photonics, AIM Photonics is working with companies on phased arrays and optical sensors for healthcare and defense applications. The organization is a public-private venture, funded by the U.S. Department of Defense, the States of New York, Massachusetts, California, Arizona, and university and industry members.

Integrating silicon die into flexible, conformable electronics systems

Another emerging “packaging” opportunity is integrating silicon intelligence into  flexible, stretchable products. “People have been talking for decades now about a purely printed solution, but printed transistors do not have enough mobility for the needed performance, and in a switching application will burn out in about a day” notes Jason Marsh, Director of Technology at NextFlex, the Manufacturing Innovation Institute for Flexible, Hybrid Electronics, who will talk about this effort at the SEMICON program on flexible packaging July 14. “But there is real demand for flexible, conformable products for medical wearable and implantable devices and for IoT edge devices.”  The collaborative program aims to develop the manufacturing technology to enable these products, by integrating silicon die into flexible, stretchable environments.

This will require the development of new processes for bridging directly from ~100µm-scale printed electronic circuits to 50µm-scale PCB artwork to much finer die-level bond-pad pitch, eliminating the usual intervening steps ─ of wirebond/flip chip, package, interposer, circuit board, connector ─ all at low temperature and with good signal integrity. Potential approaches could include flip chip with an anisotropic conductor connection, or alternatively, printing the traces directly on bigger pond pads. The institute aims to develop the basic building blocks of the technology and put together a U.S. supply chain that companies can then use to develop and manufacture their own products. NextFlex is building a facility in San Jose for the technology, which members can use to develop prototypes and build their pilot products.

Building this new manufacturing supply chain means re-thinking the traditional food chain of circuit board, packaging and assembly. “We may need to do things in different order, with die attach to the substrate before circuitization, and may need big arrays on big substrates, with new process tools to handle them,” suggests Marsh. “Package and assembly suppliers will need to understand more of the full end-to-end process, with assembly companies understanding packaging, and packaging companies understanding interposers.” The project aims to help bring these suppliers together, and also to help develop the necessary technical expertise in the workforce in the U.S. “The goal is to accelerate the speed of development from some 5-6 years to 1-2 years,” says Marsh.

The program is funded by $75 million from the U.S. government, and $96 million from the City of San Jose, and other corporate, academic, and government partners.

Building a U.S. ecosystem for wide bandgap power semiconductor manufacturing

PowerAmerica, the Next Generation Power Electronics Manufacturing Innovation Institute, aims to build the U.S. ecosystem for manufacturing wide bandgap power semiconductors, by supporting R&D, production facilities, and workforce development to accelerate the adoption of these smaller, lighter and more energy efficient power systems, and to make it easier for new and small U.S. companies to develop products.

“It’s about driving down cost and validating the reliability of SiC and GaN for demanding power electronics applications. The physics are clear. Wide bandgap semiconductors can offer very high-power densities and higher performance with a lower cost bill of materials. We are rapidly approaching the tipping point where market demand and production volume will bring the price of wide bandgap devices down to match silicon in $/Amp,” says John Muth, PowerAmerica’s deputy director, who will update on the effort in the power packaging program at SEMICON West on July 12.

Taking full advantage of the physical properties of wide bandgap semiconductors for high performance will require highly optimized packages that can handle high voltages while minimizing inductance and efficiently remove heat, with more reliable materials for interconnections, die attach, and baseplate/substrates, and better cooling solutions. One result of the packaging projects to date are the low inductance, high performance power modules recently announced by Wolfspeed.

PowerAmerica activities across the supply chain range from the 6-inch SiC foundry at X-Fab in Lubbock, Texas, now being used by five members, to products under development by end users across in transportation, renewable energy, motor drives, data centers, and the power grid, at members such as ABB, Agile Switch, Atom Power, John Deere, Navitas, Lockheed-Martin, and Toshiba.

The institute has recently also started to invite unsolicited proposals that solve a technical problem to help grow and strengthen the supply chain or to accelerate adoption of SiC or GaN into new products. All projects have 1:1 cost sharing, and require a clear path to market. Other efforts include aggressive demonstrations of wide bandgap semiconductor performance by universities, industry-led road mapping activities, and curriculum development at member universities, and tutorials and short courses to bring industry engineers quickly up to speed in GaN and SiC technology.

The five-year $146 million program is funded by $70 million from DOE and another $76 million from cost matching from its members and the state of North Carolina.

To learn more about SEMICON West 2016, visit the Schedule-at-a-Glance and learn about the eight forums.

Correction: The first draft of this article stated in error that Jason Marsh’s talk would take place on July 12. Jason Marsh will speak on flexible packaging at SEMICON West on July 14.