Category Archives: Semicon West

By Bettina Weiss, VP, Business Development and Product Management, SEMI

Leading industry experts participated in the joint SEMI-MEMS Industry Group (MIG) workshop during SEMICON West 2015 to discuss industry challenges – and potential solutions and collaborative approaches – in the MEMS, sensors and semiconductor industries. The group discussed commonalities, lessons learned, and tried-and-true solutions such as standardization, best known methods (BKMs) and other pre- or non-competitive platforms to tackle some of the more vexing technology challenges in MEMS, sensors, and semiconductors. Disucssions covered heterogeneous integration, system-level packaging and a likely  move to 300mm wafers for MEMS devices.

The joint workshop was a direct result of a survey from both SEMI and MIG, conducted in parallel among their respective members in the spring.  SEMI and MIG members were asked to respond to and rank issues and challenges they see coming in the next 5-10 years, from product development and ramping to testing, packaging, and the need for Standards and broader platforms for collaboration. As an example, the chart below shows a strong indication on both the semiconductor as well as the MEMS/sensor side for the importance of higher integration devices, which makes it a natural topic for SEMI and MIG members to collaborate.

Alissa Fitzgerald of AM Fitzgerald & Associates, Dave Thomas of STPS Technologies, and Michael Nagib of Si-Ware Systems kicked off the workshop with presentations highlighting their perspective of overarching industry challenges and how innovative solutions create smarter products. Fitzgerald spoke specifically to “The Business Case for MEMS Standardization,” providing concrete examples – SOI wafer specifications and DRIE test pattern and recipe performance ─ where Standards could provide immediate benefits to the MEMS industry. She encouraged executives to study the financial benefits derived from standards and to send their engineers to actively contribute to new standards development.

The panel discussion following the presentations provided substance for the subsequent Q&A and open discussion. Moderated by Steve Whalley of MEMS Industry Group, Mike Rosa of Applied Materials, Bill Chen of ASE Group, Nim Tea of InvenSense, Inc. and Claire Troadec of Yole Developpment discussed “Manufacturing for the Internet of Things” from their vantage points and then participated in the open discussion. MEMS, sensors and semiconductor devices are headed to the Internet of Things – and that means the IoT will also require Standards. Participants talked about a variety of topics where Standards can be beneficial, from specifications for thin wafer handling and novel materials to FOLWP, monolithic integration between CMOS and MEMS and optimization of volume production processes.

Are supply chain stakeholders really collaborating, though, to leverage existing Standards, as well as jointly prioritize the need for new specifications and test methods? Are there other platforms for achieving shared objectives aside from Standards? How can we drive solutions with speed and agility? SEMI and MIG will take up these issues with the formation of a Joint Task Force to address these and other critical issues. And as a first step, both organizations will put together a landscape document of Standards Developing Organizations (SDOs) and a list of available Standards for each one, to assess what Standards already exists, which ones are applicable to both the MEMS/sensor and semiconductor industries, and then identify gaps and opportunities for new, industry-wide solutions. This is an exciting time. Become part of this activity and help shape the future!

For more information, please contact Bettina Weiss at [email protected]. Upcoming MEMS events include: SEMI European MEMS Summit and MEMS Executive Congress US 2015

By Zvi Or-Bach, President and CEO, MonolithIC 3D Inc.

SEMICON West 2015 had a strong and rich undercurrent – the roadmap forward is most certainly 3DIC. Yes, the industry can and we will keep pushing dimensions down, but for most designs the path forward would be “More than Moore.” As Globalfoundries’ CEO Jha recently voiced: It’s clear that More-than-Moore is now mainstream rather than niche. Really it is leading-edge pure digital that is the niche. Instead the high-cost leading edge processes are really niche processes optimized for applications in data centers or for high computational loads, albeit niches with volumes of hundreds of millions of units per year.”

CEA Leti’s CEO in her opening presentation for the SEMICON West–Leti day presented the following slide:

3DIC CEA-Leti

Calling the 28nm as the ‘switch node’ from the homogeneous march of the industry with dimensional scaling to the bifurcation we now see, where “More than Moore” approaches such as SOI and 3DIC are taking on an important portion of future progress.

CEA Leti went even further by dedicating its SEMICON West day entirely to 3D technologies, as is seen in their invitation:

leti day logo

GOING VERTICAL WITH LETI: Solutions to new applications using 3D technologies

  • Welcome– Leti’s 3D integration for tomorrow’s devices > N Semeria
  • CoolCubeTM: 3D sequential integration to maintain Moore’s Law > Faynot
  • Photonics: why 3D integration is mandatory > Metras
  • Computing: 3D technology for better performance > Cheramy
  • Lighting: 3D integration for cost effectiveness > C Robin
  • Nanocharacterization for 3D>  Bleuet
  • Conclusion– Silicon Impulse > N Semeria

Olivier Faynot, Microelectronic Section Manager at LETI, presented the following slide in his CoolCube presentation.

3DIC Cea-Leti coolcub

This illustrates that monolithic 3DIC of 4 tiers could provide the equivalent scaling value of the 5nm node at a far less infrastructure or NRE cost. As the slide states: “New scaling path, compared to 2D.” The time is now for monolithic 3D approaches to take hold a grow.

A similar message is projected by a slide presented by An Steegen of IMEC at their pre-SEMICON Technology Forum:

3DIC device stacking

The same assessment was also presented by Intel’s Jeff Groff from his synopsis of Intel’s Q2 call: “In summary, it seems that Intel is executing fairly well on the process technology side of the business considering the ever increasing difficulty of pushing forward with Moore’s Law. We can expect exciting new structures and materials (just maybe not at 10nm) and an increasing importance of 3-D structures in both logic and memory fabrication.” This resonates with our blog Intel Calls for 3D IC, and was recently voiced by Intel process guru Mark Bohr: “Bohr predicted that Moore’s Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.” Bohr’s ISSCC slide from earlier this year reasserts this:

3DIC ISSCC

The key two concerns regarding 3DIC stacking using TSV are (a) Cost, noted in the slide above “Poor for Low Cost,” and (b) Vertical connectivity, as voiced by Mark Bohr: “Intel’s Bohr agrees that 3D structures will become more important. He said the kind of through-silicon vias used for today’s chip stacks need to improve in their density by orders of magnitude.”

These limitations are the driver behind the efforts to develop monolithic 3D technology. Monolithic 3D would provide a very cost effective alternative to dimensional scaling with 10,000x higher than TSV vertical connectivity, as illustrated by the following slide of CEA Leti.

3DIC coolcube 2

A 1,000x improvement in energy efficiency using monolithic 3D was calculated by Stanford Prof. Subhasish Mitra. His sum-up at a SEMICON West keynote panel: “We have an opportunity for a thousand-fold increase in energy efficiency…from collaboration between dense computing and memory elements and dense 3-D integration of them.”

Until recently, all monolithic 3D process flows required a significantly new transistor formation flow. Since the transistor process is where the majority of the R&D budget and talent is being allocated, and carries with it fresh reliability concerns, the industry has been most hesitant with respect to monolithic 3D adoption. Yet in this recent industry gathering there is a sense that industry wide interest is strengthening for 3D technologies. The success of 3D NAND as the first monolithic 3D industry wide adoption could help this new interest build even faster.

A recent technology breakthrough, first presented in IEEE S3S 2014 conference (Precision Bonders – A Game Changer for Monolithic 3D) introduced a game changer in the ease of monolithic 3D adoption. Enhancement of this breakthrough will be presented in this year’s IEEE S3S 2015. This new monolithic 3D flow allows the use of the existing fab transistor process for the fabrication of monolithic 3D devices, offering a most attractive path for the industry future scaling technology.

P.S.

A good conference to learn more about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D – 3DV, and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies, and many other authors will be talking about their work on monolithic 3DIC and its ecosystem.

More blog posts from Zvi Or-Bach: 

Moore’s Law to keep on 28nm

Paradigm shift in semi equipment – Confirmed

Moore’s Law has stopped at 28nm

Paradigm shift: Semi equipment tells the future

CH2M has seen many changes and trends in the semiconductor industry since the company was involved designing many of the industry’s first wafer fabs back in the 1980s. As the industry matured and became more competitive, every new capital investment was more carefully scrutinized to make sure every investment yielded a good return.

For many years, investments in sustainable design weren’t regarded as attractive ROI generators. The technologies were there to save energy, water, and reduce waste. But the desire to avoid the cost of achieving such admirable improvements was stronger than the gratification gained by “doing the right thing.”

But times have changed. Rising regulatory rigor and improving sustainable design technologies have increasingly made doing the right thing also the economical thing.

The popularity of green building certification spawned by the USGBS’s LEED program has proliferated into an international family of green building rating systems.

CH2M has found growing acceptance of sustainable design among our semiconductor clients. For one client, the company designed a new fab achieving signif- icant reductions in energy (20%), water (35%), and emissions (50%). Another client OK’d a project called the semiconductor industry’s most environmentally friendly fab, including reductions of 15% in greenhouse gas emissions and 70% in water consumption. This trend is being supported by the advent of “smart building,” “Internet of Things,” and “Machine to Machine” technologies being applied to next generation wafer fabs. These technologies are driving new levels of achievement in such arenas as Fab Resource Management (Net Zero water/waste/energy, renewables integration, co-generation heat recovery); Building Systems (passive solar, natural ventilation critical systems redundancy, disaster planning); Information Management (building management system, building information model, energy simulation model, zone sensor controls, performance monitoring, predictive maintenance); and Optimized Human Experience via online dashboards.

Seeing this trend gain momentum, the industry approached the USGBC and formed the LEED User Group: Industrial Facilities (LUGIF), a small team of green building lead- ers including Assa Abloy, CH2M, Colgate Palmolive, GAF, Intel, Johnson Controls, Kohler Co., Procter & Gamble, Turner Construction, United Technologies and AECOM.

This group was instrumental in shaping LEED’s latest Version 4, which better address- es the green certification standards for industrial buildings including semiconductor fabs.

CH2M has helped advance this next generation fab movement with its design of the world’s first LEED Gold semiconductor fab, first LEED Gold semiconductor Process Utility Building, and first LEED Gold data center. These projects save long-term operating costs while burnishing the brand of these companies that choose to take a greener path.

Green certification programs aren’t a fit for every building. But owners who don’t think they’re a fit for green design need to know there are now more creative approaches for actively linking green design to attractive long-term economic benefits.

Today’s approach for green design is to reflect before you reject: there are refined and reliable tools to assess a fab retrofit or greenfield project for its green design suit- ability. If owners don’t think the ROI is good enough, they can always take a pass. But if they take the time to take a look, they may be surprised at how good the green design ROI has become.

By Jeff Dorsch, Contributing Editor

Semiconductor test equipment and inspection/metrology equipment are unglamorous yet critical segments of the equipment field.

Most people could name the top vendors in semiconductor manufacturing equipment, yet many would draw a blank after identifying KLA-Tencor as a leader in inspection/metrology equipment – maybe Applied Materials and Hitachi High-Technologies, if they’re on the ball.

Greg Smith, broadband and computing business unit manager for Teradyne, estimated the semiconductor test system market was worth $2.9 billion in 2014 and could come in at $2.6 billion this year.

“This year looks a little bit weaker than last year, last year being a strong year,” he says. 2014 saw a lot of capital spending on automatic test equipment, particularly in memory testing. The Apple iPhone 6 and Samsung Galaxy S6 boosted “the supply chain for those devices,” Smith observes. “This year, there’s not that kind of buzz.”

On the other hand, “automotive is very strong,” Smith says. “Microcontrollers are very strong.”

MCUs account for a total of $150 million to $200 million in sales per year, for all vendors, and testers for chips going into Internet of Things applications account for “probably only $10 million to $15 million of that total,” he adds.

Teradyne will be focusing on semiconductor test at SEMICON West, according to Smith. The company will feature its ETS-800 test system from the Eagle Test Systems line, which can handle radio frequency-enabled MCUs. The J750-LitePoint tester will also be highlighted, targeting chips for smart homes and wearable electronics.

On the inspection/metrology side of the market, Rudolph Technologies expects the second quarter will represent another quarter of growth, its fifth consecutive quarter of growth, according to Mike Plisinski, executive vice president and chief operating officer. Mobility is the main growth engine for the company and the industry, he says.

“Mobility drives a variety of devices and technologies including microprocessors, memory, RF communication devices, and MEMS sensors. The inspection and metrology requirements are increasing for many of these customers as their process complexity increases and at the same time they are under increasing pressure to react faster to consumer demand while improving long term reliability. More importantly, we see a trend towards more integrated solutions for customers,” Plisinski says.

The movement to wafer-level fan-out packaging at the back end is presenting “a lot of challenges in metrology for these types of packages,” Plisinski says.

When it comes to high-end devices using low-k and interlevel dielectrics, “we can predict where chipping and cracking could occur,” he adds. Rudolph has made significant investments in its software, which provides “more and deeper understanding,” he notes. “We go directly into the sensor data at the equipment to correlate it with what is happening at the wafer,” Plisinski says. “This is pushing the limits of our systems, requiring the use of ‘big data’ technologies and advances in data acquisition. That’s all been driven by the last 12 to 18 months of customer demand.”

“We see customers repurposing a lot of 200-millimeter equipment for some of smaller, lower-cost devices used in mobility and the Internet of Things,” Plisinski says. “We never stopped optimizing our 200-millimeter products.”

At the same time, he acknowledges that the Internet of Things is “not really driving Rudolph’s growth.”

FEI sees “momentum in the business that is favorable compared to last year, particularly in Asia,” says Rob Krueger, the company’s vice president and general manager for the semiconductor business. “Logic spending is a little lumpy, compared with memory,” he adds.

Krueger has witnessed research and development spending on 10-nanometer semiconductors in the past year, while R&D on 7nm chips is “definitely on,” he says. “We shipped our first (7nm) tools early this year to advanced laboratories.”

The large silicon foundries dominated FEI’s business in 2014, the executive says. “This year, it’s more regional foundries,” he notes. “We’re starting to see that trickle-down of advanced technology.”

One trend that Krueger sees is the transition from scanning electron microscope analysis to transmission electron microscope analysis. Analytics has evolved beyond “just pictures,” he says. While FEI’s life sciences business makes greater use of “big data” analytics technology than its electronics business, FEI’s customers are “processing larger data sets” when it comes to defect detection, Krueger says. “We’re handling data with standard computing.”

FEI is anticipating “the momentum to continue into the 2nd half of the year,” Krueger says.

FEI last month introduced a new Helios DualBeam plasma-focused ion beam system for electrical fault isolation, electrical failure analysis, and sample preparation for sub-20nm devices. The company has already made some customer shipments of the system, according to Krueger.

As the semiconductor industry progresses to 10nm, 7nm, and possibly 5nm devices, test and inspection/metrology equipment vendors stand ready to handle the challenges of new materials and other aspects of next-generation process nodes.

By Pete Singer, Editor-in-Chief

As packaging technology continues to advance to maintain the ever-increasing demand for faster, higher capacity, and lower power devices, wafer bumping plays an important role in enabling these capabilities. Bumps can be placed almost anywhere on the die, giving chip makers the ability to put more and more I/O points on an individual die compared to previous methods.

Inspecting bumps is becoming more challenging. The number of I/O points continues to increase. “As chip makers and OSATs need to put more bumps on an individual die, the geometries are being driven smaller and smaller just like transistor technology,” notes Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit.

Materials are also changing. The industry is experiencing a transition from solder bump to Cu pillar, just as it moved from an evaporated bump to a plated process, according to a new report from TechSearch International. While the transition to copper pillar is underway, SnAg remains the Pb-free solution of choice.

Laser triangulation technology in conjunction with specially designed optics and analytical algorithms is used on bump inspection systems to provide high-quality measurements of micro-bump critical dimensions at full production speeds.

“Manufacturers need to make sure all the bumps are at the same height. If you have one bump that’s too tall or too short, you start to run into connection issues that result in poor yield or a failed device,” says Goodrich. “Our systems measure bump height to make sure coplanarity is uniform across an individual die,” he added, referring to Rudolph Technologies’ Wafer Scanner Inspection Series. Combined with Discover Enterprise, Rudolph Technologies’ yield and defect management software, the tools provide yield management for 3D/2D bump and RDL metrology, bump and RDL defect detection, and macro defect inspection throughout post-fab processes.

The tools can be used in either a characterization mode, where the dimensions of every bump on every wafer is analyzed, or in a high volume manufacturing mode, where the norm is to do a sampling scenario to monitor for process excursions.

One of the biggest challenges is handling vast amounts of data. “An individual die can have several thousand bumps, which results in millions of bumps on a wafer,” Goodrich said. “The amount of data generated becomes pretty unwieldy, really fast. Being able to manage that data and turn it into information and make decisions is extremely important. We are working with customers to implement that into their process flow.”

Utilizing laser triangulation technology, the Wafer Scanner enables 3D inspection of bumps and RDL of different sizes at high speed. An optional ultra high resolution sensor enables inspection of micro bumps and RDL heights as low as 1µm. Film frame handling capability allows inspection of thin and diced wafers and features a quick-change wafer platform to switch between film frame and whole wafers.

Inspection Smooths a Bumpy Road photo

By Pete Singer, Editor-in-Chief

Imagine EUV lithography in high volume production. ASML has been working for years to make it happen.

Earlier this year, ASML said that one of its major chip-manufacturing customers has placed an order for 15 EUV systems, including two that are set to be delivered before the end of this year. ASML did not name the customer, but it is almost certainly Intel (according to research firm IHS).

ASML’s CEO Peter Wennink said in a statement announcing that the customer agreement had been signed: “EUV is now approaching volume introduction. Long-term EUV planning and EUV ecosystem preparation is greatly supported by this commitment to EUV, kick-starting a new round of innovation in the semiconductor industry. The commitment extends the planning horizon and increases the confidence in EUV.”

EUV Unlike Anything Else in the Fab Figure 1

Unlike the current atmospheric based High End immersion lithography tools used in volume manufacturing, the ASML NXE tool is vacuum based and using 13.5nm EUV light, generated by a tin-based laser produced plasma source. The systems feature all-reflective 4x reduction optics assemblies from Carl Zeiss SMT with a numerical aperture (NA) of 0.33 and a maximum exposure field of 26mm by 33mm.

EUV tools are very different from any other tool in a fab in a couple of different ways. A main difference is that the tool is designed to operate in a continuous mode. “Other tools in the fab, such as single wafer tools or batch tools, will undergo many step changes during a total cycle such as process, vent, load and unload wafers and also cleaning steps,” says Jos Donders, global market sector manager at Edwards. “In principle the EUV tool is made for continuous operation. Knowing the cost of the tool and the cost for the facilities, you understand why it’s so important that the tool is always up and why there is such a demand on the reliability and uptime of the supporting equipment such as vacuum and abatement.”

EUV Unlike Anything Else in the Fab Figure 2

Donders, who was involved with the early work at ASML in understanding vacuum and abatement requirements of EUV, said the scanner and the source have very different requirements when it comes to vacuum levels. “The condition in the source is very different than the condition in the scanner. The challenge for the vacuum and abatement system is to handle the different conditions in an acceptable footprint in the sub-fab,” he said. “The cleanliness requirements, the materials selection and the overall budget are very important, as is the vacuum system that supports it,” he added.

Hydrogen in EUV is used to mitigate the contamination effect on the mirrors Andrew Chambers, Technical manager at Edwards said.

Pumping hydrogen is a challenge in itself. “It’s a small molecule,” says Donders. “It’s very difficult to pump. Your pumping mechanism needs to accommodate hydrogen, but also other gases (when the tool is in different states).” Chambers said there is interest in alternative solutions for handling and abating the process gases for EUV and work in Edwards is underway to achieve this ahead of volume manufacturing.

Donders concluded that one of Edwards’ main tasks is to enable EUV lithography going into volume production by supporting it needs to further improve the total energy use and offering sustainable solutions going forward.

Thursday, July 16, 2015

10:00 am – 12:30 pm
STS MORNING SESSION:
A Path to Future Interconnects
Moscone North, Hall E, Room 133

11:00 am – 3:00 pm
CMP Technical and Market Trends
TechXPOT North, Moscone North Hall
Session Partner: NCCAVS CMP User Group

12:00 pm – 4:00 pm
UNIVERSITY DAY
Career Expo
Esplanade, Room 300

1:00 pm – 3:00 pm
The Factory of the (Near) Future: Disruptive Technologies from IoT to 3D Printing Impact the Semiconductor Manufacturing Sector
TechXPOT South, Moscone South Hall
Session Sponsor: Air Liquide

1:20 pm – 4:45 pm
STS AFTERNOON SESSION:
Flexible Hybrid Electronics for Wearable Applications – Challenges and Solutions
Moscone North, Hall E, Room 132

The ClassOne Technology Solstice S4 won the Best of West award, presented by Solid State Technology and SEMI. The award was presented to Byron Exarcos, president of ClassOne, at the company’s booth in the North Hall on Wednesday afternoon.

Byron Exarcos, president of ClassOne Technology; Karen Salava, president of SEMI Americas; and Pete Singer, Editor-in-Chief of Solid State Technolgy

Byron Exarcos, president of ClassOne Technology; Karen Salava, president of SEMI Americas; and Pete Singer, Editor-in-Chief of Solid State Technolgy

Solstice S4 is the first automated plating tool that delivers advanced performance on smaller substrates at affordable prices. Described as “advanced plating for the rest of us,” Solstice is designed specifically for the smaller-substrate users in emerging technologies such as MEMs, LEDs, Power Devices, RF Communications, Interposers, Photonics and Microfluidics. Solstice sets new standards for plating performance and affordability.

“There’s a convergence of forces for the different trends that we all see in the market, and right now, it’s the internet of things, it’s the More than Moore, and it’s the flexibility of the manufacturers to achieve all these things,” said Kevin Witt, chief technology officer at ClassOne Technology, after the award presention. “We’ve felt that we had a product that reflected a lot of what those requirements were.”

Witt said there’s a lot of work being done at the cutting edge of 300mm, as well it should. “But there’s an equally important 200mm and below surge. Those folks need equipment. What they can buy now is from the ‘90s,” he said.

Until now, with the Solstice. “The people that are building the 200mm and below fabs need the modern capability of wafer level packaging and interfacing for chip stacking. They need something that fits their budget profile, that is not a 300mm tool that has been repurposed for 200mm,” he said.

Witt concluded: “We went for best of show in the hopes that the world would see that there are companies that are focused on meeting the needs of the smaller level producers that are the next growth area.”

Designed for high-performance, cost-efficient ≤200mm electroplating, Solstice systems are priced at less than half of what similarly configured plating tools from the larger manufacturers would cost — which is why Solstice has been described as delivering “Advanced Plating for the Rest of Us.” Solstice can electroplate many different metals and alloys in a spectrum of processes, on transparent or opaque substrates. ClassOne now offers three Solstice models: the LT for plating process development, the S4 for mid-volume production, and the S8 for high-volume, cassette-to-cassette production, with throughput of up to 75 wph.

Earlier this week, at SEMICON West, ClassOne Technology announced a configuration for optimizing Through Silicon Via (TSV) and Through Wafer Via (TWV) processes on its Solstice® electroplating systems. The Solstice family, introduced last year, is designed to provide advanced yet cost-efficient plating for MEMS, Sensors, RF, Interposers and other emerging technologies for ≤200mm wafers. Flexibly configurable, the Solstice for TSV/TWV combines chambers for the critical blind via pre-wet operation with advanced copper plating on the robust and reliable automation frame that is the heart of the Solstice.

“In recent months customer requests for TWV, whether alone or in combination with forming redistribution layers (RDL), have skyrocketed,” said Witt. “Many of our smaller-wafer customers seek the advantages of 2.5 and 3D packaging needed for their next generation products; and cost-effective TSV or TWV processing is mission critical. The new Solstice configuration addresses their needs effectively and elegantly with a plating tool that is affordably priced for 200mm and smaller substrates.”

Witt explained that the new Solstice TSV configuration, which has already been sold to customers, employs a unique, high-efficiency but simple vacuum pre-wet chamber followed by copper via electroplating. This combination of capabilities enables the ClassOne tool to routinely produce fully-filled or lined vias with widths ranging from 5 to 250 micron having aspect ratios as high as 9:1. Traditionally, this level of performance has been challenging even for plating systems costing twice as much as Solstice. The Solstice can also be configured to perform additional downstream processing such as resist strip and seed layer etch making it a cluster tool that delivers a suite of critical processes, reducing cycle time and saving money. This technology makes it possible to process TSV alone or TSV and redistribution layers simultaneously to provide a complete solution on a single tool.

SEMI honored six industry leaders for their outstanding accomplishments in developing Standards for the microelectronics and related industries. The annual SEMI Standards awards were announced at the SEMI Standards reception held last night during SEMICON West 2015. 

2015 SEMI International Standards Excellence Award, inspired by Karel Urbanek

The SEMI International Standards Excellence Award, inspired by Karel Urbanek, is the most prestigious award in the SEMI Standards Program. The 2015 recipient is Dr. Jean-Marie Collard of Solvay Chemicals. The Award recognizes the leadership of the late Karel Urbanek, co-founder of Tencor Instruments and a past SEMI Board of Directors member who was a key figure in the successful globalization of the Standards Program.

Active in SEMI Standards development since 1997, Collard co-chaired the European Chapters of the Gases and Liquid Chemicals Committees since 2003. Under his leadership, the committees created numerous Standards for the semiconductor and solar manufacturing industries.  Collard has been instrumental in ensuring that the standards developed are relevant. He has actively recruited key players in the supply chain to contribute to development efforts, making certain that the published Standards reflect the true needs of the industry.  He also served as co-chair of the European Regional Standards Committee (ERSC) from 2009 to 2013, steering the ERSC through difficult economic times. As ERSC co-chair, Collard was also an International Standards Committee member, and provided valuable, practical input for new proposals, including the current effort to establish virtual meetings.

Collard earned his Master’s degree and Ph.D. in analytical chemistry from the University of Liege, Belgium. He joined Solvay in 1988 and has worked in Belgium, France, and the United States.

Merit Award

The Merit Award recognizes a Standards volunteer major contributions to the semiconductor industry through the SEMI Standards Program. Award winners typically take on a complex problem at the task force level, gain industry support, and drive the project to completion. Matt Milburn of UCT established the Surface Mount Sandwich Component Dimensions Task Force, within the North America Chapter of the Gases Committee, in April 2013 to develop standards for “sandwich” components (components located between substrate and another component). At the time of Task Force formation, these components did not have dimensional standards in place and varied by each manufacturer, resulting in interchangeability issues between manufacturers of functionally equivalent components.  Milburn addressed this problem by leading the successful development of ballot 5595, Specification for Dimensions of Sandwich Components for 1.125 Inch Type Surface Mount Gas Distribution Systems, which was recently approved by the Gases Committee and will be published as SEMI C88-0715.

Leadership Award

The Leadership Award recognizes volunteers who have demonstrated outstanding leadership in guiding the SEMI Standards Program. This Award is presented to individuals who have strengthened the Program through member training, mentoring, and new member recruitment. Frank Parker of ICL Performance Products and Frank Flowers of PeroxyChem have co-chaired the North America Chapter of the Liquid Chemicals Committee for over ten years. During this time, Parker and Flowers have overseen the development of new specifications and analytical test methods for liquid chemicals while keeping the extensive catalog of previously developed liquid chemical standards up-to-date with current industry needs. Their experience and patience has been critical in transforming new volunteers into productive committee contributors, effectively guiding them through the standardization process and minimizing wasted efforts.

Honor Award

The Honor Award is presented to an individual who has demonstrated long-standing dedication to the advancement of SEMI Standards. Dr. Jaydeep Sinha of KLA-Tencor has contributed to the Silicon Wafer Committee for over 15 years and has led the development of numerous metrology standards. In addition to leading the Advanced Wafer Geometry Task Force, Sinha organized several SEMI Standards workshops around the world, recruiting technologists from leading device makers, equipment suppliers, and consortia to educate local audiences on recent developments and future needs in wafer geometry. Sinha also actively works to keep the Silicon Wafer Committee familiar with oncoming industry trends, frequently inviting industry experts to speak at committee meetings on hot topics.

Corporate Device Member Award 

The Corporate Device Member Award recognizes the participation of the user community and is presented to individuals from device manufacturers. Dr. Jan Rothe of GLOBALFOUNDRIES is this year’s recipient. Rothe has been active in SEMI Standards since the mid-2000s, and has led the International E84 (Specification for Enhanced Carrier Handoff Parallel I/O Interface) Revision Task Force since 2007. Rothe’s consistent participation in the Physical Interfaces and Carriers Committee and feedback on ballot proposals has ensured that the customer perspective is reflected in all committee output.

By Shannon Davis, Web Editor

Fifty years of technological developments following Moore’s Law has changed our world in some phenomenal ways, but Intel’s Doug Davis believes the time has come to change the way we think about developing new solutions.

At SEMICON West 2015 on Wednesday morning, Intel’s Internet of Things Senior Vice President and General Manager challenged attendees to broaden their thinking on the potential of the IoT and examine their own roles in bringing about global change through new, innovative technology.

“The question is not how do we make these devices smart? The question becomes what are the problems that we can work together to solve?” Davis said.

Davis’ presentation addressed four complex issues the world is currently facing: an aging population, climate change, the urban boom, and how we feed the planet, offering real IoT solutions that could impact these growing concerns.

IoT and an aging population

Since 1950, the average lifespan has increase by more than 20 years. By the year 2050, more people on the planet will be over the age of 60 than under the age of 14.

“As we’re all living healthier, longer lives, we also have to reflect that as a society we’re unprepared to provide care for these kinds of numbers,” said Davis.

Even if the infrastructure were available, if you talk to seniors, they’d rather live out their lives at home, Davis pointed out. How can the IoT help us with this challenge? Davis offered up MimoCare as an example pioneering technology that addresses this.

MimoCare is an IoT technology currently available that uses analytics to provide the caregiver with a unique monitoring solution. Using a network of motion, door, and presence sensors, MimoCare will unobtrusively provide data on what is normal in the home and what changes are occurring, which allows the caregiver to make decisions if they are concerned. The result: seniors are enabled to live in the comfort of their own homes longer.

IoT and climate change

No matter where you stand on global warming, there’s no arguing that air quality is becoming a serious issue in an increasing number of cities in the world, Davis said.

He challenged his audience to also think about this problem differently, posing the question, “What if we reduced emissions at every point in the supply chain?”

Davis cited Intel’s own predictive analytics solutions, which have been used in a number of their fabs around the world.

“Engineers at one Intel fab have used this data to reduce maintenance time by 50%, parts replacement by 20%,” Davis said. “They were able to reduce non-genuine yield loss by as much as 20%.”

With this kind of increase in efficiencies, Davis said Intel believes this also helps to reduce their carbon footprint.

IoT and the urban boom

“We’re undergoing the fastest rural to urban migration in human history,” Davis explained. “City populations are growing by 65 million people per year – that’s seven new Chicagos every year.”

And there are a lot of growing concerns that go along with this boom, from traffic problems to pollution. To address these issues, Davis said Intel has pilot programs now in the UK that are beginning to capture data on traffic patterns, air quality, water supply and more, and overlaying that data with public service agencies, which would allow these agencies and eventually citizens to make real-time decisions and changes.

IoT and how we feed the planet

Davis argued that the real problem the world is facing isn’t how to feed the planet, but the amount of food wasted while so many people go hungry.

“The World Bank says that we’re currently wasting 1/4 to 1/3 of the food that’s being produced on the planet today,” said Davis. “We have to get better at distributing food.”

Davis shared one example of improved agricultural performance through IoT solutions installed in rice fields in Malaysia, where farmers used ground water and weather forecasting analytics to monitor and make decisions about crop management. In the end, Davis said, farmers were able to see water savings of up to 10% and rice production increase of 50%.

What’s possible in the next five years?

It’s hard to imagine what the world will look like after another 50 years of technological developments, so Davis concluded his presentation with market research that demonstrates the dramatic impact these Internet of Things systems can have in just five years.

According to recent studies by Juniper, he reported, the world’s healthcare systems could save $36B by implementing remote patient monitoring technologies. Predicted maintenance could have as much as 1,000 times return on investment, when we think about the total impact those solutions could deliver. Smart city traffic management could reduce cumulative global emissions by 164 million metric tons, the equivalent to taking 35 million cars off the road. Improved data collection, weather forecasting, and precision agriculture could decrease agricultural losses by as much as 25% percent.

“The genius of Moore’s Law showed us what was possible and set the pace for us,” Davis said. “Over the next 50 years, think about what’s possible – think beyond just the device and into the end-to-end solutions we can create, and we can tackle these huge challenges worldwide.”