Category Archives: Semicon West

By Pete Singer, Editor-in-Chief

Continued advances in the semiconductor will increasingly be enabled by materials technology, versus the scaling that has been commonplace over the last 50 years as defined by Moore’s Law. Yet new materials technology will itself create new challenges, not only in terms of deposition, etching, cleaning, planarization and cleaning, but in terms of handling. “I like to at materials within the context of what a lot of people are describing as the inflection points in the industry,” said Jim O’Neill, Chief Tech- nology Officer at Entegris. “Most materials innovations and new material introductions have been associated with those.”

O’Neill joined Entegris in 2014 as part of the ATMI acquisition. Prior to that, he was director of 14nm technology development at IBM where he led process development activi- ties at both Albany Nanotech and East Fishkill facilities.

“Historically, Moore’s Law has really been about miniaturization, but we’ve run into patterning limitations with wavelengths,” O’Neill said. “We’ve run into mobility problems with the channel ma- terials we now have. In order to maintain the spirit of Moore’s Law, materials have really been front and center.”

Today, materials are being driven most aggressively by multi-patterning: “There’s been a class of materials that have been increasingly emphasized in terms of low temperature silicon for the whole patterning stack,” O’Neill said.

Another key area is the device and the transition from planar to 3D structures, such as finFETs on the transistor side, and 3D NAND on the memory side. “This has put an increased emphasis on deposition and a transition from CVD to ALD type precursors,” O’Neill said. “Also, very specific materials such as fluorine-free tungsten, for example, for 3D NAND.”

New high mobility channel materials are also needed in the frontend. In the back end, there’s whole class of new materials being introduced for interconnects and metallurgies to try to improve RC delay performance and reliability, including cobalt and ruthenium.

One of the biggest challenges with introducing these new materials is that the infrastructure that surrounds them needs need approaches. “What you end up having to do — and what’s so disruptive to our customers — is change the whole integration scheme,” O’Neill said.

In the case of cobalt, for example, clean processes and post-polish process have need to be cobalt-compatible. “You’re not just putting in a new CVD material. You’re putting in that material and changing the enabling infrastructure that surrounds it. That’s a real challenge for our customer, the process integrators and the fab folks. But for us it creates a great opportunity,” O’Neill added.

O’Neill said Entegris’ deposition business is growing, driven to some degree by the increased need for ALD materials for 3D structures, which is the ATMI part of the business. But there are also new challenges in handling those materials. “Many of the precursors that we’re dealing with are solids. The whole challenge of handling solid materials and deriving a gas from a solid that ends up delivering a film on a wafer goes beyond the material itself and deals with the container: Its filtration, its handling. Those are really expertises of the traditional Entegris,” O’Neill said.

Entegris is now working on capabilities that would take the solid precursor in a delivery vessel with the appropriate filtration to remove any entrained particulates in the delivery stream, then sensor monitor capabilities to ensure that there is feed gas flow. “That’s really an entire materials delivery solution focused on enablement and no defectivity,” O’Neill said.

Monday, at SEMICON West, Entegris announced the release of Torrento X Series 7 nm filters with FlowPlane linear filtration technology. FlowPlane is the semiconductor industry’s first scalable, linear, high-flow filtration platform enabling advanced wet cleaning applications for the 10nm node and beyond. The first in a series of filters based on the linear filtration technology, the FlowPlane S model is designed for point of dispense (POD) applications, enabling improvements in both on-wafer defectivity and yield for critical wet cleaning applications.

“We’ve reached an inflection point where filter design must evolve to meet the needs of the most complex semiconductor manufacturing processes,” said Entegris Vice-President of the Liquid Microcontamination Control business unit, Clint Haris. “A filter is the last line of defense to prevent defect-causing contaminants from reaching the wafer. Our smaller, more powerful filtration solution will enable our customers to effectively implement their 10 and 7nm technology nodes.”

Torrento X series 7nm filters with FlowPlane linear filtration technology improve retention and increase flow rate performance by 100% compared to similarly sized radial filters. Moreover, FlowPlane users will benefit from the format’s smaller device footprint as well as improved wafer defectivity performance.

By Pete Singer, Editor-in-Chief

“Let no element on the periodic table go un-used!” That may well be the rallying cry of the semiconductor industry moving forward. One problem is that many of the new materials being considered are flammable, corrosive, toxic, pyrophoric, carcinogenic and/or hazardous in general.

“We’re all familiar with silane and hydrogen as flammable materials, but there are many other materials finding their way into manufacturing,” said Andrew Chambers, a Technical Manager at Edwards Ltd. “Disilane springs to mind, which is extremely hazardous and flammable.”

In various manufacturing process such as CVD and etch, materials are introduced into the tool as gases, liquids and solids. They react with each other and what’s on the wafer, and byproducts are pumped out of the chamber and into exhaust pipes. They are often diluted and treated by a gas abatement system, and ultimately vented to the atmosphere.

One of the biggest concerns in the fab is with flammable gas and the catastrophic dam- age that a fire could cause in the fab or sub-fab to equipment and, of course, to personnel. “If you have an exhaust pipe with flammable materials in it, it’s routine to dilute them with nitrogen to keep the concentrations below their lower flammable limit,” explained Chambers. “So even if there’s an escape to the environment, it can’t be ignited.”

A pending problem is that as process gas flows increase, more flammable materials such as hydrogen, silane and disilane are being used. “The amount of nitrogen you need to put into the exhaust pipe to dilute it to a safe level becomes extremely large,” Chambers said. “That has a number of consequences. The consumption rate increases significantly. While nitrogen in itself is not that expensive of a commodity, as you start to approach the nitrogen generation limit of your plant, it suddenly gets a lot more expensive if you have to get into extending the nitrogen supply infrastructure in your fab.”

In addition, the point of use abatement system on the end of your exhaust pipe has to be correspondingly large to deal with the very large volume of nitrogen that goes into the front of it. “The abatement of process gases in high dilution flows is very inefficient. The consequence of that is not only are you using a lot of nitrogen, but you’re having to buy very much more gas abatement capacity than you need. With that goes the additional expense of installing the equipment, providing it with water, natural gas, electrical power and so on,” Chambers said.

Edwards is presently exploring alternatives to using a gas dilution strategy to ensure safety. “We have imaginative ways of keeping the operation of the exhaust pipe safe, while reducing the cost of doing that. This includes treating the gas pipe as part of an entire inte- grated sub-fab system that is comprised of the vacuum pumps, the exhaust pipe, the end-of-pipe abatement system and the support infrastructure that goes with that. We would put in place measures so that the flammable gas is not diluted to the same level that they are accustomed to, but the safety of that gas is assured by doing a number of things. It might be that the concentration in the exhaust pipe is higher than its lower flammable limit, but that in itself is not a problem providing you keep air or oxygen or other oxidants out of the pipe at the same time,” Chambers explained.

Chambers said those kinds of ideas are starting to get some traction, because it allows the end user to regulate nitrogen consumption, reduce the amount of abatement capacity needed and generally provide a lower cost of ownership.

Clearly, properly assembled exhaust pipes with conventional joint seals will exclude air from exhausts containing flammable gases, but the operational risk is assurance of exhaust pipe integrity through years of continuous operation and numerous invasive service interventions. He said that a unified process exhaust design, with a clearly identified owner responsible for safe operation and servicing and appropriate integrated safety features, provides assurance of exhaust system integrity during prolonged operation, including routine servicing.

The same argument applies to process gases which may not be flammable but which are corrosive or toxic and could easily condense into the exhaust pipe during normal process operation. Ammonium chloride (NH4Cl), for example, is a common concern during metal etch. Ammonium hexafluorosilicate ((NH4)2 SiF6) is a nasty byproduct of nitride CVD.

“Over a period of time, they’re going to block the exhaust. Once the exhaust become blocked, you’re into areas where you need to take the tool out of manufacturing, pull the ex- haust pipe to pieces, clean it all out, leak check it and get it back into service again,” Chambers said. “There’s strong motivation for end users to provide ways of avoiding condensation in exhaust pipes.”

Interestingly, Chambers said what is perceived as a common solution to the problem — heater jackets — is not effective. “What we’ve found through a lot of experience is that, in many instances, the heater jackets and the heating systems for exhaust pipes are really badly applied. Heating the exhaust pipe and its maintenance at the required temperature is patchy at best and completely ineffective at worst.”

The best way to address all of this, according to Chambers, is to consider the sub-fab system as a complete integrated package. “We’ve been selling integrated systems comprising pumps and abatement systems for many years. If you join that whole thing together as an integrated system, it enables you to get data out of your system that can be used to provide diagnostic routines. It’s going to tell you about impending problems with your vacuum pumps, abatement system and exhaust pipe,” he said.

TÜV Rheinland, a full-service testing, inspection and certification company, exhibiting at the annual SEMICON West expo, announced the expansion of services to include Environmental, Health & Safety testing and certification of Group III-V compounds in semiconductor manufacturing environments. A Nationally Recognized Testing Laboratory (NRTL), TÜV Rheinland will have representatives on hand at the expo to discuss services ranging from mobile EMC testing, Canadian and US certification marks (cTUVus) for the North American market, and safety assessments based on SEMI standards.

“Over the years, SEMICON has become our best opportunity to meet with current and potential clients, and to truly absorb the latest developments in the semiconductor industry. This space changes so quickly, and new discoveries can alter manufacturing and safety requirements. We participate each year to be able to provide our clients with the absolute latest in safety and compliance certification services,” said Jonathan Kotrba, Business Field Director, Commercial of TÜV Rheinland.

Assessing hazardous compounds in semiconductor manufacturing

Because silicon transistor scaling appears to be reaching its limits under current technology, attention is turning to the group III–V compound family of materials to fabricate semiconductors. Group III-V compound semiconductor wafers are compounds formed by elements from columns III and V of the periodic table. Examples include Gallium arsenide (GaAs) wafers, Aluminum arsenide (AlAs), Indium arsenide (InAs), and Indium Gallium Arsenide (InGaAs), among others.

When arsenic, phosphide, and the other group III-V materials are bound or embedded in the solid wafer, they do not pose an inhalation risk. However, if evaporated during processing, like wafer heating, etch, or laser ablation, arsine gas or arsenic compounds may be driven off the wafer and are more likely to affect people. Arsenic containing compounds may deposit on unprotected clothes or cleanroom garments, and if not properly segregated, migrate within the facility and even be brought home on employees’ clothes.

TÜV Rheinland can test to SEMI S2 and S8 standards to assess potential health risks accompanying semiconductor manufacturing, and can certify an OEM in compliance with national standards, or can develop an action plan to help bring a facility up to standard so there are no certification barriers to market.

In-Situ EMC testing: Compliance solutions, delivered

There are situations when heavy equipment cannot be moved to an offsite lab even with our state-of-the-art Electromagnetic Compatibility (EMC) testing facilities conveniently located throughout North America.  For these clients, TÜV Rheinland maintains a fleet of dedicated mobile labs with specialized equipment to test at a client’s location. All test equipment is brought to the customer in climate-controlled box trucks owned by TÜV Rheinland, never a third-party shipping or trucking firm. In most instances, on-site testing takes no more than three days, from arrival to departure.

The right mark for the North American market

The US and Canadian governments have clearly defined regulations which products—especially electronics equipment—must satisfy before they can be approved for sale. TÜV Rheinland of North America is accredited as a NRTL by OSHA (The Occupational Safety and Health Administration) in the United States, and by SCC (Standards Council of Canada) in Canada.

The cTUVus certification mark issued by TÜV Rheinland tells both consumers and business partners that an OEM’s products have been thoroughly tested and specifically certified to comply with the electrical and fire safety regulations. With a single cTUVus mark, customers can demonstrate compliance for both the US and Canadian markets.

Inside every new smartphone, tablet or other digital gizmo are microchips with more circuits — and more processing power — than manufacturers could make a year or two before.

And behind each advance in microchips are innovations, such as one emerging next week from a Twin Cities firm, that consumers never think about or see.

Subodh Kulkarni, chief executive of Golden Valley-based CyberOptics, displayed a new sensor that measures humidity in chip-making.

Subodh Kulkarni, chief executive of Golden Valley-based CyberOptics, displayed a new sensor that measures humidity in chip-making.

At SEMICON West 2015, Golden Valley-based CyberOptics Corp. will unveil a sensor product that lets chipmakers measure the vibration, leveling and humidity inside the machines turning plain silicon wafers into chips. It’s an advance from a previous product that combined two measurements.

For chipmakers, that means slightly less time in a production run needs to be spent taking measurements, and more time can be devoted to making chips. It’s a jump in efficiency that is one of the reasons that digital gadgets keep getting better and cheaper.

For CyberOptics, it’s an addition to a lineup of semiconductor sensors that is the fastest-growing product segment in the company, which has about $45 million in annual sales. “What we are good at is taking different types of sensors and putting them together,” said Subodh Kulkarni, the company’s chief executive.

CyberOptics was started in the 1980s by a University of Minnesota electrical engineering professor named Steven Case, who recognized the role that laser-based sensors could play in lining up circuit boards. Its products were originally used by makers of computers and other electronics items for the assembly of circuits onto boards. It still makes those kinds of sensors, which have advanced to where they measure in 3-D and at eye-blinking speeds.

The company moved into the chip manufacturing industry in 2004 when it first combined a miniature sensor with a Bluetooth wireless transmitter and placed it on a substrate the size of a silicon wafer. That sensor device could then be run through a chipmaking machine to measure its accuracy and performance, sending data wirelessly in real time.

Since chipmakers need to check several attributes, such as whether wafers are being kept level or whether there is dust or other particles in the machine, they needed to run separate sensors through, consuming time that would otherwise be used for actual production.

The company’s new product adds humidity sensors into the multi-sensor package. Keeping track of humidity inside the machines that make chips has become more important as the distance between circuits has shrunk, the innovation that allows more circuits to be put on a chip.

Ever smaller chips

Just this week, IBM announced a breakthrough in making computer chips even smaller, creating a test version of the world’s first semiconductor that shrinks the circuitry to a separation of 7 nanometers. By contrast, today’s fastest computers and servers use microprocessors with circuits of 14- and 22-nanometers. The width of a human hair is about 10,000 times bigger. A strand of human DNA is 2.5 nanometers.

At such tiny widths, moisture inside the machine that is making a chip can create oxidation that renders the silicon wafer useless. While the IBM innovation is several years from becoming a commercial process, each step toward smaller circuits means that the machines and processes to make them need to be better.

“This is all good for us because, when transistors were hundreds of nanometers, you didn’t need to measure things that precisely,” Kulkarni said. “But as the chips get more sophisticated, the manufacturers can no longer afford to use the existing crude tools to do measurements and sensing.”

CyberOptics sold about $8 million worth of advanced sensors for chipmaking last year. It doesn’t break out profitability of such products but, in a filing to securities regulators, it said that its newest products, including semiconductor sensors, “have more favorable margins compared to products we have sold in the past.”

By Pete Singer, Editor-in-Chief

Opportunities for cost savings abound in the “sub-fab” of semiconductor operations where the vacuum pumps and gas abatement systems

Dr. Michael Czerniak, Environmental Solutions Business Development Manager, at Edwards Ltd.

Dr. Michael Czerniak, Environmental Solutions Business Development Manager, at Edwards Ltd.

reside. Typically, these systems are running full tilt, no matter what’s going on in the process tool.

In a case where the cobbler’s children may finally be getting new shoes, work is underway to improve the communication between sub-fab equipment and process tools so that fuel in gas abatements systems can be turned off if there’s nothing to abate, and vacuum pumps can be throttled back or slowed if there’s nothing to pump.

“If you have equipment that is enabled with this capability, you can access these savings by essentially turning down the power or the fuel gas consumption when they’re not actually required for chip processing, said Dr. Michael Czerniak, Environmental Solutions Business Development Manager, at Edwards Ltd.

Czerniak gave a talk at 2:00pm on Tuesday at SEMICON West as part of the Sustainable Manufacturing Forum. The forum, held on Tuesday in Moscone North, Hall E, Room 132 from 10:00am to 5:00pm, allows experts to share the latest information on the environmental and social impacts of advanced technologies that are likely to be introduced into semiconductor manufacturing in the near future.

At SEMICON West in 2014, Czerniak was honored with SEMI’s Merit Award, along with Daniel Chlus (IBM) and Lance Rist (RistTex). The trio, were part of the Energy Saving Equipment Communication Task Force responsible for developing new standards designed to help reduce energy consumption in production equipment, specifically the SEMI E167 standard.

While production equipment and support equipment are all capable of reduced utility consumption, implementation has been slow due to lack of a standard.

SEMI’s E167 solved one piece of the puzzle – enabling the factory host to tell the process too that there are no wafers coming, for example – another standard is needed for the tool to communicate with sub-fab equipment that it, too, can power down. That is where a new standard, SEMI S23 comes in. “Once the tool has decided it doesn’t need pumps and abatement for the next 45 minutes or so — whatever it decides — it can then cascade that message down to the subfab where the energy savings will actually take place,” Czerniak explained.

At SEMICON West, a working group of the SEMI S23 task force is preparing additions to the Related Information section of SEMI S23 to provide for suggested utility-consumption test conditions and report formats for some components and peripheral equipment commonly used in semiconductor manufacturing equipment systems.

The components initially considered are dry vacuum pumps, refrigerated chillers and heat exchangers, although other components such as process power equipment may be considered soon. Also under discussion is the inclusion of Related Information for the application of efficiency rating systems for components and peripheral equipment. The goal of the working group is to produce suggested new Related Information in SEMI S23 for consideration on a future SEMI Standards Ballot.

“We’re working pretty hard as part of a SEMI standards committee – to get standardized signaling for that sort of information – so that all pump and abatement suppliers can get access to signals that allow them to do these energy savings,” Czerniak said.

Czerniak said this will work best in a new facility, once the tools have the ability to communicate directly with the pumps and abatement systems. In a retrofit scenario, it can be a challenge to get those signals. “We’re talking about getting signals derived from loadlock pumps,” he said.

In practice, it may be impossible to actually turn off vacuum pumps completely, particularly those that are pumping byproducts that tend to condense inside the pump. “You generally don’t want to switch them off due to the risk of not being able to restart them. In those cases, what you do is typically reduce the frequency at which you spin them and save maybe 10-15% of the running power. To get them back to full speed and full operating temperature isn’t such a long period of time,” Czerniak said.

On the other hand, with gas abatement systems, particularly those that burn fuel (i.e., natural gas) to destroy the byproducts, it’s possible to shut them to near zero. “In our case, we usually just leave them running on a pilot flame. They come back on line in tens of seconds, and you save about 90% of your fuel gas. There are very significant savings,” Czerniak said. “At the same time, you also save on your CO2 footprint. It gets to be quite an important factor when people do CO2 audits of their manufacturing process so they can put green stickers on their end products.”

This has been the focus of one of the working groups in the European EEM450PR project, which is focused on 450mm tool developed (similar work is underway at the G450C Consortium in Albany).

In his talk on Tuesday, Czerniak described those models that were constructed as part of the EEM450PR project to simulate the impact of green modes, at various levels of wafer inactivity, initially for 300mm, and then extended for a hypothetical 450mm fab. It was also noted that additional savings would be possible in the facility, e.g. reduced process cooling water when the pump and abatement thermal load is reduced. The model was then validated by looking at data from a HVM 300mm fab, simulating the effect of green modes (without actually implementing them), and also live green mode implementation on pumps and abatement at imec’s R&D lab in Europe.

A live demonstration was also conducted in the G450C Albany fab on some installed 450mm toolsets, as part of the complementary and collaborative engagement between the regions on the 450mm topic, in order to validate the assumptions for future 450mm fabs.

CEA-Leti and EV Group launched a new program in nano-imprint lithography (NIL) called INSPIRE to demonstrate the benefits of the nano-patterning technology and spread its use for applications beyond semiconductors.

Leti and EVG Launch INSPIRE Figure 2

In addition to creating an industrial partnership to develop NIL process solutions, the INSPIRE program is designed to demonstrate the technology’s cost-of-ownership benefits for a wide range of application domains, such as photonics, plasmonics, lighting, photovoltaics, wafer-level optics and bio-technology.

Leti and EVG will jointly support the development of new applications from the feasibility-study stage to supporting the first manufacturing steps on EVG platforms and transferring integrated process solutions to their industrial partners, thus significantly lowering the entry barrier for adoption of NIL for manufacturing novel products.

In its effort to support high-volume manufacturing applications, EVG recently launched the HERCULES NIL equipment platform, and the INSPIRE program’s activities will complement the company’s efforts within the framework of its NILPhotonics competence center that was launched in December 2014.

“EVG is excited about the value that the partnership with Leti in the INSPIRE program will provide to industry,” said Markus Wimplinger, corporate technology development and IP director at EV Group. “After more than a decade of research and development activities, EVG has propelled NIL technology to a level of maturity that enables significant advantages for certain applications compared to traditional optical lithography.”

After launching its NIL technology-development program more than 10 years ago, Leti oriented the use of this technology mainly for photonics applications. In early 2014, the program was integrated in the Silicon Technologies Division to establish a NIL collaborative program.

“Leti and EVG have a long history of collaborating on ways to bring new technologies to market at reasonable costs for the benefits of our customers,” said Laurent Pain, patterning program manager in Leti’s Silicon Technologies Division. “Through INSPIRE, we will develop new ways for them to use this flexible, powerful nano-patterning technology to create new products for a wide range of applications.”

Wednesday, July 15, 2015

9:00 am – 10:00 am
KEYNOTE: The Internet of Things and the Next Fifty Years of Moore’s Law
Speaker: Doug Davis, Senior Vice President, General Manager, Internet of Things Group, Intel
Moscone North, Hall E, Room 135

10:30 am – 12:30 pm
Subsystem and Component Suppliers at Critical Crossroads to Deliver on Yield and Productivity
TechXPOT South, South Hall
Session Sponsor: Advanced Energy

1:30 pm – 3:30 pm
Packaging: Auto Utopia: Gearing up Semiconductor to Turn Dreams to Reality
TechXPOT North, North Hall
Session Partner: Meptec

2:00 pm – 4:30 pm
STS SESSION:
Scaling Transistors: HVM Solutions Below 14nm; Getting to 5nm
Moscone North, Hall E, Room 133
Session Sponsor: Lam Research

3:30 pm – 4:30 pm
SILICON INNOVATION FORUM:
INNOVATE Keynote
Speaker: Stephen Forrest, Ph.D., Professor, Dept. of Engineering, University of Michigan
Moscone North, Hall E, Room 135

4:30 pm – 6:00 pm
SILICON INNOVATION RECEPTION
Innovation Village

By Jeff Dorsch, Contributing Editor

When Gordon Moore of Fairchild Semiconductor published his famous article on chip scaling and costs in 1965, gasoline in the U.S. was 31 cents per gallon, the Dow Jones Industrial Average was under 1,000, and a house could be purchased for $13,000 or so, noted Denny McGuirk, president and CEO of SEMI, at Tuesday morning’s press conference opening the SEMICON West 2015 conference and exhibition.

It’s the 45th anniversary of SEMI itself and the annual SEMICON show in Northern California during 2015, he added.

Karen Savala, president of SEMI Americas, reviewed SEMICON West events for this week and new aspects of the show, such as the Career Exploration Forum.

Dan Tracy, SEMI’s senior director of industry research and statistics, presented the market forecast for semiconductor equipment and materials. Foundry and memory chip manufacturers will primarily drive this year’s growth for wafer fabrication equipment, he said.

SEMI is forecasting capital equipment revenue will reach about $40 billion worldwide this year, with 8 percent growth for all equipment and 10 percent growth for wafer fab equipment.

SEMI Press Conference Highlights Market Forecast, Economic Conditions Figure 1

The global materials market is predicted to increase 4 percent in revenue this year, according to Tracy, to $46 billion for all packaging and semiconductor materials.

The SEMI executive focused on fan-out wafer-level packaging, which will increase dramatically over the next four years, according to TechSearch International. WLFO is primarily meant for mobile applications, “driven by consumer demand,” Tracy noted. Such consumer products will bring “a lot of pricing pressure,” he added.

Tracy also highlighted the currency situation presented by a strong dollar, which is having adverse effects on the euro and the yen. The Semiconductor Equipment Association of Japan estimates 2014 billings grew by 37 percent when measured in yen, and only 26 percent measured in U.S. dollars.

SEMI Press Conference Highlights Market Forecast, Economic Conditions Figure 2

Rudolph Technologies, Inc. and DISCO Corporation of Tokyo, Japan, announced a collaborative partnership to deliver leading-edge hardware and software solutions to optimize the wafer saw unit processes. These comprehensive solutions will enable their customers to consistently improve the quality and productivity of their advanced packaging products. The complete wafer saw solution includes: DISCO’s fully automatic dicing saw for high-throughput, dual-cut processing, DISCO’s ablation laser saw and stealth dicing saw, Rudolph’s NSX inspection system for post-saw inspection, Rudolph’s new Equipment Sentinel fault detection and classification (FDC) software for real time monitoring and feedback of DISCO’s dicing tools, and Rudolph’s Discover Enterprise yield management software for sophisticated wafer-to-process tool correlations.

The evolution of semiconductor device materials for advanced packaging has resulted in more stringent dicing process requirements. Process deviations and excursions during die singulation can result in chips and cracks that impact the long-term reliability of devices. The agreement between DISCO and Rudolph, which took effect June 1, 2015, will drive a new level of innovation in saw processing, including improved kerf control, chipping minimization and overall cost-of-ownership enhancement resulting in solutions that will accelerate advanced packaging adoption.

“With the increasing use of complex materials in today’s semiconductor devices, dicing is an increasingly critical process step. DISCO is committed to providing the highest quality wafer saw solutions to address our customers’ most demanding challenges. We continue to invest in our industry-leading wafer dicing equipment, leveraging advanced sensors and data acquisition technologies to provide even greater insight into the performance of our equipment,” explains Noboru Yoshinaga, executive operating officer, general manager, sales division at DISCO. “Through our collaboration with Rudolph we are able to turn data into valuable knowledge for our customers, making DISCO tools easier to ramp, monitor and control.”

“For the past year, our collaboration with DISCO has allowed us to understand and address the increasing challenges faced by our mutual customers resulting in a close partnership capable of providing comprehensive solutions to improve device reliability and data reporting, while at the same time lowering their costs and decreasing ramp times,” states Mike Plisinski, Rudolph’s executive vice president and chief operating officer. “Demand for turnkey solutions is increasing and we are committed to continuing to develop and build on this success to meet that growing demand.”

According to Thomas Sonderman, vice president and general manager of Rudolph’s Software Business Unit, “Our new, automated FDC software, Equipment Sentinel, offers advanced packaging manufacturers significant benefits that, to date, have not been fully exploited by the industry. For example, the bi-directional correlation of equipment sensor data with diced product data gives users a comprehensive, easy-to-understand view of their process, allowing them to use predictive analytics to take immediate action, thus reducing product jeopardy and improving the overall effectiveness of their manufacturing operations. The savings that result from avoiding a single failure at a critical process step can easily justify the return on investment for this type of process control solution.”

Equipment Sentinel, which was announced today, combines key wafer-level data with high-fidelity tool signal and event data into a single framework, giving users a comprehensive, easy-to-understand view of their processes and equipment. Currently installed at multiple beta sites worldwide, fab personnel will use Equipment Sentinel software to extract the maximum value from the voluminous amounts of data generated in today’s semiconductor operations.

“Many applications have been developed over the years to address advanced tool monitoring and control for semiconductor manufacturing, but they are typically focused on either wafer or equipment state information, not both,” said Sonderman. “Equipment Sentinel integrates these formerly independent data streams into a powerful monitoring and control engine to enable timely actionable intelligence, greatly enhancing optimization capabilities with predictive analytics in the fab.”

Rudolph’s new Equipment Sentinel software can efficiently identify and isolate the cause of abnormal operating conditions and implement corrective actions to reduce product jeopardy and increase overall equipment effectiveness.

“The ability to quickly detect, isolate and correct actual tool excursions provides unparalleled value to a manufacturing operation. In many cases, the detection of a single critical incident more than offsets the total cost of this type of system,” added Sonderman. “Equipment Sentinel is capable of acquiring, processing and analyzing the massive amounts of data generated in today’s high-tech manufacturing environments, providing a new avenue for corrective actions to ensure the maximum return on investment for semiconductor manufacturers.”

Stop by the Rudolph booth #5580 for more information.

Nano-electronics research center imec announced today at SEMICON West that it has demonstrated concept and feasibility for pore-sealing low-k dielectrics in advanced interconnects. The method, based on the self-assembly of an organic monolayer, paves the way to scaling interconnects beyond N5.

The need for ultra-porous low-k materials as interconnect dielectrics to meet the requirements dictated by the ITRS (International Technology Roadmap for Semiconductors) poses several challenges for successful IC integration. One of the most critical issues is the indiffusion of moisture, ALD/CVD metal barrier precursors and Cu atoms into the porous low-k materials during processing (low-k pore diameter larger than 3nm, up to 40% porosity). This leads to a dramatic increase of the material dielectric constant and leakage current, and to the reduction of the voltage for dielectric breakdown.

Imec has developed a method to seal the pores of the low-k material with a monomolecular organic film. The method not only prevents diffusion of moisture and metal precursors into the low-k material, it also might provide an effective barrier to confine copper within the copper wires and prevent copper diffusion into the low-k material.

Self-assembled monolayers (SAMs) derived from silane precursors, are deposited from vapor phase on 300mm wafers into low-k during chemical vapor or atomic layer deposition and subsequent Cu metallization. The dielectric constant (k) of the resulting sealing layer is 3.5 and a thickness lower than 1.5nm was achieved. This is key to limit the RC delay increase enabling beyond 5nm technology nodes. As a result, a ca. 30% capacitance reduction was observed after SAM pore-sealing was applied. Moreover, a clear positive impact on the low-k breakdown voltage is observed upon sealing.

imec

Imec’s research into advanced interconnects includes key partners as GLOBALFOUNDRIES, Intel, Micron, Panasonic, Samsung, SK Hynix, Sony, and TSMC.