Category Archives: Semicon West

SEMI today announced that Mark Durcan, CEO and a member of the Board of Directors of Micron Technology, is the recipient of its 2015 SEMI Outstanding EHS Achievement Award – Inspired by Akira Inoue. Durcan accepted his award for leadership at the Global Care Environmental, Health, and Safety (EHS) Lunch today at SEMICON West 2015 in San Francisco, Calif.

“SEMI is pleased to recognize Mark Durcan’s leadership in the global semiconductor industry,” said Denny McGuirk, president and CEO of SEMI.  “Micron has achieved significant corporate citizenship goals, and Mark has ensured their execution through leadership and strong governance practices. Most importantly, his focus and advocacy of sustainable manufacturing initiatives have resulted in significant positive impact to the global semiconductor manufacturing industry.”

“At Micron, we believe being a leader in memory involves conducting operations that lead our industry in environmental health and safety,” said Micron CEO Mark Durcan. “Micron’s vision is to create a work environment, business practices and memory products that contribute to the sustainable use of our planet’s resources. Memory makes megatrends like Big Data, mobility and the Internet of Things possible. We enable these trends with innovative memory technology that is produced with a commitment to global sustainability.”

Durcan’s leadership in EHS is particularly significant to the semiconductor industry given Micron’s global manufacturing facilities in the U.S., China, Japan, Malaysia, Singapore, and Taiwan. His leadership extends beyond Micron’s facilities, influencing the broader semiconductor industry from his position as Board member of the Semiconductor Industry Association (SIA) in the U.S. and as a U.S. delegate at the World Semiconductor Council (WSC). Durcan collaborated with his SIA colleagues and members companies to pursue aggressive EHS objectives, even enlisting Micron’s staff to help lead SIA’s global EHS advocacy efforts.

Durcan’s leadership impact at Micron can be measured in four crucial areas that are in support of SEMI Award criteria:

  • Occupational Safety and Health: Micron launched a global occupational health and safety system, first receiving OHSAS 18001 certification in 2004 for all of its global facilities and further deploying those systems to acquired facilities including Elpida in 2014. In addition, Micron’s Singapore site received the Workplace Safety and Health Performance Award from the Singapore Workplace Safety and Health (WSH) Council in 2012. At the Taichung, Taiwan site, the Micron EHS Team shared best practices for reducing occupational injuries and was recognized in 2012 by the local authorities at the Central Taiwan Science Park (CTSP).
  • Environmental Management:  Micron implemented an environmental management system at its sole Boise, Idaho site in 1997 becoming one of the first companies in the U.S. to attain certification under ISO 14001.  Micron’s commitment was carried forward as a global system by deploying global ISO 14001 expectations for all of its worldwide facilities. At Micron’s headquarters in Boise, the City of Boise recognized Micron in 2011 for the best green commercial building project to reduce energy utilization.  In 2014, the headquarters location conserved 730 million gallons of water, recycled 104,761 pounds of integrated circuit trays and 1.4 million pounds of paper, plastic, cardboard and wood, and saved 10 million kWh of energy due to chilled water economizer and 7.5 million kWh due to energy efficiency.
  • Water Conservation: Micron’s reclamation system is a model for water-use habits in the semiconductor industry. Examples of water reclamation at Micron include the site’s supply for fire suppression system back-up, landscape irrigation water, cooling towers, boiler water make-up, and tool cooling.
  • Pollution Prevention: Micron is committed to reducing, reusing or recycling chemicals used in its manufacturing process. The company has achieved a 50 percent reduction in photolithography Spinfil chemical use, a reduction in hazardous waste, and an $800,000 reduction in annual material spend savings. Micron also developed a waste collection system that recovers chemicals used in the fabrication process. In turn, Micron ships used chemicals for reprocessing into other products such as a cleaning compound.

The “Outstanding EHS Achievement Award — Inspired by Akira Inoue” is sponsored by SEMI (www.semi.org). The award is named after the late Akira Inoue, past president of Tokyo Electron Limited and a strong advocate of EHS. Inoue also served on the SEMI Board of Directors. The award recognizes individuals in industry and academia who have made significant contributions by exercising leadership or demonstrating innovation in the development of processes, products or materials that reduce EHS impacts during semiconductor manufacturing. Past Award recipients include: Tzu-Yin Chiu (CEO, SMIC), Ajit Manocha (CEO, GLOBALFOUNDRIES), Dr. Morris Chang (chairman and CEO, TSMC), Dr. Jong-Kap Kim (chairman and CEO, Hynix Semiconductor), Atsutoshi Nishida (president and CEO, Toshiba), and other prominent industry leaders.

By Pete Singer, Editor-in-Chief

SEMICON West 2015 kicked off Tuesday morning with a keynote panel session that addressed the challenges of “Scaling the Walls of Sub-14nm Manufacturing.” The general consensus was that future progress is dependent on better coordination and collaboration between design, manufacturing and packaging companies and people.

The panel consisted of Jo de Boeck, Senior Vice President, Corporate Technology at imec, who acted as the moderator; Gary Patton, Chief Technology Officer and Head of Worldwide Research and Development at GLOBALFOUNDRIES; Michael Campbell, Senior VP Engineering at Qualcomm; Calvin Cheung, Vice President, Business Development and Engineering at ASE and Subhasish Mitra, Associate Professor, Dept. of EE and CD at Stanford University.

Tuesday panel

Patton said the end of scaling was nowhere in sight. “People have talked about the end of scaling. Scaling is not going to end. I am not worried about solving the physics challenges,” he said. “We have run into many barriers over the years and we always find a way to get around it.

Patton said what worries him is doing it in a way “that can deliver to our customers a real value proposition for going to that next technology node. The cost of doing design in these nodes is increasing at a pretty rapid rate and we have to provide them with a return on investment. It’s becoming more challenging,” he said.

He noted that in the past most breakthroughs, such as high-k metal gates, took over 10 years in the research stage before they were ready for manufacturing. That was one reason behind the merger between IBM and GLOBALFOUNDRIES: access to 16,000 some IBM patents. Patton also mentioned IBM’s expertise in a ASICs business, differentiated IP, RF technology – both silicon germanium as well as RFSOI – as well as 3D and 2.5D technologies.

Qualcomm’s Mike Campbell said the biggest threat to Moore’s Law is yield. “Yield is now an end-to-end question,” he said. “That doesn’t just mean semiconductor yield today. It’s the package yield on top of that and then the systems yield.”

Campbell said he’d like to see that end-to-end yield contained in a productivity model. “If you have a 10nm or 7nm silicon piece and it works to the spec at the silicon level, but then we change the stress characteristics because we have to saw and dice it up into a package. Then we put it into a 2.5D or 3D package and change the stress levels again. The yields change at every level,” he said.

Campbell believes that the whole system has to be interactive. “Until 28nm, you didn’t need to have that interactivity. But as we go deeper and deeper into submicron technology, the interactivity between the package, the system and the silicon itself—and the basic R&D for the silicon – all have to start to play together or else at the end we’ll end up with gaps in the system which will then add cost to the deliverables that we have to bring to the marketplace,” he said.

ASE’s Calvin Cheung said the company’s biggest concern was CPI (chip package interaction). “We are really pushing assembly and test technology capabilities,” he said. “In the case of 2.5D, we have connect a couple hundred thousand interconnects and put them on a very, very small space. With the scaling, the die is getting smaller but your I/O density continues to increase.”

SEMI today announced that Stephen S. Schwartz, CEO of Brooks Automation, and Toshikazu Umatate, senior vice president and general manager of the Semiconductor Lithography Business at Nikon Corporation, were elected as new directors to the SEMI International Board of Directors in accordance with the association’s by-laws.

Four current board members were re-elected for a two-year term: Bertrand Loy, president and CEO of Entegris; Dave Miller, president of DuPont Electronics & Communications; Kyu Dong Sung, CEO of EO Technics; and Xinchao Wang, chairman and CEO of JCET.

Additionally, the SEMI Executive Committee confirmed Yong Han Lee, chairman of Wonik as SEMI Executive Committee chairman, and Tetsuo Tsuneishi, chairman of the Board of Tokyo Electron, Ltd. as SEMI vice-chairman.

The leadership appointments and the elected board members’ tenure become effective at the annual SEMI membership meeting on July 15, during SEMICON West 2015 in San Francisco, California.

“These two distinguished industry leaders will be tremendous assets to the SEMI Board of Directors,” said Denny McGuirk, president and CEO of SEMI. “We also appreciate the continued service of those re-elected to the Board — their counsel and wisdom is valued as SEMI responds to new industry challenges, inflections, and opportunities.”

SEMI’s 19 voting directors and 11 emeritus directors represent companies from Europe, China, Japan, Korea, North America, and Taiwan, reflecting the global scope of the association’s activities. SEMI directors are elected by the general membership as voting members of the board and can serve a total of five two-year terms.

By Pete Singer, Editor-in-Chief

The expansion of fan-out is finally coming, says Rich Rogoff, Vice President and General Manager, Lithography Systems Group at Rudolph Technologies.

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging.

It was originally introduced by Infineon in the fall of 2007. Called eWLB, or embedded wafer-level ball grid array technology, it enables all operations to be performed highly parallel at wafer level. In August of 2008, STMicroelectronics, STATS ChipPAC, and Infineon signed an agreement to jointly develop the next-generation eWLB, based on Infineon’s first-generation technology.

Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.

STATS ChipPAC’s eWLB high volume manufacturing process, for example, today includes automated wafer reconstitution (including wafer-level molding), redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 200mm and 300mm diameters can be supported.

According to a recent report from Yole Développement, the fan-out WLP (FOWLP) market will reach almost $200M in 2015, with 30% CAGR in the coming years. Yole analysts say FOWLP started volume commercialization in 2009/2010 and started promisingly, with an initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. In 2012 big fabless wireless/mobile players started slowly volume production after qualifying the technology.

It faced strong competition from other packaging technologies, such as wafer-level chip scale packaging (WLCSP) in 2013/2014. Intel Mobile also backed off from the technology, and the main manufacturers reduced their prices in 2014, creating a transition phase with low market growth.

Strong growth is now expected, hoped in part by the arrival of 2nd generation FOWLP. “Benefiting from the delay in introducing 3D through-silicon via (TSV) architectures, FOWLP is currently seen as the best fit for the highly demanding mobile/wireless market and is attractive for other markets focusing on high performance and small size”, explains Jérôme Azemar, Technology & Market Analyst, Advanced Packaging & Manufacturing, Yole Développement.

Rudolph’s Rogoff believes it will be implemented in a wafer form for the next year or two, but will ultimately transition to a panel-based approach. “The big question for the industry is are they going to move to panels?” Rogoff asked. “From a lithography perspective, the tools are ready today. As the demand goes up, there will be a push also for a switch,” he said. “Development of panels has already started and will continue to increase in activity over the next year.”

In an article in Solid State Technology published in 2014, titled “A square peg in a round hole: The economics of panel-based lithography for advanced packaging,” Rogoff said moving from round wafers to rectangular panels (“panel-ization”) saves corner space, delivering a roughly 10% improvement in surface utilization. The larger size of the substrate and the improved fit between the mask and substrate reduce the transfer overhead by a factor of 5. The potential reduction in throughput resulting from an increase in the number of alignment points is more than offset by the improvements in throughput. Compared to a 1X stepper on wafers, panel-based processes can reduce lithography cost per die by as much as 40%.

One of the advantage of Rudolph Technologies’ JetStep Panel System (JetStep S3500) is that it can handle such rectangular panels. Both the panel and wafer 2X reduction steppers offer many advantages — based in part on Azores’ 6700 platform which was developed for LCDs — including the largest printable field-of-view, programmable aperture blades and large on-tool reticle library, large depth-of-focus along with autofocus to accommodate 3D structures in advanced packaging, very large working distance, and warped substrate handling (+/- 6mm). The wafer system (JetStep W2300) features programmable wafer edge protection, enabling a variable edge exclusion zone of 0.5-5 mm. The systems also feature a large (17mm) working distance between the lens and the substrate, which helps avoid a common maintenance issue on 1X systems.

Rogoff said the ability to handle warped wafers is increasingly important. “We’ll always be putting the best focus point in the middle of our depth of focus range. If there’s any variation due to substrate warp, we can go up a little and down a little and we’re still going to be in focus,” he said.

The large working distance helps eliminate problems with thick resists, which can outgas and potentially contaminate the lens. “We’re so far away — and we also have some purging in the area – we don’t have that issue. The less you have to take the machine down to clean it, the better,” he said.

When it comes to fan-out, the challenge is being able to manage the overlay performance over a large field area. “Our competitors like to say it can’t be done, yet we prove it can,” Rogoff said. “The larger the field is, the more die you get in it, so the more variations you’re likely to see. With our ability to correct for intrafield parameters, we can extract out that variation so what’s left is just random noise.”

If the random noise gets too high, another solution Rudolph can provide is a combination of stepper modeling capability with inspection. “You can measure the die placement on a high speed inspection tool, throw that data into the modeling software and spit out the stepping model for the stepper,” Rogoff explained. “This is something we’re continuing to develop. The first round is available and as the fan-out technology gets more complex, we’re continuing to expand on that.”

By Jeff Dorsch, Contributing Editor

The used and refurbished semiconductor equipment market can be a hazardous business for buyers. The watchword always is: Caveat emptor – let the buyer beware.

There are many reputable companies in the used equipment business, of course. Intel, Texas Instruments, and other big chipmakers put their surplus production equipment on the market, typically on an “as-is” basis.

Some used-equipment vendors and brokers also offer their wares as they are, without any guarantees or warranties. The chip-making gear may be faulty; it could lack a software license from the original equipment manufacturer, which has occasionally been a legal issue.

Many purveyors of used equipment are also involved in refurbishing pre-owned equipment, and some even develop their own equipment, given their experience in buying, maintaining, updating, and selling equipment.

“It’s an interesting year. The industry has been very busy,” says Byron Exarcos, CEO of ClassOne Equipment, which is based in Atlanta and has operations around the world in key markets. “There definitely is a lack of supply, versus demand. It has driven pricing up.

”It’s become very difficult to find equipment, especially 200-millimeter equipment,” he adds. “There’s a very tight supply and high demand, which invariably increases prices.”

Dave Pawlak, ClassOne’s vice president of purchasing, says the supply-and-demand situation has lately improved. The market is seeing “a slowdown” after a torrid period of activity, he adds. “Tools are becoming available. We’re starting to see a turn. The prices are coming down,” Pawlak observes.

Driving the demand for 200mm tools are manufacturers of microelectromechanical system devices and sensors, according to Exarcos. Light-emitting diodes are typically manufactured on 150mm wafer fabrication lines.

“They may have been using 3-inch, 4-inch tools,” he says of these manufacturers. “Eight-inch tools – they’re the leading edge.”

While Intel and Samsung Electronics are fabricating their most advanced chips on 300mm fab lines, those integrated device manufacturers (both of who are in the foundry business) are “keeping their 200mm tools,” Exarcos says. “They’re getting busy with them.”

The ClassOne Group now has an operation in Kalispell, Montana, which was the home of Semitool, an equipment manufacturer acquired in 2009 by Applied Materials. ClassOne Technology, founded in 2013, makes new wet-chemical process tools, including electroplating systems, for companies making LEDs, MEMS, photonics, power devices, radio-frequency devices, and other components. These companies may turn out 5,000 to 10,000 wafer starts per month, according to Exarcos, not on the level of volume production for the big IDMs.

In February, ClassOne Technology announced the acquisition of two product lines, a spin-rinse-dryer and a spray solvent tool, from Microprocess Technologies. Those products became the company’s Trident SRD and Trident SST lines.

Exarcos concludes, “It is critical to work with the right company.”

The related field of spare parts for semiconductor equipment was rocked in the 1990s by the case of Semiconductor Spares, Inc., which conspired with insiders at Applied Materials, Lam Research, and Varian Associates (the semiconductor equipment business of which was bought by Applied in 2011) to steal drawings of parts, enabling SSI to undercut those vendors on pricing. David W. Biehl, the company’s owner and president, pleaded guilty to a variety of charges in the case and was sentenced in U.S. District Court to 31 months in prison and ordered to pay $100,000 in restitution.

Once more – Caveat emptor.

By Jeff Dorsch, Contributing Editor

The short answer to that headline’s question is “no.” Longer term, in going beyond the 5-nanometer process node, silicon may finally reach the end of its usefulness to the semiconductor industry.

SEMI estimates the worldwide semiconductor materials market grew 3 percent in 2014 to $44.3 billion, compared with 2013’s $43.05 billion. The 2014 total was composed of $24.0 billion in wafer fabrication materials and $20.4 billion in packaging materials. Taiwan last year remained the world’s largest consumer of semiconductor materials, accounting for $9.58 billion in sales, an 8 percent increase from the prior year’s $8.91 billion.

SEMI’s Silicon Manufacturers Group reports silicon wafer area shipments increased 11 percent in 2014 to 10,098 million square inches, as against 9,067 MSI in 2013. Revenues, however, grew only 1 percent year-to-year, to $7.6 billion from $7.5 billion, still far below the 2007 peak of $12.1 billion.

Researchers around the world are constantly investigating materials that could be the successor to silicon. Molybdenum disulfide shows promise. Graphene, the “wonder material” with many exciting attributes, is difficult to employ as a semiconductor material due to its lack of a bandgap, although bandgaps can be found in bilayer graphene or graphene nanoribbons.

Closer at hand are silicon carbide and the III-V materials, such as gallium arsenide and gallium nitride.

Scott Balaguer, Edwards’ president of the U.S. & Europe Semiconductor Business Unit, observes, “Chemistries, gas flows and materials are constantly changing across numerous applications and design nodes. We see these innovations in both silicon and compound semiconductor technologies. A great example is the new prototype SiC line at SUNY Polytechnic Institute that General Electric is driving in Albany, New York.

“The rate and pace of 10nm development is picking up and 14nm HVM fabs continue to improve and efficiencies and achieve higher yields.

“Clearly the rate of EUV adoption has gained momentum as source performance and throughput has improved. It is not a question of if, it is just when,” Balaguer says.

Thomas Piliszczuk, senior vice president of marketing, business development, and global sales for Soitec, says radio-frequency silicon-on-insulator technology is becoming mainstream and has seen “huge growth over the past several years.” He adds, “SOI is today in 99 percent of smartphones.”

On the fully-depleted silicon-on-insulator front, the industry today is at a tipping point with strong industry support and a growing ecosystem. The low-power, significant performance, and cost benefit attributes of FD-SOI are making the technology attractive for mobile, wearable devices, and the Internet of Things, as well as automotive and networking applications, according to Piliszczuk. “FD-SOI is a cheaper solution, overall,” he says. The executive looks for it to soon become “a very high-volume market.”

“The ecosystem now sees SOI not as a niche any more, but as a robust technology for many consumer applications,” Piliszczuk concludes. Shin-Etsu Handotai and SunEdison Semiconductor have joined Soitec as SOI wafer suppliers.

EUV and immersion lithography are expected to usher in the 7nm and 5nm process nodes. What happens past N7 and N5?

An Steegen, senior vice president of process technology for imec, looks ahead to nanowires and high-mobility channels in semiconductors of the future. Those nanowires will be made of silicon or silicon germanium, she says, with germanium in the channel.

That technology will have its drawbacks, she acknowledges. “One nanowire will never beat the performance of one FinFET,” Steegen says.

IBM Research has touted the future use of carbon nanotubes in transistors.

So, don’t write off silicon for now. The old reliable material may have years of usefulness ahead, whether in compound semiconductors or on its own.

SEMI projects three consecutive years of growth in worldwide semiconductor equipment sales according to the mid-year edition of the SEMI Capital Equipment Forecast, released today at the SEMICON West exposition. SEMI forecasts that the total semiconductor equipment market will grow 7 percent in 2015 (reaching $40.2 billion) and expand another 4 percent in 2016 to reach $41.8 billion.

The following results are given in terms of market size in billions of U.S. dollars and percentage growth over the prior year:

SEMI® 2015 Mid-Year Equipment Forecast by Market Region

By Equipment Type

2014 Actual

2015 Forecast

 year-over-year

(% Change)

2016 Forecast

 year-over-year

(% Change)
Wafer Processing

29.26

32.13

9.8%

33.53

4.4%
Test

3.55

3.45

-2.8%

3.53

2.3%
Assembly & Packaging

3.06

2.80

-8.5%

2.84

1.4%
Other Front-End

1.63

1.77

8.6%

1.89

6.8%

Total (Equipment)

37.50

40.15

7.1%

41.79

4.1%
By Region

2014 Actual

2015 Forecast

 year-over-year

(% Change)

2016 Forecast

 year-over-year

(% Change)
China

4.37

4.66

6.6%

5.54

18.9%
Europe

2.38

2.71

13.9%

3.41

25.8%
Japan

4.18

4.73

13.2%

4.60

-2.7%
Korea

6.84

8.55

25.0%

9.23

7.9%
North America

8.16

6.45

-21.0%

6.70

3.9%
ROW

2.15

2.16

0.5%

2.31

6.9%
Taiwan

9.41

10.89

15.7%

10.00

-8.2%

Total (Regions)

37.50

40.15

7.1%

41.79

4.1%

Totals may not add due to rounding
Source: SEMI, July 2015; Equipment Market Data Subscription (EMDS)

Following strong growth of 18 percent in 2014, the equipment market is poised to continue to expand for the next two years. Key drivers for equipment spending are investments by memory and foundry fabs. Front-end wafer processing equipment is forecast to grow 10 percent in 2015 to $32.1 billion, up from $29.3 billion in 2014.  Test equipment, assembly and packaging equipment are forecast to contract this year, falling to $3.5 billion (-3 percent) and $2.8 billion (-9 percent), respectively.

“Memory and foundry device manufacturers are continuing to invest in leading-edge process technologies to enable mobility and interconnectivity,” said Denny McGuirk, president and CEO of SEMI. “We expect capital spending to post growth throughout the remainder of 2015 and into 2016.”

Taiwan is forecast to continue as the world’s largest spender with $10.9 billion estimated for 2015 and $10.0 billion for 2016. In 2015, South Korea is second at $8.6 billion, followed by North America at $6.5 billion. For 2016, these three regions are expected to maintain their relative rankings.

In 2015, year-over-year increases are expected to be largest for South Korea (25 percent), Taiwan (16 percent), Europe (14 percent), and Japan (13 percent). Projected year-over-year percentage increases for 2016 are largest for Europe (26 percent increase), China (19 percent), South Korea (8 percent), and Rest of World (7 percent).

TUESDAY, JULY 14, 2015

9:00 am – 10:00 am
OPENING KEYNOTE PANEL: Scaling the Walls of Sub-14nm Manufacturing
Panel moderator: Jo de Boeck, Senior Vice President, Corporate Technology, imec
Keynote Stage, Room 135, North Hall E

10:00 am – 12:35 pm
STS Session: Semiconductor Manufacturing: Current Challenges and Future Opportunities for the Semiconductor Supply Chain
SESSION PARTNER: SEMATECH
Moscone North, Hall E, Room 131

10:30 am – 12:30 pm
What’s Next for MEMS?
TechXPOT South, South Hall

11:10 am – 12:45 pm
SILICON INNOVATION FORUM: Start-Up Pitches
Moderator: Dr. Pradeep Haldar, Vice President of Entrepreneurship, Innovation and Clean Energy Programs at SUNY Polytechnic Institute, Interim Dean of SUNY Poly’s College of Nanoscale Engineering and Technology Innovation, Chief Operating and Technical Officer of the U.S. Photovoltaic Manufacturing Consortium (USPVMC) in partnership with SEMATECH

1:30 pm – 3:30 pm
MATERIALS SESSION: Contamination Control in the Sub-20nm Era
Hosted by SEMI CGMG Committee
TechXPOT South, South Hall

2:00 pm – 4:30 pm
STS Session: Packaging: “Digital Health and Semiconductor Technology”
SESSION PARTNER: CPMT
Moscone North, Hall E, Room 133

semicon west

By Pete Singer, Editor-in-Chief

Major inflection points at logic, memory, foundry and display customers are creating a great future for Applied Materials, said president and CEO Gary Dickerson, speaking at an analyst meeting on Monday.

In opening remarks, Dickerson chose not to mention the recently failed merger between Applied Materials and TEL. Instead, he described how key inflection points are being enabled by new materials technologies. “Those inflections are enabled by materials innovation. New structures and new materials in semiconductors and displays create great, great opportunities for Applied,” he said.

He also pointed to new product launches that target these opportunities. This week, Applied Materials launched a new ALD system, as well as a new etch system. Both systems are based on completely new platforms.

Dickerson said the new transitions or inflection points are “the biggest that we’ve seen in decades.” He also said the rate of change is faster than he’s ever seen. “When you look at what they need to do for higher performance, longer battery life and better visual experience at the right cost, the technologies to enable those major inflections are bigger than we have ever seen in this industry,” he said.

“When you think about mobility or automotive or IoT or wearables, the pace of the technology changes are very, very fast,” he said. “You either hit these windows or you’re out for those products,” he added. He said hitting these narrow windows was “life or death for our customers.”

About a year ago, Applied Materials formed a Patterning Group, led by Prabu Raja, group vice president. The group handles etch, CVD, selective material removal and ALD. “The growth there has been tremendous,” Dickerson said.

Dickerson said they have moved $400 million of investment in the company into these opportunities and into new products.

This week, Applied Materials launched the Centris Sym3 Etch system, featuring an entirely new chamber for atomic-level precision manufacturing. The Centris Sym3 etch chamber employs a unique True Symmetry technology with multiple tuning controls for optimizing global process uniformity to the atomic level. Key to the design is a focus on controlling and removing etch byproducts, which are increasingly hampering within-chip patterning uniformity.

The company also launched a new Olympia atomic layer deposition (ALD) system that features a flexible and rapid process sequence vital for controlling the more complex chemistries needed to develop the next generation of ALD films. Further, the modular design creates complete separation of chemistries, eliminating the pump/purge steps of conventional ALD technologies for improved productivity.

By Jeff Dorsch, Contributing Editor

Presentations at the SEMI/Gartner Market Symposium on Monday afternoon could be summed up in two words: Uncertainties Ahead.

That was part of the title for the presentation by Bob Johnson, a research vice president at Gartner. Currency volatility, with multiple currencies contending with a strong dollar, is expected to continue in the short term, he said.

“This affects everyone in the electronics supply chain,” Johnson said.

Jim Walker, another Gartner research vice president, earlier said China is in for a “hard landing,” after a spectacular run-up in equities traded on the Shanghai Stock Exchange in the past year, followed by a crash last month.

“The U.S. economy is the bright spot,” he said. “Businesses and households are spending more.” Those U.S. expenditures are cautious, he added.

The keynote address was by Ian Ferguson, vice president of segment marketing at ARM Holdings. “The semiconductor industry is consolidating,” he said. “A lot’s going on. The pace is accelerating.”

Regarding the Internet of Things, Ferguson said, “Just because it’s connected doesn’t make it a good idea.” He divided the IoT market into consumer, commercial, and industrial segments.

For the near future of the IoT, he predicted there will be “a significant security scare,” which will bring on more security precautions. Second, “people will stop discussing things as smart devices,” Ferguson said. Instead of smart refrigerators and smart televisions, there will be just refrigerators and televisions, he noted. Finally, “new connected things will interface to multiple subsystems,” he concluded.

Johnson said solid-state drives will be a significant driver of growth, especially boosting NAND flash memory devices.

The DRAM market is set for an oversupply situation with the additional capacity coming on line, which will be followed by price declines, according to Johnson.

In contrast, NAND flash is “the bright spot” in the semiconductor industry, “due to SSDs gaining traction,” Johnson said.