Category Archives: Semicon West

By Jeff Dorsch, Contributing Editor

The era of three-dimensional chips is upon us.

At the Design Automation Conference last month in the Moscone Center, I saw a Hybrid Memory Cube in the booth of Open-Silicon in the South Hall. There before me was technology I had read about for years, without witnessing it in person.

The Hybrid Memory Cube, High-Bandwidth Memory technology, and logic parts such as Intel’s Xeon Phi “Knights Landing” microprocessor are leading examples of 3DIC technology. Meanwhile, other advances in packaging – chip-scale packages, copper pillar bumping, fan-in wafer-level packaging, flip-chip ball grid arrays, and wafer-level fan-out packages, among others – are gaining in adoption.

The Semiconductor Technology Symposium during SEMICON West 2015 will include two sessions devoted exclusively to advanced packaging on Tuesday, July 14. Packaging: The Very Big Picture is scheduled for 10 a.m., while Packaging: Digital Health and Semiconductor Technology will commence at 2 p.m.

SEMI reported packaging materials represented $20.4 billion in worldwide sales during 2014. That figure was essentially flat with 2013. SEMI noted that if bonding wire were excluded from the segment, sales would have been up more than 4 percent from the previous year. “The continuing transition to copper-based bonding wire from gold is negatively impacting overall packaging materials revenues,” SEMI stated.

McKinsey & Co. last year published a report on advanced packaging technologies that estimated the number of integrated circuits containing 2.5DIC and 3DIC technologies will increase from about 60 million units in 2012 to more than 500 million units in 2016.

“There still is a lot of uncertainty in the market about 2.5DIC and 3.0DIC technologies – for instance, when and how exactly to adopt these newer packaging configurations, who will dominated among the players, and the role China will play,” the authors of the report wrote.

Through-silicon vias figure in many 3DIC schemes, while silicon interposers are often regarded as a bridge to 3DIC technology and called 2.5DIC packaging. Ed Korczynski, senior technical editor of Solid State Technology magazine, wrote last month about recent developments in 3DIC technology.

The emergence of advanced packaging and 3DICs hasn’t escaped the attention of semiconductor equipment vendors, of course. KLA-Tencor in April introduced two systems – the CIRCL-AP for characterization and modeling of wafer-level packaging processes and the ICOS T830 for automated optical inspection of IC packages with 2D and 3D measurements. Both products are already installed in facilities around the world.

“Advanced packaging technologies offer device performance advantages, such as increased bandwidth and improved energy efficiency,” Brian Trafas, KLA-Tencor’s chief marketing officer, said in a statement. “The packaging production methods, however, are more complex – involving the implementation of typical front-end IC manufacturing processes, such as chemical mechanical planarization and high-aspect-ration etch, and unique processes, such as temporary bonding and wafer reconstitution.”

For 2014, Amkor Technology reported that “advanced products” accounted for $1.553 billion in revenue, or 49.6 percent of the company’s total revenue. That figure has steadily risen over the past three years.

Phil Garrou, a senior consultant for Yole Developpement, speaking last December at a symposium in Burlingame, Calif., took a hardline position on the subject of 2.5D technology. “It’s 2D or 3D,” he said, with nothing in between. “Interposers are packages,” he added.

Wherever you stand on 2D, 2.5D, or 3D, there will be much to discuss at SEMICON West this week.

Genmark Automation, a developer of tool and factory automation solutions for the semiconductor and related industries, today announced the launch of its new CODEX Stocker. The CODEX Stocker integrates stocking, sorting and metrology functions in a single tool that stores and delivers various substrates on demand, of defined quality and in defined numbers. Consolidating the functions of these traditionally nonrevenue-generating tools frees up fab floor space for production equipment, enabling a facility to maximize its productivity and yield.

“There is a clear market opportunity for a high-quality, highly reliable tool that can enable the functions of sort, stocking and metrology simultaneously,” said Carl McMahon, President & EVP of Global Customer Operations at Genmark Automation. “Given the continual pressure to improve yield and productivity, the benefits of storing, measuring and tracking all media in one location, using less cleanroom floor space, quickly becomes evident.”

Key differentiators of the CODEX Stocker include:

  • Reduced overall tool footprint. Novel rotary “carousel” module, which increases the volume of substrates stored compared with existing rack systems, and allows the robot to access the wafers from a single side.
  • First library retrieval system for semiconductor manufacturing. Integrated stocker and metrology systems enable real-time measurement and data tracking. Storing all substrates in a single location allows for more effective tracking of the substrate life cycle.
  • Gantry robot to provide extended range and larger working envelope for wafer delivery.

“Beyond the traditional Si wafer market, the glass wafer for bond/debond, reticle and reticle box storage are important targets for this type of integrated system,” said McMahon. “Taking the glass wafers used in bond/debond as an example, concentricity, uniformity and thickness are very important. By stocking all media in one location with onboard metrology, you can easily make decisions on when the usable lifetime of a wafer is up and when to change it out, to consistently maximize productivity.”

The CODEX’s modular design is easily configurable to customers’ specific needs, whether integrated device manufacturers or original equipment manufacturers. A high-capacity system, it is performance-optimized for high throughput, has a configurable architecture and is readily expandable. For example, using 300mm wafers, each carousel can hold up to 1,700 wafers, depending on thickness. The tool supports 200mm, 300mm and 450mm wafers as well as reticles.

codex

CEA-Leti today announced its first results towards the demonstration of CoolCube’s feasibility in FinFET technology on its 300mm production line, and new CoolCube circuit designs that improve the trade off between area, speed and power.

Key process steps developed on 300mm wafers show progress in closing the gap between the demonstration of a single device and taking the technology to fabrication.

CoolCube is Leti’s sequential integration technology that enables the stacking of active layers of transistors in the third dimension. Under development for eight years, it aims at fully benefiting from the third dimension, and is enabled by cutting in half the thermal budget in manufacturing transistors, while maintaining their performance.

Mobile devices, where minimal power consumption is key, are the primary market for chips manufactured with the technology. CoolCube also allows designers to include backside imagers in the chips, and co-integration of NEMS in a CMOS fabrication process also is possible.

“CoolCube enables local via density that is 10,000 times higher than ‘standard’ 3D integration, because the technology is designed to connect stacked active layers at a nanometric scale,” said Maud Vinet, Leti’s advanced CMOS laboratory manager. “In the digital area, we expect this 3D technique to allow a gain of 50 percent in area and 30 percent in speed compared to the same technology generation in classic 2D – gains comparable to those expected in the next generation. In heterogeneous integration, we expect CoolCubeTM to be an actual enabler of smart-sensor arrays by allowing a close integration of sensors, detection electronics and digital signal processing.”

Leti’s team will be in the European Pavilion, South Hall, Booth #2317, during SEMICON West.

Leti feature 1

Leti’s CoolCube is made possible by sequential integration.

By Jeff Dorsch, Contributing Editor

While the lithography equipment market sometimes seems like A Tale of Two Cities, it’s more complicated than that. The basic fact is that the semiconductor industry is soldiering on with 193-nanometer immersion lithography technology and multiple-patterning exposures while extreme-ultraviolet lithography continues its long-aborning development.

ASML Holding is the leading vendor in the EUV lithography field, and it’s also a big supplier of 193nm immersion lithography systems. The industry consensus now seems to be that the near future will see the combined use of EUV and immersion, possibly at the 10-nanometer process node and definitely at the 7nm node. Beyond that, it’s anyone’s guess.

ASML had big news to reveal at the SPIE Advanced Lithography Symposium in February. Taiwan Semiconductor Manufacturing had successfully exposed 1,022 wafers within 24 hours on ASML’s NXE:3300B EUV system, with sustained power of more than 90 watts from the scanner’s power source.

In April, ASML reported that “one of its major U.S. customers” had agreed to order at least 15 EUV systems. Industry speculation on the unidentified customer quickly centered on Intel. The Dutch company has been relatively quiet since then.

Hans Meiling, ASML’s vice president of service and product marketing EUV, notes the progress that the company has made in the past year, but didn’t offer any new information on its EUV program. ASML’s EUV scanners will be “meeting production requirements within a couple of years,” he says.

“We want to get to 70 percent availability and 1,000 wafers per day,” Meiling says, and not just in a one-day test at TSMC. The goal is to provide that kind of productivity and throughput for all EUV customers, he adds.

In 2016, ASML is aiming for a daily throughput of 1,500 wafers, according to Meiling. “We have a large program internally to support that,” he says.

To make its EUV scanners productive and production-ready, ASML has developments on several fronts, Meiling notes. “It’s a multifaceted introduction of not only the scanner,” he says, taking in photomasks, photoresists, and pellicles.

Progress has been made in detecting and reducing defects in EUV mask blanks, Meiling reports. It seems likely that Intel, Samsung Electronics, and TSMC will each make their own EUV masks, he says.

When it comes to resists, “we don’t control the ecosystem,” Meiling says. “We’re monitoring this.” Resist suppliers are “continually improving critical-dimension quality” and providing “faster resist without losing the imaging capability,” he states.

Even “beautiful masks,” near-perfect photomasks, “have to have a pellicle to protect them,” Meiling observes. “Light goes through the pellicle twice,” he notes, and the pellicle’s membrane must be very thin as a result. ASML began work on a EUV pellicle two years ago and has developed a removable pellicle. The company has achieved “full mask coverage” with its pellicle and is going through an initialization phase on producing them, according to Meiling.

The ASML executive ticks off the attributes of EUV – single exposures of chips, reduction of process complexity, and the capability to deal with the complexity of chip layers. “Customers are finding out with multipatterning, it’s becoming more and more difficult,” Meiling says. “It’s very difficult for certain layers in the chip stack.”

For all the publicity about EUV, ASML is constantly improving its deep-ultraviolet lithography scanners as well, he notes. “Immersion is our workhorse,” Meiling says. “We’re tightening requirements brought to us by customers.”

Stefan Weichselbaum, ASML’s director of product marketing DUV, says the company is committed to “holistic lithography” – looking beyond scanner performance and integrating a metrology environment. Most of all, ASML wants to keep DUV/immersion machines affordable, and “the most simple thing we can do is improving the output,” he says.

Currently capable of processing 250 wafers per hour, the NXT:1980 scanner will be boosted to 275 wafers per hour during the second half of this year, according to Weichselbaum. Among other improvements, ASML has debuted feed-forward corrections, reticle cooling, and wafer-by-wafer correction for higher-order reticle distortion in the NXT:1980. “If we can manage it through software, we will,” he adds.

Donis Flagello, president, CEO, and chief operating officer of Nikon Research Corporation of America, acknowledges that immersion with co-exist with EUV at some point, as ASML and others contend.

“EUV is probably not going to go away,” he says, while adding, “It’s not going to take over.”

Nikon does analysis on EUV technology and the state of the art in immersion lithography; the company is focused on 193nm and “pushing to get the costs down,” Flagello says.

“Demand is still strong” for 193nm machines, he reports. “The entire Internet runs on semiconductors.” Still, “the semiconductor industry is mature” and consolidating, Flagello says. “We can see it in conferences.”

Immersion lithography presents its own challenges in masks and resists, the Nikon executive notes. “We can afford to pump more power into the system,” Flagello says. “We have to control the lenses better.”

While EUV has a long, well-known history of delays and problems, the industry transition to 193nm lithography wasn’t an easy one, either, according to Flagello. “There was lots of stuff we didn’t expect,” he says.

There are alternatives to 193nm and EUV lithography, such as directed self-assembly, direct-write electron-beam, and nanoimprint lithography. DSA “would be complementary” to the mainstream lithography technologies, and the others have their disadvantages, Flagello says.

An Steegen, imec’s senior vice president of process technology, says, “Multipatterning is the most cost-effective way.” With “cheaper materials,” the costs of multipatterning can be further reduced, and “there are lots of efforts here at imec and our suppliers,” she adds.

Immersion lithography can be extended to the 10nm and 7nm process nodes, Steegen says. With EUV, “you can replace multipatterning exposures with one exposure,” she notes.

The industry roadmap calls for EUV insertion into production in 2017, Steegen says. EUV source power is “almost everywhere running at 80 watts,” she adds, and uptime has been improved. “The whole EUV ecosystem is coming together,” Steegen notes, with progress in EUV photomasks and photoresists.

Directed self-assembly is “a complementary patterning technology,” the imec executive says. “We always keep an eye on all the alternatives.” While imec has succeeded in improving DSA, “we are not having huge activities around these areas,” such as multi-beam E-beam and nanoimprint, Steegen says.

“We’re getting smarter, combining multipatterning and EUV,” she adds.

One issue that concerns her is the use of FinFETs in current and future process nodes. “How far can we push those? When will they break?” she asks. “How tall can we make the FinFET? Beyond 5 nanometers? The taller, the better.”

Another area where lithography is progressing is in the field of advanced packaging. Doug Anberg, vice president of advanced stepper technology at Ultratech, says wafer bumping and other packaging technologies are “still progressing forward. We’re seeing a lot of activity in that area.”

Thomas Uhrmann, director of business development for EV Group, says “there is a lot of traction” in lithography for advanced packaging. His company plans to exhibit a nanoimprint platform tool at SEMICON West, intended for making light-emitting diodes and Internet of Things devices.

In summary, there are lots of developments in lithography, along with lots of challenges and lots of questions. And so it goes.

SEMI today announced the cornerstone safety Standard S2 (Environmental, Health, and Safety Guideline for Semiconductor Manufacturing Equipment) will be updated this month. SEMI S2 is one of the most widely-used safety-related documents in the industry. SEMI S2 provides a set of performance-based environmental, health, and safety (EHS) guidelines for semiconductor manufacturing equipment.

EHS--shutterstock_264365318

SEMI International Standards are consensus-driven industry-specific guidelines and specifications for the semiconductor supply chain. Use of standards decreases manufacturing costs and increases productivity and industry efficiency by reducing or eliminating duplication of efforts. Virtually every major semiconductor company globally includes equipment safety-related requirements in their purchasing specification, typically SEMI S2.

Used in the industry for over 25 years, the SEMI S2 Guideline is the result of significant efforts by the volunteer experts in SEMI’s International Standards Program. SEMI S2 is periodically updated and revised by a Standards Task Force consisting of device makers, equipment manufacturers, material makers, and other engaged communities (academia, consortia, associations, etc.). SEMI S2 covers 22 specific EHS categories, including regulatory requirements; electrical, mechanical, fire, chemical, radiation, noise, and ergonomics hazards; emergency shutdown, ventilation, and exhaust specifications; hazard warnings and more.

SEMI S2 is on a targeted release schedule with revisions effective once every three years, not immediately upon approval. The upcoming release in July 2015 will contain all changes approved since July 2012; the next milestone release of SEMI S2 is scheduled for July 2018.

This SEMI S2 release will include the following updates, effective July 2015:

  • Section 3.3 Revision (Limitations Section)
  • Addition of a new Related Information section (Additional Guidance for Safety Functions)
  • Revision to Optical Radiation Criteria
  • Revisions related to Fire Detection Manual Activation and Fire Suppression Manual Activation
  • Revision to Chemical Exposure Criteria Reporting and Fire Detection/Suppression Annunciators

Updates to SEMI S8 (Safety Guidelines for Ergonomics Engineering of Semiconductor Manufacturing Equipment)and SEMI S22 (Safety Guideline for the Electrical Design of Semiconductor Manufacturing Equipment) are also on the same three-year targeted release schedule. SEMI S8 will reflect changes to terminology for critical controls as well as several updates to the Supplier Ergonomic Success Criteria (SESC) Checklist including: “Actual/Conforms?” Column Modifications; Ball Handle Minimum Diameter; Hand Control Location Applications; Hand Control Location Pictogram Addition. SEMI S22 will include revisions to facilities electrical connection, protection against risk of electrical fire, and testing.

For more information on SEMI International Standards, please visit www.semi.org/en/Standards. To purchase SEMI S2 updates, SEMI (www.semi.org) offers SEMIViews ─ an annual subscription-based product for online access to all SEMI Standards. SEMIViews includes Standards in English (the official language) as well as selected Standards in Japanese, Traditional Chinese, and Korean.

SEMI North American Standards meetings will be held at SEMICON West 2015, starting on July 13. For more information on the standards meetings in San Francisco, visit www.semi.org/node/55801. In addition, many other upcoming SEMI Standards meetings are scheduled; please visit www.semi.org/en/Standards/CalendarEvents.

By Jeff Dorsch, Contributing Editor

Plasma etching is a key step in wafer fabrication, from deposition to the patterning of photolithography to dry or wet etch. As such, it is a crucial and hotly-contested area for vendors of semiconductor manufacturing equipment.

Lam Research holds about half of the worldwide etch equipment market and principally competes with Applied Materials, Tokyo Electron, and Hitachi High-Technologies.

In May, Lam introduced the Kiyo F Series conductor etch system for volume production of advanced DRAMs and 3D NAND flash memory devices. Lam says the Kiyo F Series is employed for critical conductor etch applications at “all major memory manufacturers.”

A year ago, Lam brought out the 2300 Kiyo F Series with the Hydra Uniformity System, which corrects for critical-dimension non-uniformities on the incoming wafer. The company also unveiled an atomic layer etch (ALE) capability on the 2300 Kiyo F Series conductor etch system, which is paired with Lam’s atomic layer deposition (ALD) systems, the VECTOR ALD Oxide system for dielectric film ALD and the ALTUS system for tungsten metal film ALD.

Applied Materials and Tokyo Electron set plans in 2013 to merge their companies. The merged company, to be called Eteris, would have commanded about one-third of the worldwide etching equipment market. The merger was called off in April, however, as U.S. antitrust regulators indicated that they would not approve the transaction.

SEMI cheered a decision by the U.S. Department of Commerce in February to remove export controls on certain etch equipment, concluding a four-month investigation. SEMI had petitioned the federal government agency in July 2014 to look at the foreign availability of anisotropic plasma dry etching equipment.

“SEMI stands for free trade and open markets to support the development and success of the global semiconductor manufacturing industry supply chain,” Denny McGuirk, president and CEO of SEMI, said in a statement. “We applaud the decontrol of semiconductor etch equipment as a rational response to current technology, trade, and commercial realities. This is a win for both equipment makers and their customers operating in the global market.”

“The Commerce Department’s decision to remove export control restrictions for etch equipment is a big victory for the U.S. semiconductor equipment sector and our customers around the world,” said Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials. “Recognizing the availability of these tools will help fuel growth and promote the success of the global industry supply chain.”

In May, imec and Tokyo Electron presented a direct copper etch scheme for patterning copper interconnections. This would replace the usual copper damascene process, according to imec and TEL. The Belgian research organization worked with nine leading chipmakers on developing the direct copper etch technology.

Dry or wet, etching technology will be the subject of discussions at the SEMICON West 2015 conference and exhibition.

By Jeff Dorsch, Contributing Editor

There are four main segments in the thin-layer deposition equipment market – atomic layer deposition, chemical vapor deposition, epitaxy, and physical vapor deposition, also known as sputtering.

As the semiconductor industry powers through the 14-nanometer process generation, interest is keen on how researchers and suppliers will improve the current crop of deposition equipment to meet the requirements of the 10nm and 7 nm nodes.

The long-pending merger of Applied Materials and Tokyo Electron into a company to be called Eteris, called off in April due to regulatory issues, would have created a mighty deposition vendor, holding nearly 60% of the worldwide market. Applied still holds a commanding share of the deposition market, yet will have to contend with Lam Research (which acquired Novellus Systems in 2012), AIXTRON, ASM International, and other competitors.

Global Industry Analysts (GIA) forecasts the global deposition equipment market will hit $13.6 billion by 2020. Atomic layer deposition (ALD) will be the fastest growing segment, with a compound annual growth rate of 19.9 percent, the market research firm estimates.

Chemical vapor deposition (CVD) will be the second largest deposition segment through the end of this decade, followed by physical vapor deposition (PVD) and epitaxy, according to GIA. Japanese vendors, namely Hitachi Kokusai Electric/Kokusai Semiconductor Equipment and Tokyo Electron, dominate the worldwide CVD market, with significant market shares held by Applied Materials, ASM International, and Lam Research, the market research firm states.

Taiwan is the world’s largest market for deposition equipment, Global Industry Analysts says. That’s not surprising, since SEMI estimates that Taiwanese semiconductor manufacturers will spend about $10.5 billion on wafer fabrication equipment this year, representing nearly 30 percent of worldwide spending on fab equipment in 2015. GIA sees China being among the fastest-growing markets for deposition, with a CAGR of 15.1 percent.

In May, Applied Materials introduced the Applied Endura Cirrus HTX PVD system for making titanium nitride hardmask films, targeting applications in fabricating semiconductors with 10nm and 7nm features.

A year ago at SEMICON West, the company debuted the Applied Producer XP Precision CVD system, which it said supports the industry transition to 3D NAND flash memory devices by providing nanometer-level layer-to-layer film thickness control for critical-dimension uniformity across a wafer.

July of 2014 also saw Lam Research unveil its VECTOR ALD Oxide system to produce conformal dielectric films defining critical pattern dimensions in multiple patterning.

SEMICON West 2015 is expected to see announcements on new products and research in the deposition equipment field.

By Jeff Dorsch

Chemical mechanical planarization (CMP) technology has been around for a long time. In addition to the semiconductor industry, CMP has applications in data storage, polishing the rigid disks and magnetic heads of hard-disk drives.

Those interested in learning about developments in CMP for hard drives and integrated circuits would do well to attend the CMP Technical and Market Trends session on Thursday, July 16, at 11 a.m. in the TechXPOT North area of Moscone Center’s North Hall. Representatives of Intel, HGST, Entegris, TDK, and other companies will be speaking.

While 450-millimeter wafers haven’t been much in the news this year, Thursday’s session will include a presentation by the Global 450 Consortium, with speakers from the College of Nanoscale Science + Engineering (CNSE) and SEMATECH.

CNSE is part of the SUNY Polytechnic Institute in Albany, N.Y., which also contains the Chemical Mechanical Planarization Center, a joint program with SEMATECH. Mitsubishi Chemical joined the program this spring.

While CMP is still used for its traditional polishing applications for interlayer dielectrics, it’s also finding employment in more advanced applications, such as bulk oxide polishing, shallow trench isolation, “stop on poly” isolation, and polishing of various dielectrics in advanced transistor designs.

CMP includes consumable products, polishing pads and slurries. Dow Chemical is the leading vendor in polishing pads, while Cabot Microelectronics dominates the CMP slurry market.

Late last month, Applied Materials and Cadence Design Systems announced that they are collaborating on optimizing the CMP process through silicon characterization and modeling for ICs with 14-nanometer features, and beyond that process node. Cadence, one of the leading vendors of electronic design automation software and services, will provide its CMP Predictor and CMP Process Optimizer tools. Applied will employ its Reflexion LK Prime CMP system.

“From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster,” Derek Witty, vice president and general manager of Applied’s CMP Products Group, said in a statement.

Whatever your level of expertise in CMP, SEMICON West 2015 will help you polish up your knowledge of the field.

By Christian Dieseldorff and Lara Chamness, SEMI

We, in the semiconductor supply chain, are constantly immersed in detailed numbers. It’s important to pull back and look at the major trends that have profoundly changed and are reshaping our industry.

Data from SEMI World Fab Forecast reports

1997

2002

2007

2012

2017
Global Volume Fab Count
Number of Fabs WW 

682

802

849

861

864
Number of Fabs WW (excluding discrete and LED)

472

508

499

440

440
Global Volume Fabs by Wafer Size
Number of volume 200mm fabs (excluding discrete and LED)

111

170

173

152

149
Number of volume 300mm fabs (excluding discrete and LED)

0

13

62

81

109
Global Fab Capacity by Device Type
Fab Capacity (200mm equiv. thousand wafer starts per month)

5,655 

7,519 

15,441 

18,068 

20,609 

Memory

20%

19%

36%

29%

27%

Foundry

13%

19%

18%

27%

30%

MPU&Logic

35%

31%

22%

17%

16%

Analog, Discretes, MEMS & Other

32%

31%

24%

27%

26%
Largest Regional Fab Capacities
Fab Capacity Regional Trends (excluding discrete and LED)

Largest installed capacity

Japan

Japan

Japan

Japan

Taiwan

Second largest installed capacity

Americas

Americas

Taiwan

S. Korea

S. Korea

Third largest installed capacity

Europe

Europe

S. Korea

Taiwan

Japan
Source: SEMI (www.semi.org) 

The table shows that the largest increase of new fabs occurred in the time frame from 1997 to 2002 with 18 percent growth rate. The growth rate drops to 6 percent from 2002 to 2007, 1 percent from 2007 to 2012 and flat from 2012 to 2017. This drop in change rate does not mean that there are no new fabs being built but is explained by fabs closing. There are still new fabs being built ─ especially for 300mm ─ but the rate of fabs closing is overshadowing this fact. From 2007 to 2012 alone over 150 facilities closed with majority from 2008 to 2010.

With the rise of 300mm at begin of the millennium we see a rapid increase of 300mm fabs from 2002 to 2007 with 380 percent and at the same time a decrease of new 200m fabs from 50 percent to 2 percent. From 2007 to 2012 more 200mm fabs were closed but this trend is slowing. With emerging IOT demand, 200mm fabs will be part of the capacity mix for the foreseeable future.

Fueled by the fabless or “fab lite” movement, we see that the foundry era has a strong and steady growth since begin of its era in the 90s. By 2017, foundry capacity will have surpassed memory with 30 percent of the total capacity.

Both foundry and memory mainly use 300mm wafers which contribute to the large increase in capacity. The other sector MPU & Logic uses mainly 300mm but there are still fabs with wafer sizes of 200mm or less. While the Logic sector is increasing in capacity with System LSI applications, we see a decline for MPU which contributed to the decline in share.  Although we see an increase of capacity for sensors and analog/mixed signal, the sector combined as “Analog, Discretes, MEMS & Others” shows modest growth mainly because the wafer sizes used are 200mm and below which contributes to the less share of capacity.

For decades Japan was the leader in installed capacity which will have changed by 2017 when Taiwan will have taken over the highest capacity spot.  Japan is restructuring business models and approaching a more fab-lite to fabless model.  Korea is mainly driven by Samsung and is benefitting from the mobile business using memory and System LSI chips.

For more information on market data, visit www.semi.org/en/MarketInfo and attend an upcoming SEMICON: SEMICON West 2015 (July 14-16) in San Francisco, Calif; SEMICON Taiwan 2015 (September 2-4) in Taipei, Taiwan; SEMICON Europa 2015 (October 6-8) in Dresden, Germany; SEMICON Japan 2015 (December 16-18) in Tokyo, Japan.

By Debra Vogler, SEMI

If you attended just about any mask making conference in the last five to seven years, you would have heard the lament about exploding data volumes and their impact on mask writing time and, by extension, mask costs. The industry is still concerned with data volumes, whether 193nm immersion or EUVL. “Data volume is significantly increased node by node and requires a faster data transfer rate,” Jongwook Kye, director of the Strategic Lithography Technology Group at GLOBALFOUNDRIES, told SEMI. “We have to support data transfer across multiple continents, and that is a bottleneck.”

So it’s not just that masks are getting more complicated – with large data volumes – but it’s how the data gets transferred from one continent to the other that is becoming more challenging. “Even if you improved the mask writing time, with a multiple e-beam mask writing tool, the problem is still the data transfer rate.” On the subject of multiple e-beam writing tools, Kye noted that they aren’t currently available, and investment in the technology has not been aggressive, so the challenges remain even as the industry goes from node 10 down to node 5. Kye will present at SEMICON West 2015 (July 14-16) in the July 15 Lithography session during the Semiconductor Technology Symposium.

Kye pointed to another sector – the Internet of Things (IoT) – as having the potential to unlock solutions for the data volume/data transfer rate conundrum. “The IoT folks want to solve the data collection problem that arises from having trillions of sensors,” said Kye. “Once the infrastructure is there [to collect sensor data], those solutions can be transferred in some manner to fit the data transfer needs of the mask writing industry.”

One key factor that has changed over the years is that now, edge placement error (EPE) is the most important parameter of concern for lithography, noted Kye (Figure 1). “In traditional lithography, we tried to control overlay (OL) and CDU (critical dimension uniformity),” said Kye. “These days, the OL and CDU are no longer independent parameters, so we unify them together in one word and call it edge placement error.”

Christopher Progler, VP and CTO at Photronics, Inc., told SEMI that, today, EUV masks are being produced that are suitable for wafer technology development and production in limited applications. One relatively new development – pellicles for EUV masks – has taken a major step forward. “The ecosystem is rapidly responding to this new requirement,” noted Progler. “Despite this progress, however, EUV represents a very different mask technology overall when compared to even the most advanced 193nm masks. This presents the industry with new challenges and learning cycles on the path to delivering high yielding production EUV masks.” All in all, however, Progler observed that EUV mask infrastructure continues to advance with progress in a number of critical areas including blank defects, patterning modules, cleaning and validation.

“EUV mask defects will be handled using essentially a multi-sensor approach of inspection and characterization methods knitted together to form sound decisions on an EUV mask for use in particular applications,” Progler told SEMI. He anticipates that eventually, a high-speed, full-field actinic mask inspection tool will be delivered. “Such capability can be enabling for broad adoption of EUV masks, and therefore, EUV lithography.” Progler, however, believes that parallel plans are needed, “One that optimizes and calibrates the multi-sensor approach, and also the collaborative development of the full-field actinic inspection system.”

Addressing the need for greater speed over and above those of single-beam writing tools, Progler told SEMI, “There are a number of mask writer programs underway that would employ a writing engine instead comprised of an array of beams, thereby enabling faster writing time and improved flexibility for real-time pattern correction.” He noted that Photronics has been engaged in an equipment development program at IMS nanoFabrication alongside other industry partners to bring about this type of technology solution.

Rounding out the industry’s “to-do” list for EUVL, the mask industry also faces a challenge in the area of “so-called mask matching.” “Mask matching comprises methods to ensure two masks really are functionally identical for the given use,” Progler told SEMI. “So, driving integrated inspection/metrology/characterization solutions that ensure two masks work equivalently in a given application will continue to evolve.”

In addition to Kye (GLOBALFOUNDRIES) and Progler (Photronics), presenters from Nikon Research, ASML, Canon Nanotechnologies, Sematech and CEA Leti will be featured at the “Making Sense of the Lithography Landscape” (a Semiconductor Technology Symposium session) at SEMICON West 2015, which will be held July 14-16 at Moscone Center in San Francisco, Calif.