Category Archives: Semicon West

By Ed Korczynski 

Global industry R&D hub IMEC defines the “IMEC 7nm-Node” (I7N) for finFETs to have 56nm Contacted Gate Pitch (CGP) with 40nm Metal Pitch (MP), and such critical mask layers can be patterned with a single exposure of 0.33 N.A. EUVL as provided by the ASML NXE:3400B tool. To reach IMEC 3nm-Node (I3N) patterning targets of ~40 CGP and ~24 MP, either double exposure of 0.33 N.A. EUVL would be needed or else single-exposure of 0.55 N.A. EUVL as promised by the next-generation ASML tool. All variations of EUVL require novel photoresists and anti-reflective coatings (ARC) to be able to achieve the desired patterning.

The Figure shows that IMEC has led tremendous progress on the photoresists, with best resolution in a single 0.33 N.A. EUVL exposure of 13nm half-pitch (HP) line arrays. The most important parameter for the photoresist is the sensitivity target of 20 mJ/cm2, but at that dosage the best materials seen today have unacceptably high line-width roughness of >5nm three-sigma.

“If you’re talking about lines of 16nm width, for 3-sigma you want to be less than 3nm line-width-roughness,” explained Steegen during the 2017 IMEC Technology Forum. “Smoothing techniques are post-develop technologies that basically reduce line-width-roughness. We are working with many partners, and all are making progress in reducing line-width roughness though post-develop techniques.”

Top-down SEM images of the best achieved EUVL resolutions using 0.33 N.A. stepper and Chemically-Amplified Resist (CAR) or metal-oxide Non-Chemically-Amplified Resist (NCAR) formulations, along with post-development “smoothing” technologies to improve the Line-Width Roughness (LWR) to meet target specifications. (Source: IMEC)

Top-down SEM images of the best achieved EUVL resolutions using 0.33 N.A. stepper and Chemically-Amplified Resist (CAR) or metal-oxide Non-Chemically-Amplified Resist (NCAR) formulations, along with post-development “smoothing” technologies to improve the Line-Width Roughness (LWR) to meet target specifications. (Source: IMEC)

The Figure also shows that IMEC has been working with vacuum deposition companies on atomic-layer deposition (ALD) or chemical-vapor deposition (CVD) processes to ideally take off 2 nm of sidewall roughness. Plasma energy may be capacitively- or inductively-coupled to a vacuum chamber to allow for either PEALD or PECVD processing. Such precise atomic-scale processing may be composed of “dep/etch” sequences of one/few atomic layer depositions followed by light plasma etching such that the nominal line-width would not necessarily change. However, this approach necessitates that the wafer leave the lithography track and move to a separate vacuum-tool.

To save on cost and time, LWR smoothing may be accomplished to some extent today in the litho track by specialized spin-on materials. Companies that supply lithography resolution extension (EXT) materials such as spin-on hard masks (SOHM) and anti-reflective coatings (ARC) have looked at ways spin-on materials can improve the LWR of post-developed resist lines. This can be combined with “shrink” materials that add controlled thicknesses to sidewalls of holes, or with “trim” materials that subtract controlled thicknesses from the sidewalls of lines. Generally, some manner of complex chemical engineering is used to create a film that either forms or breaks bonds when thermally driven by a bake step, and after image transfer to underlying SOHM layers the shrink/trim material is typically stripped in a solvent such as propylene glycol methyl ether acetate (PGMEA).

EUVL photoresists may be based on metal-oxide nano-particles, instead of on extensions to the Chemically-Amplified Resist (CAR) formulations that have been mainstays of ArF/ArFi lithography for decades. Inpria Corp.—the 10-year-old-start-up supported by industry—has ultimately developed a tin-oxide family of blends that are shown as the Non-Chemically-Amplified Resist (NCAR) in the Figure. NCAR metal-oxide resists show similar LWR at similar exposure doses to CARs. However, the metal-oxides in the NCAR can often replace SOHM materials, saving cost and complexity in the resist stack.

IMEC’s work on EUVL with ASML steppers leads to the belief that the source power will increase to allow throughput to rise from today’s ~100 wph to ~120 wph by the end of this year. However, those throughputs assume 20mJ/cm2 resist-speed, and masks may require 30 mJ/cm2 target exposures even with post-develop smoothing steps.

[DISCLOSURE: Ed Korczynski is also Sr. Technology Analyst with TECHCET Group, and author of the Critical Materials Report: Photoresists and Extensions and Ancillaries 2017”.]

SEMI announced the recipients of the 2017 SEMI Awards for the Americas today. The awards honor: a team from Micron Technology (Micron) for the development of the hybrid memory cube and their leadership in co-founding the Hybrid Memory Cube Consortium, and Bryan Black from Advanced Micro Devices for integration of the “Fiji” 3D-IC graphics processor product. The awards were presented at SEMICON West 2017 today.

SEMI Awards recognize technology developments that have had a major impact on our industry and the world.  The 2017 award recipients share the distinction of having pioneered processes and integration breakthroughs that enabled the first high-volume production of 3D memory and the integration of 3D memory into the first high-volume production of 3D Systems-in-Package (SiP) products.

Use of the third dimension in 3D memory devices provides density and performance that are beyond the range of traditional 2D scaling.  Although efforts to use the third dimension have been ongoing for decades, the use of through-silicon-vias (TSVs) was critical to creating the technology foundation on which current devices are based. The work of Warren Farnworth and Salman Akram at Micron was essential to enabling the development of the “hybrid memory cube.” By 2011, Micron had developed the technology to the point where its technical potential was clear, but Scott Graham recognized that it would be a “niche product” ─ unless a community of device manufacturers, developers, and adopters followed a common interface specification. Micron made a bold move, teaming up with a major competitor (Samsung), to co-found the Hybrid Memory Cube Consortium. The Consortium now has 100+ members working to innovate and expand the capabilities of the next generation of memory-based solutions. For developing the Hybrid Memory Cube technology and their leadership in the establishment of the Hybrid Memory Cube Consortium, SEMI is proud to present Warren Farnworth, Salman Akram, and Scott Graham of Micron with the 2017 SEMI Award. Tom Eby, VP of Micron’s Compute and Networking Business Unit, accepted the award for Micron.

Advanced Micro Devices (AMD) also recognized the importance of collaboration in 3D SiP devices. A decade ago, AMD realized that advanced graphics processing would require major innovation in multi-die integration and increases in processor-memory bandwidth. To meet this challenge, AMD began a 10-year development process with its memory partner, SK-Hynix, and the system integrator, ASE. Their process drove advances in multi-die memory stacking and software standards as well as addressing the crucial challenges of thermal management and “intelligent reliability” for components operating at the edge of their design envelope. In 2015, AMD introduced the “Fiji” graphics processor which was made possible by an aggressive prototyping sequence that produced over 15 distinct product designs and involved over 20 contributing companies. More importantly, the AMD-led project produced a number of industry firsts:  the use of die-stacked memory in a graphics processor, the use of a high-volume interposer package in a graphics product, the integration of 22 discrete die into a package shipping millions of parts, and collaboration across the supply chain. These innovations would not be possible without the leadership of AMD. SEMI is honored to present Bryan Black, a senior AMD Fellow at AMD Austin, with the 2017 SEMI Award for the integration of the “Fiji” 3D-IC graphics processor.

“Every year SEMI honors key technological contributions and industry leadership through the SEMI Award. This year’s recipients were each instrumental in delivering technologies that will influence product design and system architecture for many years to come. Congratulations to both Bryan from AMD and the Micron team for their significant accomplishments,” said David Anderson, president, SEMI Americas.

“Both of the 2017 Awards recognize the enabling of high-volume manufacturing through collaboration with key vendors in the supply chain at AMD and by establishing a collaboration with competitors as well as the supply chain at Micron. These breakthroughs through collaboration set an example for acceleration of innovation in the future,” said Bill Bottoms, chairman of the SEMI Awards Advisory Committee.

The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The award is the highest honor conferred by SEMI Americas. It is open to individuals or teams from industry or academia whose specific accomplishments have broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of North American-based member companies of SEMI. For a list of past award recipients, visit www.semi.org/semiaward.

SEMI honored four industry leaders for their outstanding accomplishments in developing Standards for the electronics and related industries. The SEMI Standards awards were announced at the SEMI International Standards reception held during SEMICON West 2017.

The SEMI International Standards Excellence Award, inspired by Karel Urbanek, is the most prestigious award in the SEMI International Standards Program. The 2017 recipient is Bert Planting (ASML) who has been active in SEMI Standards for more than a decade, without interruption, in numerous international safety standardization projects, including:

  • S10 (Safety Guideline for Risk Assessment and Risk Evaluation Process) since 2005
  • S27 (Safety Guideline for the Contents of Environmental, Safety, and Health (ESH) Evaluation Reports) since 2010
  • S2 (Environmental, Health, and Safety Guideline for Semiconductor Manufacturing Equipment)
  • S25 (Safety Guideline for Hydrogen Peroxide Storage and Handling Systems) since 2012

Planting has co-chaired the North American (NA) chapter of the EHS Technical Committee since 2013, and also currently leads the S10 Revision Task Force and the S2 Interlock Reliability Task Force. As leader of the S10 Revision Task Force, he significantly improved S10’s usefulness and practicality. Under his strong direction, the risk assessment methodology of S10 (and by reference, S2) is now more objective, easier to implement, and better harmonized with major international Standards for safety risk assessment. As co-chair of the European EHS Technical Committee from 2005–2013, he successfully led a major S10 revision as well as development of a new Safety Guideline.

The North American SEMI International Standards Merit Award recognizes major contributions to the SEMI International Standards Program.  Award winners typically take on a very complex problem at the task force level, gain industry support, and drive the project to completion. This year two people received the award:

  • Yanli “Joyce” Chen (UCT) reactivated the Pressure Measurements Task Force during the SEMICON West 2014 Standards Meetings. This task force was chartered to develop a series of standardized performance definitions and test methods related to pressure measurement devices used in the semiconductor industry. Previous attempts to develop a standard test method for pressure transducers in gas delivery systems were not successful, but Chen reenergized the Task Force, putting tremendous effort into test apparatus development, test procedure optimization, data collection, and test results analysis, and conducting an extensive pressure transducer side-by-side evaluation project. This provided a solid base for the development of the new Standard, and SEMI F113, Test Method for Pressure Transducers Used in Gas Delivery Systems was approved and published. Chen has also been instrumental in updating several test methods for mass flow controllers and other components with benefits to the entire semiconductor industry.
  • John Visty (Salus Engineering International) has been the leader of the S2 Chemical Exposure Task Force since 2008; he is also the Task Force leader for the S2 Non-ionization and the S6 (Exhaust Ventilation) Revision. Leading these Task Forces resulted in revisions of SEMI S2, the most recognizable SEMI standard. The industrial hygiene section (regarding chemical exposure) in SEMI S2 was in need of clarification to ensure consistent technical interpretation by equipment suppliers, end-users and third-party evaluators.  Visty drove development through multiple ballot attempts, incorporating feedback from unfavorable ballots to reach industry consensus. In March 2017, revisions to SEMI S2 related to chemical exposure were approved and incorporated into SEMI S2. This clarification benefits the semiconductor industry by providing consistent chemical conformance criteria.

The North American SEMI International Standards Leadership Award recognizes outstanding leadership in guiding the SEMI International Standards Program. Brian Rubow (Cimetrix) has been an important contributor to SEMI Standards for many years and has demonstrated ongoing and increasing leadership.  Rubow became leader of the North American Diagnostic Data Acquisition (DDA) Task Force in 2008, leader of the NA GEM300 Task Force in 2010, co-chair of the NA Chapter of the Information and Control Committee in 2013, and vice-chair of the NA Regional Standards Committee in 2014. He continues to serve in all four of these positions. Among other accomplishments, Rubow drove the development of two important advances to bring semiconductor factory automation into the world of modern networks:

  • SEMI E172, SECS Equipment Data Dictionary (SEDD), which allows factory automation systems to adapt to the individual capabilities of each equipment type
  • SEMI E173, SECS Message Notation (SMN), which allows the content of factory messages to be specified in modern XML notation.

Rubow’s technical knowledge of factory connectivity solutions and outstanding leadership skills make a major contribution to the SEMI International Standards program.

For more information about SEMI International Standards, visit www.semi.org/en/Standards.

Solid State Technology and SEMI today announced the recipient of the 2017 “Best of West” Award — Microtronic Inc.— for its EAGLEview 5. The award recognizes important product and technology developments in the electronics manufacturing supply chain. Held in conjunction with SEMICON West, the largest and most influential electronics manufacturing exposition in North America, the Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

Microtronic’s EAGLEview 5 Macro Defect Management Platform is the new, yield-enhancing, breakthrough macro defect inspection platform that was developed ─ and deployed in production ─ through collaboration with several leading device manufacturers who wanted to standardize and unify wafer defect management throughout their fab. Innovations include: dramatically improved defect detection; level-specific sorting; and integration with manual microscopes. (Process Control, Metrology and Test Category; North Hall Booth #5467)

EAGLEview 5

When it comes to defects and contamination in the semiconductor manufacturing industry, most people tend to think of small, sub-nm defects at the transistor level. As important as those are, there are plenty of things that can go wrong and be seen at the macro level. Scratches, fingerprints, hot spots, spin defects, edge chips, poly haze, missing patterns, etc. are usually visible with the naked eye, perhaps aided by a green light or a microscope.

Fabs often do manual visual inspections, but it tends to be fairly random, only sampling a few wafers at a time. “You put some wafers on the screen, and you look sporadically at five, ten points on a few of the wafers,” notes Reiner Fenske, founder, CEO and president of Microtronic (Hawthorne, NY). “If you find something, typically it’s very difficult to feed that information forward. You might take a picture, but then where does that picture go?” It’s also difficult to compare defects, such as scratches, with previously seen defects. “How many scratches did you have last week? Does that scratch look like the one that you had last night?” Reiner asks.

An automated macro inspection tool – such as the newly released Microtronic EAGLEview 5, which will be running wafers at North Hall Booth #5467 at Semicon West this week — solves those problems, without requiring any recipes and quickly scanning every wafer in the cassette, noting and logging various defects. The EAGLEview 5 represents a big upgrade over the company’s previous offering. “There’s really a dramatic difference in terms of defect detection, defect resolution, defect sensitivity, and there’s no hit to throughput, so we’re still looking at 3,000 wafers a day, which is incredibly fast,” said Mike LaTorraca, Microtronic’s Chief Marketing Officer. Errol Akomer, Applications Director at Microtronic, adds that in addition to the higher resolution, it’s a much cleaner signal. “The signal-to- noise ratio is much better — there’s a 5X improvement in that as well,” he said. Internally developed software algorithms also results in less nuisance defects and increased defect detection.

With these new capabilities, LaTorraca said they’ve created a bridge between micro and macro, and manual and automated. “We can take manual microscope images and put them into the same software that runs on EagleView. We can start to integrate defect information and the actual defect images from the manual microscope world into our tool, and that gives the fab owners a much more unified approach, a better, more comprehensive view, to make better decisions,” he said.

EAGLEview 5 is equipped with advanced imaging technology, analytical software, robotics and a 4-cassette multi-size (100mm-300mm) wafer platform. EAGLEview ProcessGuard Client Software provides defect visualization, digital guard-banding, wafer randomization/slot positional analysis, together with integration with manual microscopes for fab-wide defect tracking and reporting.

Every wafer is automatically OCR read, imaged, 100% inspected and stored for any step throughout the manufacturing process providing a comprehensive, centralized record – or ‘waferbase’ – that is also compatible with the fab’s manual microscope inspection data providing a more integrated, wholistic view of both micro and macro defects.

EAGLEview 5 acts as a hub for defect management across the fab by integrating manual microscope inspection, high resolution EAGLEview wafer images. EAGLEview 5 replaces legacy manual/micro wafer inspection by automating and standardizing wafer inspection processes. Blindly sampling 5 sites on a wafer is no longer needed. The newly developed ProcessGuard microscope interface software records micro defect classifications. This coupled with on-board commonality analysis allows root cause to be determined for micro defects and breathes new life into existing microscope inspection strategies. EAGLEview was originally designed to be comparable to naked eye 1x green light inspection.   EAGLEview 5 shifts the line between a macro green light inspection and microscope inspection.

“You can put all the micro defects into our database in the same ways you did the macro, so you classify your macro defects and you classify all your micro defects,” Fenske explained. “Now you have a record of what, where, how many, and because we collect all the history of where the lot went to, which tools it went through, we can then use that information to do commonality studies to figure out which tool caused the problem. With the microscope, there hasn’t been that type of integration, so we can now take all of those legacy things everyone needs to use and actually give them a new life.”

By Pete Singer

In order to increase device performance, the semiconductor industry has slowly been implementing many new materials. From the 1960s through the 1990s, only a handful of materials were used, most notably silicon, silicon oxide, silicon nitride and aluminum. Soon, by 2020, more than 40 different materials will be in high-volume production, including more “exotic” materials such as hafnium, ruthenium, zirconium, strontium, complex III-Vs (such as InGaAs), cobalt and SiC.

These new materials create a variety of challenges with regard to process integration (understanding material interface issues, adhesion, stress, cross-contamination, etc.). But they also create new challenges when it comes to material handling.

“As we go through technology node advancements, people are looking at the potential of different materials on the wafer,” notes Clint Haris, Senior Vice President and General Manager of the Microcontamination Control Division at Entegris (Billerica, MA). “They’re looking at different chemicals that are required to clean those materials to reduce defects and improve their operational yield, and what we’re increasingly seeing is that fabs are concerned with the fact that contamination can be introduced in the fluid stream anywhere in that long process flow.”

Haris said that part of their mission at Entegris is to make sure that the entire supply chain – from the development of a chemistry at the supplier to its use on a wafer in a fab – is working in harmony, particularly with regard to any materials that might “touch” the chemicals. “Not only do you want to filter and purify things throughout the whole fluid flow,” he said, “but you want to have that last filtration right before the fluid touches the surface of the wafer.”

The goal of filtration is, of course, to remove contaminants and particles before they reach the wafer, but the exact purity required can be a moving target. “Today we’re seeing a lot of these materials and liquids, which have a parts per trillion purity level, but there’s a desire to move to parts per quadrillion,” Haris said. That’s the equivalent of one drop in all the water that flows over Niagra Falls in one day.

In addition to the filtration challenge of achieving that level, there’s the question of do the analytical tools exist to actually measure contaminants at that level. The answer – not yet. “It’s actually a real issue where some of the metrology tools cannot meet our customers’ needs at those levels, and so one of the things that we’ve done is we’ve developed some techniques internally to enhance the capability of metrology,” Haris said. “We also work on how we prepare our samples so you can detect contamination at those levels.” Because that level of detection is so difficult — in some cases impossible – Haris said fabs are increasingly putting additional filters at the process tool and at the dispense nozzle to “protect against the unknown.”

Earlier this year, Entegris introduced Purasol™, a first-of-its-kind solvent purifier that removes a wide variety of metal microcontaminants found in organic solvents used in ultraclean chemical manufacturing processes. Using tailored membrane technology, the purifier can efficiently remove both dissolved and colloidal metal contaminants from a wide variety of ultra-pure, polar and non-polar solvents. “One of the main things that our customers are seeing is a concern with metal contamination in the photo process that can result in particular defects (see Figure), such as bridge defects,” Haris explained. Increasingly, fabs are moving from just filtration (removing particles) to purification (removing ions and metals), he added.

Illustration of metal contamination inducing defects on lithography process.

Illustration of metal contamination inducing defects on lithography process.

Entegris also recently acquired W. L. Gore & Associates’ water and chemical filtration product line for microelectronics applications. “This is a Teflon-based product line, which is used in ultrapure water filtration for semiconductor fabs, but it’s also a product that we’re selling into some of the fine chemical purification markets for some of the chemistries that are brought into the fabs,” Haris said. “We are focused on new product development and M&A to enhance our capability to support our customers as they overcome these contamination challenges..”

By Pete Singer

At a SEMICON West press conference yesterday, SEMI released its Mid-year Forecast. Worldwide sales of new semiconductor manufacturing equipment are projected to increase 19.8 percent to total $49.4 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the market high of $47.7 billion set in 2000. In 2018, 7.7 percent growth is expected, resulting in another record-breaking year ─ totaling $53.2 billion for the global semiconductor equipment market.

Figure 1 copy

“It’s really an exciting time for the industry in the terms of technology, the growth in information and data and that’s all going to require semiconductors to enable that growth,” said Dan Tracy, senior director, IR&S at SEMI.

The average of various analysts forecast the semiconductor industry in general 12% growth for the year. “It’s a very good growth year for the industry,” Tracy said. “In January, the consensus was about 5% growth for the year and with the improvement in the market and the firmer pricing for memory we see an increase in the outlook for the market.”

The SEMI Mid-year Forecast predicts wafer processing equipment is anticipated to increase 21.7 percent in 2017 to total $39.8 billion. The other front-end segment, which consists of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, will increase 25.6 percent to total $2.3 billion. The assembly and packaging equipment segment is projected to grow by 12.8 percent to $3.4 billion in 2017 while semiconductor test equipment is forecast to increase by 6.4 percent, to a total of $3.9 billion this year.

“Based on the May outlook, we are looking at a record year in terms of tracking equipment spending. This is for new equipment, used equipment, and spending related to the facility that installed the equipment. It will be about a $49 billion market this year. Next year, it’s going to grow to $54 billion, so we have two years in a row of back to back record spending,” Tracy said.

In 2017, South Korea will be the largest equipment market for the first time. After maintaining the top spot for five years, Taiwan will place second, while China will come in third. All regions tracked will experience growth, with the exception of Rest of World (primarily Southeast Asia). South Korea will lead in growth with 68.7 percent, followed by Europe at 58.6 percent, and North America at 16.3 percent.

SEMI forecasts that in 2018, equipment sales in China will climb the most, 61.4 percent, to a total of $11.0 billion, following 5.9 percent growth in 2017. In 2018, South Korea, Taiwan, and China are forecast to remain the top three markets, with South Korea maintaining the top spot to total $13.4 billion. China is forecasted to become the second largest market at $11.0 billion, while equipment sales to Taiwan are expected to reach $10.9 billion.

Figure 2

James C. Morgan will be a special guest presenter during the SEMICON West keynote session this morning at the Yerba Buena Center. Morgan is a director emeritus and past president of SEMI, and was one of SEMI’s early supporters, back when the organization consisted of an “executive secretary, two clerks, and eight board members.”

Jim will be discussing the semiconductor equipment industry and introducing his autobiography and book of business insights, Applied Wisdom: Bad News Is Good News and Other Insights That Can Help Anyone Be a Better Manager. Dan Hutcheson, CEO of VLSI Research, says that he would “definitely put this book on the shelf next to Andy Grove’s Only the Paranoid Survive.”

Complimentary copies of the ebook will be made available to all attendees of this year’s Semicon West conference.

Jim Morgan will also be signing paperback books at booth 5630 in the North Hall at Moscone Center on June 11 and 12.

James C. Morgan ran Applied Materials for nearly three decades—one of the longest tenures of any Fortune 500 CEO. The company was near-bankrupt when he joined; when he retired as CEO in 2003, Applied was a multi-billion dollar global leader with more than 15,000 employees.

More recently he and his wife Becky founded the Northern Sierra Partnership, which fosters collaboration among conservation organizations in order to preserve and restore one of the world’s great mountain ranges.

appliedwisdombook

 

By Dave Lammers

Keynote speakers Terry Higashi of Tokyo Electron Ltd. and Tom Caulfield of GlobalFoundries took the stage at the Yerba Buena Theater Tuesday morning to predict major changes in the goals and operations of the semiconductor industry.

higashi2013_11_600px_0 ThomasCaufieldSized

In many ways, 2017 has been marked by intense interest in the capabilities of neural networks and other forms of artificial intelligence (AI). Higashi, now a corporate director at TEL, predicted that AI and virtual reality are among the applications that will propel demand for semiconductors “almost without limit.” Neuromorphic processors, the veteran TEL executive said, “are one of the promising devices to enhance human creativity. They will be improved step by step, just as logic and memory devices were improved.”

Looking toward a future in which AI and human skills combine to resolve problems, Higashi predicted that today’s Von Neumann-based architectures and neuromorphic device will complement each other. “Artificial intelligence solutions will be proposed, and the challenges and problems will be solved by scientists and engineers. The combination of Von Neumann and neuromorphic computing gets us closer to true intelligence,” he said.

AI also will play a role in enhancing the immersive experiences promised by virtual reality, experiences which visionaries have predicted but which thus far mankind “has never fully experienced.”

Higashi said that by combining VR and AI, “we can attain a suspension of disbelief, and simply enjoy the experience. If we can provide the technologies, consumers will experience excitement and a form of happiness.”

Caulfield, the general manager of the Malta fab near Albany, agreed with Higashi’s assessment that that the semiconductor industry is seeing “new buds” that will bloom into large semiconductor markets.

However, Caulfield said that to achieve anything like the rate of technological progress seen over the first half century of the semiconductor industry, companies and customers will have to take collaboration to new levels. And he offered the collaboration between GlobalFoundries and AMD as an example.

“Collaboration, potentially, is the biggest thing we need to do. We need strategic partnerships, and not only among semiconductor manufacturers but also with equipment suppliers.”

At its Malta fab, GlobalFoundries builds all of AMD’s leading-edge discrete graphics engines and CPUs. “The AMD and GlobalFoundries engineering teams are so embedded with each other, one can hardly tell” which company an engineer works for, he said.

Noting the resurgence of AMD, Caulfield said “we are all proud to be part of that partnership.” And he pointed to another collaboration, between Samsung and GlobalFoundries, which allows customers to take the same 14nm design and choose whether to manufacture it at Samsung’s Austin fab or at Malta. “Customers can run photomasks in Austin or in Malta, New York and have the product look the same,” he said.

Government role

In such a collaboration-rich business environment, governments also have a role to play, Caulfield said.

“Public-private investments must imply a return to governments as well as to companies. Otherwise, they send the wrong message.” By investing several billion dollars in the Malta fab, GlobalFoundries and the state of New York put to work the well-educated young people who otherwise would have left the state in search of technology jobs. When Malta began operations, only 20 percent of the staff were educated in New York. Now, fully half of the workforce has benefited from a New York education.

“We were exporting talent. Now, the workforce has great opportunity within the state,” he said.

Both Higashi and Caulfield said major challenges face the industry. Higashi noted that innovation will be required to keep flash memory costs under control. “As data is captured by sensors and is transferred via the appropriate networks and stored in data centers, demand for NAND will be high. We must make huge efforts to reduce the overall cost, as the semiconductor industry is expected to provide enough volumes to support the Internet of Things.”

Caulfield said the performance of logic transistors has struggled to keep pace, even as density increases have continued. When the industry moved from 28nm to 14nm technologies, performance increased by fully 50 percent. But from 14nm to 10nm, speeds improved by about 18 percent, making shrinks primarily a cost improvement.

With the industry now focused on brining 7nm logic to the market, the question arises whether 5nm CMOS will provide enough performance to justify that node. While the jury on technology scaling is still out, Caulfield said the industry may have to move to gate all around (GAA) structures, or to non-silicon channel materials, in order to gain the kinds of performance improvements that customers expect from a new node.

Higashi said systems must get faster. “Real-time processing is crucial in the cyber world. And with robotic hands, there should be no delays in physical operations.”

“Memory, logic, and sensing make it possible for AI systems to solve problems much faster than a team of geniuses. We are now in a new era, one of super integration. In addition to improved specialty devices – based on logic, memory, and sensors – we must take these separate devices and put them together into fully integrated systems. It is time to make a pizza, with some of the best ingredients,” he said.

9:05 am – 9:20 am
Special Guest: James. C. Morgan
Jim talks about his new book, Applied Wisdom
Yerba Buena Theater

9:35 am – 10:05 am
Big Data in Autonomous Driving
Katherine S. Winter, Intel
Yerba Buena Theater

10:30 am – 12:30 pm
Enabling the IoT
Innovative Technologies to Advance the Connected World
Meet the Expert Theater, Moscone West

12:30 am –2:00 pm
Smart Automotive 1
The Future of Smart & Connected Self-driving Cars
Moscone North, TechXPOT North

2:00 pm – 3:00 pm
Executive Panel
Meeting the Challenges of the 4th Industrial Revolution along the Microelectronics Supply Chain
Yerba Buena Theater

2:00 pm – 5:00 pm
Advanced Packaging Technologies Enabling Advanced Applications
Moscone West, TechXPOT West

3:00 pm – 4:30 pm
Smart Manufacturing
Machine learning in design, inspection, process modeling and decision making
Meet the Expert Theater, Moscone West