Category Archives: Semiconductors

The Semiconductor Industry Association (SIA) released the following statement today from SIA president & CEO John Neuffer in support of the corporate tax reform framework released today by leaders in the Trump Administration and Congress. The proposal is expected to be considered by Congress in the coming weeks.

“Over the past three decades, the U.S. semiconductor industry has unleashed tremendous innovations that have transformed America’s economic, technological, and national security landscape. America’s corporate tax system, meanwhile, has remained largely unchanged, leaving U.S. businesses at a disadvantage to their overseas competitors.

“The tax reform framework is a step forward to make the U.S. corporate tax system more competitive and allow U.S. semiconductor companies to continue to grow and innovate here at home. The plan would advance the U.S. semiconductor industry’s core priorities for tax reform: a lower, globally competitive rate, a modern international tax system, and strong incentives for research and innovation.

“While there are many details of importance to our industry that need to be fleshed out, we support the plan as a framework for advancing corporate tax reform.  We look forward to working with Congress and the Administration to enact corporate tax reform that makes the United States more globally competitive and boosts U.S. leadership in semiconductor research, design, and manufacturing.”

Perovskite solar cells (PSCs) can offer high light-conversion efficiency with low manufacturing costs. But to be commercially viable, perovskite films must also be durable and not degrade under solar light over time. EPFL scientists have now greatly improved the operational stability of PSCs, retaining more than 95% of their initial efficiencies of over 20% under full sunlight illumination at 60oC for more than 1000 hours. The breakthrough, which marks the highest stability for perovskite solar cells, is published in Science.

Challenges of stability

Conventional silicon solar cells have reached a point of maturation, with efficiencies plateauing around 25% and problems of high-cost manufacturing, heavyweight, and rigidity has remained largely unresolved. On the contrary, a relatively new photovoltaic technology based on perovskite solar cells has already achieved more than 22% efficiency.

Given the vast chemical versatility, and the low-cost processability of perovskite materials, the PSCs hold the promise to lead the future of photovoltaic technology by offering cheap, light weight and highly efficient solar cells. But until now, only highly expensive, prototype organic hole-transporting materials (HTMs,selectively transporting positive charges in a solar cell) have been able to achieve power-conversion efficiencies over 20%. And by virtue of their ingredients, these hole-transporting materials adversely affect the long-term operational stability of the PSC.

Therefore, investigating cheap and stable hole transporters that produce equally high efficiencies is in great demand to enable large-scale deployment of perovskite solar cells. Among various inorganic HTMs, cuprous thiocyanate (CuSCN) stands out as a stable, efficient and cheap candidate ($0.5/gr versus $500 /gr for the commonly used spiro-OMeTAD). But previous attempts to use CuSCN as a hole transporter in perovskite solar cells have yielded only moderately stabilized efficiencies and poor device stability, due to problems associated with depositing a high-quality CuSCN layer atop of the perovskite film, as wells as the chemical instability of the CuSCN layer when integrated into a perovskite solar cell.

A stable solution

Now, researchers at Michael Grätzel’s lab at EPFL, in a project led by postdocs Neha Arora and M. Ibrahim Dar, have introduced two new concepts that overcome the major shortcomings of CuSCN-based perovskite solar cells. First, they developed a simple dynamic solution-based method for depositing highly conformal, 60-nm thick CuSCN layers that allows the fabrication of perovskite solar cells with stabilized power-conversion efficiencies exceeding 20%. This is comparable to the efficiencies of the best performing, state-of-the-art spiro-OMeTAD-based perovskite solar cells.

Second, the scientists introduced a thin spacer layer of reduced graphene oxide between the CuSCN and a gold layer. This innovation allowed the perovskite solar cells to achieve excellent operational stability, retaining over 95% of their initial efficiency while operating at a maximum power point for 1000 hours under full-sun illumination at 60 °C. This surpasses even the stability of organic HTM-based perovskite solar cells that are heavily researched and have recently dominated the field.

The researchers also discovered that the instability of the perovskite devices originates from the degradation of CuSCN/gold contact during the solar cell’s operation.

“This is a major breakthrough in perovskite solar-cell research and will pave the way for large-scale commercial deployment of this very promising new photovoltaic technology,” says Michael Grätzel. “It will benefit the numerous scientists in the field that have been intensively searching for a material that could replace the currently used, prohibitively expensive organic hole-transporters,” adds M. Ibrahim Dar.

OEM Group announced today a Post-Dice Clean solution on the proven Cintillio™ Batch Spray platform following plasma and laser dicing methods. Designed specifically to remove residue and particles left behind from these dicing methods, OEM Group’s Cintillio™ SST (Spray Solvent Tool) and Cintillio™ Eco-Clean systems utilize their patented Enhanced Spray Technology (EST) to deliver process improvement through uniform media flow with a nozzle-per-wafer concept ensuring uniform flow and increased rinse efficiency.

After wafers are singulated prior to “pick and place,” the conventional method of cleaning is by water rinsing; however, some singulation methods, particularly plasma and laser, may leave behind residues that water cannot clean. Slag, polymers, and other residues impede device performance and may cause corrosion or affect downstream processes. The Cintillio™ post-dice clean process successfully removes these residues to maintain final device performance. Chris Forgey, CTO for OEM Group says, “We’re pleased to leverage our patented Ozone process specifically for post dice clean applications, delivering value and superior process capability for this specific application.”

Along with the patented Enhanced Spray Technology (EST), both platforms adapt wafer carriers and rotors to hold multiple “diced wafer-on-tape-on-frame” substrates, delivering greater throughput, reduced chemical utilization, space efficient footprint, and excellent overall performance. According to OEM Group Applications Lab Manager, Joshua Levinson, Ph.D., “Any device manufacturer who performs back-end processing of wafers and who employs wafer singulation to create diced substrates will benefit from our solutions. Batch processing also reduces the number of cleaning tools required in a fab and lowers overall cost of ownership, waste generation, and DI water usage.”

With global headquarters in metro Phoenix, Arizona and additional sites throughout the North America, Europe, Japan and Asia, OEM Group, LLC is a semiconductor capital equipment manufacturer and innovator in new and remanufactured 75mm–200mm tools and services.

SK Hynix Inc. (or “the Company“, www.skhynix.com) announced its board of directors yesterday approved its plan to participate in a Bain Capital-led consortium that plans to purchase Toshiba Corporation’s memory chip unit, Toshiba Memory Corporation (or “TMC“). The Company will invest 395 billion yen (4 trillion won) in the consortium’s estimated 2 trillion yen of total investment.

SK Hynix is a part of a group of investors led by Bain Capital Private Equity that includes several Japanese and a number of U.S. companies. The Bain-led consortium will hold 49.9 percent stake in TMC, while Toshiba will hold 40.2 percent and Japan’s Hoya Corp. will own 9.9 percent.

SK Hynix plans to finance 129 of its total 395 billion yen via convertible bonds that could allow it to take an equity stake of up to 15 percent in the future. The remaining 266 billion yen is to put in a fund established by Bain Capital as a limited partner, which would help the Company enjoy capital gains when the TMC is listed.

The Bain-led consortium including SK Hynix will make its best endeavors to finalize the deal by March 2018.

Solar-Tectic LLC (“ST”) announced today that a patent application for a method of making III-V thin-film tandem solar cells with high performance has been allowed by the US Patent and Trademark Office. The patent, the first ever for a thin III-V layer on crystalline silicon thin-film, covers group III-V elements such as Gallium Arsenide (GaAs), and Indium Gallium Phosphide (InGaP), for the top layer, as well as all inorganic materials, including, silicon, germanium, etc., for the bottom layer.  Group III-V compounds such as Gallium Arsenide (GaAs) are proven photovoltaic materials with high efficiencies but until now have been cost prohibitive because high quality III-V material such as GaAs is expensive. Moreover, the cost of substrates on which to grow III-V materials, such as germanium, which is known to be an ideal material, has kept the technology from market entry. In the breakthrough technology here, ultra-thin films of III-V materials and silicon (or germanium) replace expensive, thicker wafers thereby lowering the costs dramatically. The inventor is Ashok Chaudhari, CEO of Solar-Tectic LLC.

III-V tandem (or multi-junction) cells built on wafers such as silicon are currently being developed in labs, with high efficiencies of around ~30%.  The highest dual-junction cell efficiency (32.8%) came from a tandem cell that stacked a layer of gallium arsenide (GaAs) atop crystalline silicon. Manufacturing costs are expensive especially if a germanium wafer is used as the bottom material in the two layer tandem structure.  In order to compete with low cost silicon wafer technology which is 90% of the global solar panel market, efficiencies must not only be as high as silicon wafers or greater (21.7% and 26.7% are lab records for poly- and monocrystalline silicon wafer cells, respectively), but manufacturing costs must also be lower. This is achievable in the Solar-Tectic LLC patented technology, which uses common industrial manufacturing processes and at low temperature. There is no wafer involved which saves material and energy; instead a thin film allows for precise control of growth parameters. A glass substrate instead of wafer also allows for a bifacial cell design for increased efficiency. A cost effective ~30% efficient III-V tandem solar cell in today’s market would revolutionize the solar energy industry by dramatically reducing the balance of system (BoS) costs, and thereby reduce the need for fossil fuel generated electricity. Silicon wafer technology based on polycrystalline or monocrystalline silicon could become obsolete.

Importantly, the entire patented process for the Solar-Tectic LLC III-V tandem cell can be environmentally friendly since non-toxic metals can be used to deposit the crystalline thin-film materials for both the bottom layer in the tandem configuration as well as in the top, III-V, layer.

The technology also has great promise for LED manufacturing using for example Gallium Nitride.

A “Tandem Series” of solar cell technologies has been launched by Solar-Tectic LLC, which includes a variety of different proven semiconductor photovoltaic materials for the top layer on silicon and/or germanium bottom layers. Recently patents for a tin perovskite and germanium perovskite thin-film tandem solar cell were also granted.

The ITC ruling on September 22 means that it is likely that tariffs will be imposed on crystalline silicon wafers sold in the US. These tariffs will not apply to thin-film solar cell technology, such as ST’s.

Silicon Mobility announced today the opening of an office in Burlingame, CA. The office is located close to San Francisco international airport at the gate entry of the Silicon Valley. Silicon Mobility’s Bay Area office will be headed by Mr. David Fresneau, co-founder and Vice President of Marketing and Business Development, and will lead Silicon Mobility’s corporate marketing and business development activities.

“The Silicon Valley sees a growing presence of automotive OEMs and Tiers 1 attracted by the unique concentration of high-technology companies and software excellence” says Bruno Paucard, President and CEO of Silicon Mobility. “Being full-time present in this new land for automotive will help to catalyze our contribution to the cars’ digital and electric revolution”.

In addition to powertrain electrification, Silicon Mobility foresees its deployment into the broader electrification area (Electric Power Steering, Braking, etc.) and the processor centralization in the car’s E/E architecture, in particular with regard to ADAS data fusion, functions grouping and domain control. By choosing to open an office in the Bay area, Silicon Mobility fosters its global expansion strategy helping the company to build long-term partnerships with the local ecosystem and preparing Silicon Mobility’s future.

Silicon Mobility designs, develops and sells flexible, real-time, safe and open semiconductor solutions for the automotive industry used to increase energy efficiency and reduce pollutant emissions while keeping passengers safe.

Band gaps, made to order


September 28, 2017

Control is a constant challenge for materials scientists, who are always seeking the perfect material — and the perfect way of treating it — to induce exactly the right electronic or optical activity required for a given application.

One key challenge to modulating activity in a semiconductor is controlling its band gap. When a material is excited with energy, say, a light pulse, the wider its band gap, the shorter the wavelength of the light it emits. The narrower the band gap, the longer the wavelength.

As electronics and the devices that incorporate them — smartphones, laptops and the like — have become smaller and smaller, the semiconductor transistors that power them have shrunk to the point of being not much larger than an atom. They can’t get much smaller. To overcome this limitation, researchers are seeking ways to harness the unique characteristics of nanoscale atomic cluster arrays — known as quantum dot superlattices — for building next generation electronics such as large-scale quantum information systems. In the quantum realm, precision is even more important.

New research conducted by UC Santa Barbara’s Department of Electrical and Computer Engineering reveals a major advance in precision superlattices materials. The findings by Professor Kaustav Banerjee, his Ph.D. students Xuejun Xie, Jiahao Kang and Wei Cao, postdoctoral fellow Jae Hwan Chu and collaborators at Rice University appear in the journal Nature Scientific Reports.

Their team’s research uses a focused electron beam to fabricate a large-scale quantum dot superlattice on which each quantum dot has a specific pre-determined size positioned at a precise location on an atomically thin sheet of two-dimensional (2-D) semiconductor molybdenum disulphide (MoS2). When the focused electron beam interacts with the MoS2 monolayer, it turns that area — which is on the order of a nanometer in diameter — from semiconducting to metallic. The quantum dots can be placed less than four nanometers apart, so that they become an artificial crystal — essentially a new 2-D material where the band gap can be specified to order, from 1.8 to 1.4 electron volts (eV).

This is the first time that scientists have created a large-area 2-D superlattice — nanoscale atomic clusters in an ordered grid — on an atomically thin material on which both the size and location of quantum dots are precisely controlled. The process not only creates several quantum dots, but can also be applied directly to large-scale fabrication of 2-D quantum dot superlattices. “We can, therefore, change the overall properties of the 2-D crystal,” Banerjee said.

Each quantum dot acts as a quantum well, where electron-hole activity occurs, and all of the dots in the grid are close enough to each other to ensure interactions. The researchers can vary the spacing and size of the dots to vary the band gap, which determines the wavelength of light it emits.

“Using this technique, we can engineer the band gap to match the application,” Banerjee said. Quantum dot superlattices have been widely investigated for creating materials with tunable band gaps but all were made using “bottom-up” methods in which atoms naturally and spontaneously combine to form a macro-object. But those methods make it inherently difficult to design the lattice structure as desired and, thus, to achieve optimal performance.

As an example, depending on conditions, combining carbon atoms yields only two results in the bulk (or 3-D) form: graphite or diamond. These cannot be ‘tuned’ and so cannot make anything in between. But when atoms can be precisely positioned, the material can be designed with desired characteristics.

“Our approach overcomes the problems of randomness and proximity, enabling control of the band gap and all the other characteristics you might want the material to have — with a high level of precision,” Xie said. “This is a new way to make materials, and it will have many uses, particularly in quantum computing and communication applications. The dots on the superlattice are so close to each other that the electrons are coupled, an important requirement for quantum computing.”

The quantum dot is theoretically an artificial “atom.” The developed technique makes such design and “tuning” possible by enabling top-down control of the size and the position of the artificial atoms at large scale.

To demonstrate the level of control achieved, the authors produced an image of “UCSB” spelled out in a grid of quantum dots. By using different doses from the electron beam, they were able to cause different areas of the university’s initials to light up at different wavelengths.

“When you change the dose of the electron beam, you can change the size of the quantum dot in the local region, and once you do that, you can control the band gap of the 2-D material,” Banerjee explained. “If you say you want a band gap of 1.6 eV, I can give it to you. If you want 1.5 eV, I can do that, too, starting with the same material.”

This demonstration of tunable direct band gap could usher a new generation of light-emitting devices for photonics applications.

Reno Sub-Systems (Reno), a developer of high-performance radio frequency (RF) matching networks, RF power generators and gas flow management systems for semiconductor manufacturing, today announced it has closed its Series C funding. Samsung Venture Investment Corporation led the round. New investors Samsung Venture Investment Corp., Hitachi High-Technologies Corporation and SK hynix all join Reno’s premier list of strategic investors. Existing investors Intel Capital, Lam Research and MKS Instruments also participated in this funding round.

“Our list of strategic investors now includes the venture arms of three of the top five largest semiconductor manufacturers, two out of four of the largest etch tool providers, and a key subsystems supplier,” said Bob MacKnight, CEO of Reno Sub-Systems. “Our holistic approach to precision subsystem process control across RF as well as flow technologies offers clear differentiation from competitive approaches. Our new investors are motivated to participate to secure access to our innovative technologies, to enhance their manufacturing operations or product offerings.”

“We saw high value in Reno’s technology, so it only made sense for us to pursue an investment,” said Dr. Dong-Su Kim, vice president of Samsung Venture Investment Corp.

“The new capabilities that Reno’s subsystems provide will add to our competitive strengths,” said Craig Kerkove, president & CEO of Hitachi High-Technologies America.

“Greater precision and repeatability of processing are key to future device geometries,” said Heejin Chung, head of SK hynix’s Venture Investment. “Reno’s subsystems can help us achieve that.”

The additional funding will support continued development of the technology to enable leading-edge silicon manufacturing technology nodes in high-volume production. “The C-round will allow us to support our rapidly growing number of deployments and enable high-volume manufacturing of our systems to support our recent platform wins,” said MacKnight.

The company also announced that it has secured several additional platform design wins for its Electronically Variable Capacitor (EVC™) impedance matching networks and has been qualified by a leading OEM.

Since the 2009 semiconductor downturn and strong 2010 recovery year, power transistor sales have been rocked by market volatility, falling in three of the last five years because of inventory corrections and drawdowns by systems makers worried about ongoing economic weakness and price erosion in some product categories. After recovering from a 7% drop in 2015, power transistor sales grew 5% in 2016 to $12.9 billion and are forecast to set a new record high this year with worldwide revenues rising 6% to $13.6 billion, according to IC Insights’ 2017 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discrete Semiconductors.

The expected 2017 growth in power transistor sales will be the first back-to-back annual increase in this semiconductor market segment in six years, and that will push dollar volumes past the current record high of $13.5 billion set in 2011. In 2012 and 2013, power transistors suffered their first back-to-back annual sales decline in more than three decades—dropping 8% and 6%, respectively—after rising 12% in 2011 and surging 44% in the 2010 recovery from the 2009 downturn year. The power transistor market then rebounded in 2014 with a strong 14% increase, only to drop 7% in 2015. In 2016, this semiconductor discretes market category began to stabilize and is expected to continue expanding at a modest rate in the next several years, based on IC Insights’ O-S-D Report forecast (Figure 1).

Power transistors are the primary growth engine in the $23 billion discrete semiconductor market because they play a vital role in controlling and conditioning electricity for all types of electronics—including a growing number of battery-operated systems. Worldwide efforts to reduce the waste of power in electric utility grids have significantly increased the importance of power transistors in consumer, commercial, and industrial systems. Renewable-energy applications (e.g., wind and solar systems) as well as electric and hybrid vehicles have also become important applications for power transistors in the last 15 years.

Figure 1

Figure 1

However, volatility in the first half of this decade resulted in an uncharacteristic drop in market size for power transistors during the last five years.  Between 2011 and 2016, power transistor sales fell by a compound annual growth rate of -0.9% compared to a 25-year historical annual average increase of 6.4% (between 1991 and 2016).  The 2017 O-S-D Report is projecting that worldwide power transistor sales will grow by a CAGR of 4.2% between 2016 and 2021, reaching $15.8 billion in the final year of the forecast.

All power transistor technology categories are expected to register sales growth in 2017 with MOS field effect transistor (FET) products increasing 6% to nearly $7.7 billion, insulated-gate bipolar transistor (IGBT) products also rising 6% to $4.1 billion, and bipolar junction transistor products growing 4% to about $875 million.  RF/microwave power transistors and module sales are forecast to rise 3% in 2017 to $960 million, according to the O-S-D Report.

SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it has joined the TSMC (NYSE: TSM) IP Alliance Program, part of the TSMC Open Innovation Platform, which accelerates innovation in the semiconductor design community. As an alliance member, SiFive’s RISC-V based Coreplex IP are made available to its customers to reduce time-to-market, increase return on investment and reduce waste in the manufacturing process.

With the significant increases in non-recurring engineering and design costs required to bring to life new silicon designs, TSMC’s IP Alliance Program makes it easier for fabless chipmakers to innovate and produce custom semiconductors. By participating in the TSMC IP Alliance Program, SiFive becomes the first RISC-V solution provider to make its IP readily available for fabless chipmakers leveraging the industry’s most comprehensive semiconductor IP portfolio.

“Acceptance into the TSMC IP Alliance is an honor and a significant validation not only of SiFive, but of the RISC-V architecture as a whole,” said Jack Kang, vice president of Product and Business Development, SiFive. “Having the SiFive Coreplex IP platform available through the program makes designing a chip based on the latest in open source hardware even easier. We look forward to continued collaboration with TSMC and the other members of the IP Alliance ecosystem.”

“The TSMC Open Innovation Platform forms the center of our open innovation model that addresses the needs of our customers looking to reduce design time and speed time-to-market,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The addition of SiFive’s IP to the TSMC IP catalog will streamline the process of fabricating custom silicon designs based on the RISC-V implementation.”

SiFive was founded by the inventors of RISC-V – Andrew Waterman, Yunsup Lee and Krste Asanovic – with a mission to democratize access to custom silicon. In its first six months of availability, more than 1,000 HiFive1 software development boards have been purchased and delivered to developers in over 40 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products, started shipping the industry’s first RISC-V SoC in November 2016 and announced the availability of its Coreplex RISC-V based IP earlier this year. SiFive’s innovative “study, evaluate, buy” licensing model dramatically simplifies the IP licensing process, and removes traditional road blocks that have limited access to customized, leading edge silicon.